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clean, spaces, alignement... nw
This commit is contained in:
RobertoFresca
parent
9bdeedb52b
commit
23eeecbfb6
@ -1,6 +1,6 @@
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// license:???
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// copyright-holders:Roberto Fresca
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/******************************************************************************
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/**************************************************************************************************
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MEGA DOUBLE POKER (BLITZ SYSTEM INC.)
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-------------------------------------
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@ -15,7 +15,7 @@
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* Mega Double Poker (conversion kit, set 2). 1990, Blitz System Inc.
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*******************************************************************************
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***************************************************************************************************
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Mega Double Poker is distributed as standalone PCB, or as upgrade kit for
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modified Golden Poker boards. The game has an undumped MC68705P5 MCU, so
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@ -23,8 +23,7 @@
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properly dumped.
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*******************************************************************************
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***************************************************************************************************
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Hardware Notes (Mega Double Poker, kit):
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@ -97,7 +96,6 @@
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|__________________________________________________________________________|
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PCB Layout: Daughterboard.
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________________________________________________________
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| :::::::::::::::::::: |
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@ -141,7 +139,6 @@
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|________________________________________________|
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Connections... (pins in parenthesis)
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------------------------------------
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@ -154,91 +151,70 @@
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system accuratelly.
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CPU R6502AP (U6)
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.--------\ /--------.
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MCU (01-05-07), MEGA-2 (14-20), MEGA-3 (14-20) ---|01 VSS ' /RES 40|---
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MCU (02) ---|02 RDY PH2(O) 39|---
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MCU (04) ---|03 PH1(O) /SO 38|---
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---|04 /IRQ PH0(I) 37|---
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---|05 (NC) (NC) 36|---
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MCU (03-06), MEGA-2 (01-27-28), MEGA-3 (01-28) ---|06 /NMI (NC) 35|---
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---|07 SYNC R/W 34|---
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MCU (03-06), MEGA-2 (01-27-28), MEGA-3 (01-28) ---|08 VCC D0 33|--- MEGA-2 (11)
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MEGA-2 (10), MEGA-3 (10) ---|09 A0 D1 32|--- MEGA-2 (12)
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MEGA-2 (09), MEGA-3 (09) ---|10 A1 D2 31|---
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MEGA-2 (08), MEGA-3 (08) ---|11 A2 D3 30|--- MEGA-2 (15)
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MEGA-2 (07), MEGA-3 (07) ---|12 A3 D4 29|--- MEGA-2 (16)
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MEGA-2 (06), MEGA-3 (06) ---|13 A4 D5 28|--- MEGA-2 (17)
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MEGA-2 (05), MEGA-3 (05) ---|14 A5 D6 27|--- MEGA-2 (18)
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MEGA-2 (04), MEGA-3 (04) ---|15 A6 D7 26|--- MEGA-2 (19)
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MEGA-2 (03), MEGA-3 (03) ---|16 A7 A15 25|---
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MEGA-2 (25), MEGA-3 (25) ---|17 A8 A14 24|---
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MEGA-2 (24), MEGA-3 (24) ---|18 A9 A13 23|--- MEGA-2 (26), MEGA-3 (26)
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MEGA-2 (21), MEGA-3 (21) ---|19 A10 A12 22|--- MEGA-2 (02), MEGA-3 (02)
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MEGA-2 (23), MEGA-3 (23) ---|20 A11 VSS 21|--- MCU (01-05-07), MEGA-2 (14-20), MEGA-3 (14-20)
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'-------------------'
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CPU R6502AP (U6)
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.--------\ /--------.
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MCU (01-05-07), MEGA-2 (14-20), MEGA-3 (14-20) --|01 VSS ' /RES 40|--
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MCU (02) --|02 RDY PH2(O) 39|--
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MCU (04) --|03 PH1(O) /SO 38|--
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--|04 /IRQ PH0(I) 37|--
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--|05 (NC) (NC) 36|--
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MCU (03-06), MEGA-2 (01-27-28), MEGA-3 (01-28) --|06 /NMI (NC) 35|--
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--|07 SYNC R/W 34|--
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MCU (03-06), MEGA-2 (01-27-28), MEGA-3 (01-28) --|08 VCC D0 33|-- MEGA-2 (11)
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MEGA-2 (10), MEGA-3 (10) --|09 A0 D1 32|-- MEGA-2 (12)
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MEGA-2 (09), MEGA-3 (09) --|10 A1 D2 31|--
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MEGA-2 (08), MEGA-3 (08) --|11 A2 D3 30|-- MEGA-2 (15)
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MEGA-2 (07), MEGA-3 (07) --|12 A3 D4 29|-- MEGA-2 (16)
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MEGA-2 (06), MEGA-3 (06) --|13 A4 D5 28|-- MEGA-2 (17)
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MEGA-2 (05), MEGA-3 (05) --|14 A5 D6 27|-- MEGA-2 (18)
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MEGA-2 (04), MEGA-3 (04) --|15 A6 D7 26|-- MEGA-2 (19)
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MEGA-2 (03), MEGA-3 (03) --|16 A7 A15 25|--
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MEGA-2 (25), MEGA-3 (25) --|17 A8 A14 24|--
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MEGA-2 (24), MEGA-3 (24) --|18 A9 A13 23|-- MEGA-2 (26), MEGA-3 (26)
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MEGA-2 (21), MEGA-3 (21) --|19 A10 A12 22|-- MEGA-2 (02), MEGA-3 (02)
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MEGA-2 (23), MEGA-3 (23) --|20 A11 VSS 21|-- MCU (01-05-07), MEGA-2 (14-20), MEGA-3 (14-20)
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'-------------------'
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MCU MC68705P5S (U1)
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.--------\ /--------.
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MEGA-2 (12, 20), MEGA-3 (12, 20) ---|01 VSS ' /RES 28|---
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CPU (02) ---|02 /INT PA7 27|---
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MEGA-2 (01, 28), MEGA-3 (01, 28) ---|03 VCC PA6 26|---
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CPU (03) ---|04 EXTAL PA5 25|---
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MEGA-2 (14, 20), MEGA-3 (14, 20) ---|05 XTAL PA4 24|---
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MEGA-2 (27, 28), MEGA-3 (27, 28) ---|06 VPP PA3 23|---
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MEGA-2 (14, 20), MEGA-3 (14, 20) ---|07 TIMER PA2 22|---
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---|08 PC0 PA1 21|---
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---|09 PC1 PA0 20|---
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---|10 PC2 PB7 19|---
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---|11 PC3 PB6 18|---
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---|12 PB0 PB5 17|---
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---|13 PB1 PB4 16|---
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---|14 PB2 PB3 15|---
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'-------------------'
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MCU MC68705P5S (U1)
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.--------\ /--------.
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MEGA-2 (12, 20), MEGA-3 (12, 20) --|01 VSS ' /RES 28|--
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CPU (02) --|02 /INT PA7 27|--
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MEGA-2 (01, 28), MEGA-3 (01, 28) --|03 VCC PA6 26|--
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CPU (03) --|04 EXTAL PA5 25|--
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MEGA-2 (14, 20), MEGA-3 (14, 20) --|05 XTAL PA4 24|--
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MEGA-2 (27, 28), MEGA-3 (27, 28) --|06 VPP PA3 23|--
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MEGA-2 (14, 20), MEGA-3 (14, 20) --|07 TIMER PA2 22|--
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--|08 PC0 PA1 21|--
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--|09 PC1 PA0 20|--
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--|10 PC2 PB7 19|--
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--|11 PC3 PB6 18|--
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--|12 PB0 PB5 17|--
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--|13 PB1 PB4 16|--
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--|14 PB2 PB3 15|--
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'-------------------'
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MEGA-2 27C256 (U2)
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.-------\ /-------.
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---|01 VPP ' VCC 28|---
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---|02 A12 A14 27|---
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---|03 A7 A13 26|---
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---|04 A6 A8 25|---
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---|05 A5 A9 24|---
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---|06 A4 A11 23|---
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---|07 A3 /OE 22|---
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---|08 A2 A10 21|---
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---|09 A1 /CE 20|--- CPU (01-21), MCU (01-05-07), MEGA-3 (14-20)
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---|10 A0 D7 19|---
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---|11 D0 D6 18|---
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---|12 D1 D5 17|---
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---|13 D2 D4 16|---
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CPU (01-21), MCU (01-05-07), MEGA-3 (14-20) ---|14 GND D3 15|---
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'-----------------'
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MEGA-2 27C256 (U2) MEGA-3 27C256 (U3)
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.-------\ /-------. .-------\ /-------.
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--|01 VPP ' VCC 28|-- --|01 VPP ' VCC 28|--
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--|02 A12 A14 27|-- --|02 A12 A14 27|--
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--|03 A7 A13 26|-- --|03 A7 A13 26|--
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--|04 A6 A8 25|-- --|04 A6 A8 25|--
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--|05 A5 A9 24|-- --|05 A5 A9 24|--
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--|06 A4 A11 23|-- --|06 A4 A11 23|--
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--|07 A3 /OE 22|-- --|07 A3 /OE 22|--
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--|08 A2 A10 21|-- .-- MCU (01-05-07) --|08 A2 A10 21|-- .-- MCU (01-05-07)
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--|09 A1 /CE 20|----+-- MEGA-3 (14-20) --|09 A1 /CE 20|----+-- MEGA-2 (14-20)
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--|10 A0 D7 19|-- '-- CPU (01-21) --|10 A0 D7 19|-- '-- CPU (01-21)
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--|11 D0 D6 18|-- --|11 D0 D6 18|--
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--|12 D1 D5 17|-- --|12 D1 D5 17|--
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MCU (01-05-07) --. --|13 D2 D4 16|-- MCU (01-05-07) --. --|13 D2 D4 16|--
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MEGA-3 (14-20) --+----|14 GND D3 15|-- MEGA-2 (14-20) --+----|14 GND D3 15|--
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CPU (01-21) --' '-----------------' CPU (01-21) --' '-----------------'
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MEGA-3 27C256 (U3)
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.-------\ /-------.
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---|01 VPP ' VCC 28|---
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---|02 A12 A14 27|---
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---|03 A7 A13 26|---
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---|04 A6 A8 25|---
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---|05 A5 A9 24|---
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---|06 A4 A11 23|---
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---|07 A3 /OE 22|---
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---|08 A2 A10 21|---
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---|09 A1 /CE 20|--- CPU (01-21), MCU (01-05-07), MEGA-3 (14-20)
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---|10 A0 D7 19|---
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---|11 D0 D6 18|---
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---|12 D1 D5 17|---
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---|13 D2 D4 16|---
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CPU (01-21), MCU (01-05-07), MEGA-3 (14-20) ---|14 GND D3 15|---
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'-----------------'
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*******************************************************************************
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***************************************************************************************************
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------------------------------------------------
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*** Memory Map (from Golden Poker hardware) ***
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@ -261,9 +237,7 @@
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$8000 - $FFFF ; Mirrored from $0000 - $7FFF due to lack of A15 line connection.
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********************************************************************************
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****************************************************************************************************
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Driver Updates:
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--------------
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@ -278,10 +252,7 @@
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* Added partial docs and diagrams about the CPU/MCU/ROMs addressing.
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* Added debug and technical notes.
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*******************************************************************************/
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***************************************************************************************************/
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#define MASTER_CLOCK XTAL_10MHz
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#define CPU_CLOCK (MASTER_CLOCK/16)
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@ -323,12 +294,10 @@ public:
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};
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/*********************************************
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* Video Hardware *
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*********************************************/
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WRITE8_MEMBER(blitz_state::megadpkr_videoram_w)
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{
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m_videoram[offset] = data;
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@ -351,7 +320,6 @@ TILE_GET_INFO_MEMBER(blitz_state::get_bg_tile_info)
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---- ---x tiles extended address (MSB).
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xx-- ---- unused.
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*/
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int attr = m_colorram[tile_index];
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int code = ((attr & 1) << 8) | m_videoram[tile_index];
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int bank = (attr & 0x02) >> 1; /* bit 1 switch the gfx banks */
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@ -447,10 +415,7 @@ WRITE8_MEMBER(blitz_state::mux_w)
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}
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/***** Lamps wiring *****
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*/
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/***** Lamps & Counters wiring *****/
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WRITE8_MEMBER(blitz_state::lamps_a_w)
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{
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@ -464,12 +429,9 @@ WRITE8_MEMBER(blitz_state::lamps_a_w)
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// coin_counter_w(machine(), 0, data & 0x40); /* counter1 */
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// coin_counter_w(machine(), 1, data & 0x80); /* counter2 */
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// coin_counter_w(machine(), 2, data & 0x20); /* counter3 */
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/* Counters:
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*/
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}
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WRITE8_MEMBER(blitz_state::sound_w)
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{
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/* 555 voltage controlled */
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@ -496,7 +458,6 @@ static ADDRESS_MAP_START( megadpkr_map, AS_PROGRAM, 8, blitz_state )
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AM_RANGE(0x10f4, 0x10f7) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
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AM_RANGE(0x10f8, 0x10fb) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
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*/
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AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(megadpkr_videoram_w) AM_SHARE("videoram")
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AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(megadpkr_colorram_w) AM_SHARE("colorram")
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@ -676,7 +637,6 @@ static INPUT_PORTS_START( megadpkr )
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INPUT_PORTS_END
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/*********************************************
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* Graphics Layouts *
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*********************************************/
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@ -817,32 +777,28 @@ ROM_START( megadpkr )
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ROM_END
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/*
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Manufacturer : Blitz system
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Game name : Mega Double Poker
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Platform : Bonanza golden poker interface
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manufacturer : Blitz system
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Game name : Mega Double Poker
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Platform : Bonanza golden poker interface
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BoardID
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BO-BL-01
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Protection: U11 MC68705P5S microcontroller with window
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BoardID
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BO-BL-01
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Main CPU:
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U6 UM6502
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U5 MK48T02B-15 time/clock backup RAM
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Protection: U11 MC68705P5S microcontroller with window
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U2.bin 27C256 ROM
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U3.bin 27C256 ROM
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maincpu:
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U6 UM6502
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U5 MK48T02B-15 time/clock backup ram
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U2.bin 27C256 ROM
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U3.bin 27C256 ROM
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Graphics ic
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car1_5a.bin 27C32 ROM
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car2_4a.bin 27C32 ROM
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car3_2a.bin 27C32 ROM
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note : MC68705P5S is protected
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Graphics IC
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car1_5a.bin 27C32 ROM
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car2_4a.bin 27C32 ROM
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car3_2a.bin 27C32 ROM
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note : MC68705P5S is protected
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*/
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ROM_START( megadpkrb )
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@ -874,6 +830,6 @@ ROM_END
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* Game Drivers *
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*********************************************/
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/* YEAR NAME PARENT MACHINE INPUT INIT ROT COMPANY FULLNAME FLAGS */
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/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS */
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GAME( 1990, megadpkr, 0, megadpkr, megadpkr, driver_device, 0, ROT0, "Blitz System Inc.", "Mega Double Poker (conversion kit, set 1)", GAME_NO_SOUND | GAME_NOT_WORKING )
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GAME( 1990, megadpkrb, megadpkr, megadpkr, megadpkr, driver_device, 0, ROT0, "Blitz System Inc.", "Mega Double Poker (conversion kit, set 2)", GAME_NO_SOUND | GAME_NOT_WORKING )
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Block a user