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https://github.com/holub/mame
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Forgot main file
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Angelo Salese
parent
8acf855712
commit
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1
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vendored
@ -6130,6 +6130,7 @@ src/mess/drivers/myb3k.c svneol=native#text/plain
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src/mess/drivers/mycom.c svneol=native#text/plain
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src/mess/drivers/mz2000.c svneol=native#text/plain
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src/mess/drivers/mz2500.c svneol=native#text/plain
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src/mess/drivers/mz3500.c svneol=native#text/plain
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src/mess/drivers/mz6500.c svneol=native#text/plain
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src/mess/drivers/mz700.c svneol=native#text/plain
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src/mess/drivers/mz80.c svneol=native#text/plain
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271
src/mess/drivers/mz3500.c
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271
src/mess/drivers/mz3500.c
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/***************************************************************************
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Template for skeleton drivers
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***************************************************************************/
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#include "emu.h"
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#include "cpu/z80/z80.h"
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//#include "sound/ay8910.h"
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#define MAIN_CLOCK XTAL_8MHz
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class mz3500_state : public driver_device
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{
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public:
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mz3500_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_master(*this, "master"),
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m_slave(*this, "slave")
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{ }
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// devices
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required_device<cpu_device> m_master;
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required_device<cpu_device> m_slave;
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UINT8 *m_ipl_rom;
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UINT8 *m_basic_rom;
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UINT8 *m_work_ram;
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UINT8 *m_shared_ram;
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DECLARE_READ8_MEMBER(mz3500_master_mem_r);
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DECLARE_WRITE8_MEMBER(mz3500_master_mem_w);
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DECLARE_READ8_MEMBER(mz3500_ipl_r);
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DECLARE_READ8_MEMBER(mz3500_basic_r);
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DECLARE_READ8_MEMBER(mz3500_work_ram_r);
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DECLARE_WRITE8_MEMBER(mz3500_work_ram_w);
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DECLARE_READ8_MEMBER(mz3500_shared_ram_r);
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DECLARE_WRITE8_MEMBER(mz3500_shared_ram_w);
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// screen updates
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UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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protected:
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// driver_device overrides
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virtual void machine_start();
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virtual void machine_reset();
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virtual void video_start();
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virtual void palette_init();
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};
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void mz3500_state::video_start()
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{
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}
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UINT32 mz3500_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
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{
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return 0;
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}
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READ8_MEMBER(mz3500_state::mz3500_ipl_r)
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{
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return m_ipl_rom[offset];
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}
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READ8_MEMBER(mz3500_state::mz3500_basic_r)
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{
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return m_basic_rom[offset];
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}
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READ8_MEMBER(mz3500_state::mz3500_work_ram_r)
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{
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return m_work_ram[offset];
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}
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WRITE8_MEMBER(mz3500_state::mz3500_work_ram_w)
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{
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m_work_ram[offset] = data;
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}
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READ8_MEMBER(mz3500_state::mz3500_master_mem_r)
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{
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if((offset & 0xe000) == 0x0000) { return mz3500_ipl_r(space,(offset & 0xfff) | 0x1000); }
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if((offset & 0xe000) == 0x2000) { return mz3500_basic_r(space,offset & 0x1fff); }
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if((offset & 0xe000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x4000); }
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if((offset & 0xe000) == 0x6000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x6000); }
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if((offset & 0xe000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x8000); }
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if((offset & 0xe000) == 0xa000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xa000); }
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if((offset & 0xe000) == 0xc000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xc000); }
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if((offset & 0xe000) == 0xe000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xe000); }
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return 0xff;
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}
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WRITE8_MEMBER(mz3500_state::mz3500_master_mem_w)
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{
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if((offset & 0xe000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x4000,data); return; }
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if((offset & 0xe000) == 0x6000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x6000,data); return; }
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if((offset & 0xe000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x8000,data); return; }
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if((offset & 0xe000) == 0xa000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xa000,data); return; }
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if((offset & 0xe000) == 0xc000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xc000,data); return; }
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if((offset & 0xe000) == 0xe000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xe000,data); return; }
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}
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READ8_MEMBER(mz3500_state::mz3500_shared_ram_r)
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{
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return m_shared_ram[offset];
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}
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WRITE8_MEMBER(mz3500_state::mz3500_shared_ram_w)
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{
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m_shared_ram[offset] = data;
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}
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static ADDRESS_MAP_START( mz3500_master_map, AS_PROGRAM, 8, mz3500_state )
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AM_RANGE(0x0000, 0xffff) AM_READWRITE(mz3500_master_mem_r,mz3500_master_mem_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( mz3500_master_io, AS_IO, 8, mz3500_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( mz3500_slave_map, AS_PROGRAM, 8, mz3500_state )
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AM_RANGE(0x0000, 0x1fff) AM_ROM AM_REGION("ipl", 0)
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AM_RANGE(0x2000, 0x27ff) AM_READWRITE(mz3500_shared_ram_r, mz3500_shared_ram_w)
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AM_RANGE(0x4000, 0x5fff) AM_RAM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( mz3500_slave_io, AS_IO, 8, mz3500_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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ADDRESS_MAP_END
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static INPUT_PORTS_START( mz3500 )
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/* dummy active high structure */
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PORT_START("SYSA")
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PORT_DIPNAME( 0x01, 0x00, "SYSA" )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x01, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x02, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x04, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x08, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x10, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x20, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x40, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x80, DEF_STR( On ) )
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/* dummy active low structure */
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PORT_START("DSWA")
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PORT_DIPNAME( 0x01, 0x01, "DSWA" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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INPUT_PORTS_END
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static const gfx_layout charlayout =
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{
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8,8,
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RGN_FRAC(1,1),
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1,
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{ RGN_FRAC(0,1) },
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{ 0, 1, 2, 3, 4, 5, 6, 7 },
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{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
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8*8
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};
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static GFXDECODE_START( mz3500 )
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GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
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GFXDECODE_END
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void mz3500_state::machine_start()
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{
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m_ipl_rom = memregion("ipl")->base();
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m_basic_rom = memregion("basic")->base();
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m_work_ram = auto_alloc_array_clear(machine(), UINT8, 0x40000);
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m_shared_ram = auto_alloc_array_clear(machine(), UINT8, 0x800);
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}
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void mz3500_state::machine_reset()
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{
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}
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void mz3500_state::palette_init()
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{
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}
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static MACHINE_CONFIG_START( mz3500, mz3500_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("master",Z80,MAIN_CLOCK/2)
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MCFG_CPU_PROGRAM_MAP(mz3500_master_map)
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MCFG_CPU_IO_MAP(mz3500_master_io)
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MCFG_CPU_ADD("slave",Z80,MAIN_CLOCK/2)
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MCFG_CPU_PROGRAM_MAP(mz3500_slave_map)
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MCFG_CPU_IO_MAP(mz3500_slave_io)
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/* video hardware */
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_REFRESH_RATE(60)
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MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
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MCFG_SCREEN_UPDATE_DRIVER(mz3500_state, screen_update)
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MCFG_SCREEN_SIZE(32*8, 32*8)
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MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 0*8, 32*8-1)
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MCFG_GFXDECODE(mz3500)
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MCFG_PALETTE_LENGTH(8)
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/* sound hardware */
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MCFG_SPEAKER_STANDARD_MONO("mono")
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// MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/4)
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// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
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MACHINE_CONFIG_END
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/***************************************************************************
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Game driver(s)
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***************************************************************************/
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ROM_START( mz3500 )
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ROM_REGION( 0x2000, "ipl", ROMREGION_ERASE00 )
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ROM_LOAD( "mz-3500_ipl-rom_2-0a_m5l2764k.bin", 0x000000, 0x002000, CRC(119708b9) SHA1(de81979608ba6ab76f09088a92bfd1a5bc42530e) )
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ROM_REGION( 0x8000, "basic", ROMREGION_ERASE00 )
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ROM_LOAD( "basic.rom", 0x00000, 0x8000, NO_DUMP )
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ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASE00 )
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ROM_LOAD( "mz-3500_cg-rom_2-b_m5l2764k.bin", 0x000000, 0x002000, CRC(29f2f80a) SHA1(64b307cd9de5a3327e3ec9f3d0d6b3485706f436) )
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ROM_END
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GAME( 198?, mz3500, 0, mz3500, mz3500, driver_device, 0, ROT0, "Sharp", "MZ-3500", GAME_IS_SKELETON )
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