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Added vt83c461, which is currently implemented as a 32 bit chip. This allows hooking up to the jaguar driver without any glue, but primal rage 2 does as the io bus it's connected to is only 16 bit. (nw)

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This commit is contained in:
smf- 2013-06-19 18:48:00 +00:00
parent 7242041eb1
commit 243b823635
9 changed files with 333 additions and 172 deletions
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2
.gitattributes vendored
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@ -1462,6 +1462,8 @@ src/emu/machine/upd765.c svneol=native#text/plain
src/emu/machine/upd765.h svneol=native#text/plain
src/emu/machine/v3021.c svneol=native#text/plain
src/emu/machine/v3021.h svneol=native#text/plain
src/emu/machine/vt83c461.c svneol=native#text/plain
src/emu/machine/vt83c461.h svneol=native#text/plain
src/emu/machine/wd11c00_17.c svneol=native#text/plain
src/emu/machine/wd11c00_17.h svneol=native#text/plain
src/emu/machine/wd17xx.c svneol=native#text/plain

89
src/emu/machine/idectrl.c
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@ -25,77 +25,20 @@
CONSTANTS
***************************************************************************/
#define IDE_BANK2_CONFIG_UNK 4
#define IDE_BANK2_CONFIG_REGISTER 8
#define IDE_BANK2_CONFIG_DATA 0xc
const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
ata_interface_device(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
m_config_unknown(0),
m_config_register_num(0)
ata_interface_device(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock)
{
}
ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
ata_interface_device(mconfig, type, name, tag, owner, clock),
m_config_unknown(0),
m_config_register_num(0)
ata_interface_device(mconfig, type, name, tag, owner, clock)
{
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void ide_controller_device::device_start()
{
ata_interface_device::device_start();
/* register ide states */
save_item(NAME(m_config_unknown));
save_item(NAME(m_config_register));
save_item(NAME(m_config_register_num));
}
READ8_MEMBER( ide_controller_device::read_via_config )
{
UINT16 result = 0;
/* logit */
LOG(("%s:IDE via config read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
switch(offset)
{
/* unknown config register */
case IDE_BANK2_CONFIG_UNK:
result = m_config_unknown;
break;
/* active config register */
case IDE_BANK2_CONFIG_REGISTER:
result = m_config_register_num;
break;
/* data from active config register */
case IDE_BANK2_CONFIG_DATA:
if (m_config_register_num < IDE_CONFIG_REGISTERS)
result = m_config_register[m_config_register_num];
break;
default:
logerror("%s:unknown IDE via config read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
break;
}
// printf( "read via config %04x %04x %04x\n", offset, result, mem_mask );
return result;
}
READ16_MEMBER( ide_controller_device::read_cs0 )
{
if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit read of data register
if (mem_mask == 0xff00)
{
return ata_interface_device::read_cs0(space, (offset * 2) + 1, 0xff) << 8;
@ -118,36 +61,8 @@ READ16_MEMBER( ide_controller_device::read_cs1 )
}
}
WRITE8_MEMBER( ide_controller_device::write_via_config )
{
// printf( "write via config %04x %04x %04x\n", offset, data, mem_mask );
/* logit */
LOG(("%s:IDE via config write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
switch (offset)
{
/* unknown config register */
case IDE_BANK2_CONFIG_UNK:
m_config_unknown = data;
break;
/* active config register */
case IDE_BANK2_CONFIG_REGISTER:
m_config_register_num = data;
break;
/* data from active config register */
case IDE_BANK2_CONFIG_DATA:
if (m_config_register_num < IDE_CONFIG_REGISTERS)
m_config_register[m_config_register_num] = data;
break;
}
}
WRITE16_MEMBER( ide_controller_device::write_cs0 )
{
if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit write to data register
if (mem_mask == 0xff00)
{
return ata_interface_device::write_cs0(space, (offset * 2) + 1, data >> 8, 0xff);

12
src/emu/machine/idectrl.h
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@ -26,28 +26,16 @@
MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
MCFG_DEVICE_MODIFY(_tag)
#define IDE_CONFIG_REGISTERS 0x10
class ide_controller_device : public ata_interface_device
{
public:
ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ8_MEMBER(read_via_config);
DECLARE_WRITE8_MEMBER(write_via_config);
virtual DECLARE_READ16_MEMBER(read_cs0);
virtual DECLARE_READ16_MEMBER(read_cs1);
virtual DECLARE_WRITE16_MEMBER(write_cs0);
virtual DECLARE_WRITE16_MEMBER(write_cs1);
protected:
virtual void device_start();
private:
UINT8 m_config_unknown;
UINT8 m_config_register[IDE_CONFIG_REGISTERS];
UINT8 m_config_register_num;
};
extern const device_type IDE_CONTROLLER;

1
src/emu/machine/machine.mak
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@ -535,6 +535,7 @@ MACHINEOBJS += $(MACHINEOBJ)/ataintf.o
MACHINEOBJS += $(MACHINEOBJ)/atadev.o
MACHINEOBJS += $(MACHINEOBJ)/idectrl.o
MACHINEOBJS += $(MACHINEOBJ)/idehd.o
MACHINEOBJS += $(MACHINEOBJ)/vt83c461.o
endif
#-------------------------------------------------

173
src/emu/machine/vt83c461.c Normal file
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@ -0,0 +1,173 @@
#include "vt83c461.h"
/***************************************************************************
DEBUGGING
***************************************************************************/
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
#define VT83C461_CONFIG_UNK 1
#define VT83C461_CONFIG_REGISTER 2
#define VT83C461_CONFIG_DATA 3
const device_type VT83C461 = &device_creator<vt83c461_device>;
vt83c461_device::vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
ide_controller_device(mconfig, VT83C461, "VIA VT83C461", tag, owner, clock),
m_config_unknown(0),
m_config_register_num(0)
{
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void vt83c461_device::device_start()
{
ide_controller_device::device_start();
/* register ide states */
save_item(NAME(m_config_unknown));
save_item(NAME(m_config_register));
save_item(NAME(m_config_register_num));
}
READ32_MEMBER( vt83c461_device::read_config )
{
UINT32 result = 0;
/* logit */
LOG(("%s:IDE via config read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
switch(offset)
{
/* unknown config register */
case VT83C461_CONFIG_UNK:
result = m_config_unknown;
break;
/* active config register */
case VT83C461_CONFIG_REGISTER:
result = m_config_register_num;
break;
/* data from active config register */
case VT83C461_CONFIG_DATA:
if (m_config_register_num < IDE_CONFIG_REGISTERS)
result = m_config_register[m_config_register_num];
break;
default:
logerror("%s:unknown IDE via config read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
break;
}
// printf( "vt83c461 read config %04x %08x %04x\n", offset, result, mem_mask );
return result;
}
WRITE32_MEMBER( vt83c461_device::write_config )
{
// printf( "vt83c461 write config %04x %08x %04x\n", offset, data, mem_mask );
/* logit */
LOG(("%s:IDE via config write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
switch (offset)
{
/* unknown config register */
case VT83C461_CONFIG_UNK:
m_config_unknown = data;
break;
/* active config register */
case VT83C461_CONFIG_REGISTER:
m_config_register_num = data;
break;
/* data from active config register */
case VT83C461_CONFIG_DATA:
if (m_config_register_num < IDE_CONFIG_REGISTERS)
m_config_register[m_config_register_num] = data;
break;
default:
logerror("%s:unknown IDE via config write at %03X = %08x, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask);
break;
}
}
READ32_MEMBER(vt83c461_device::read_cs0)
{
UINT32 data = 0;
if (ACCESSING_BITS_0_15)
{
data = ide_controller_device::read_cs0(space, (offset * 2), mem_mask);
if (offset == 0 && ACCESSING_BITS_16_31)
data |= ide_controller_device::read_cs0(space, (offset * 2), mem_mask >> 16) << 16;
}
else if (ACCESSING_BITS_16_31)
{
data = ide_controller_device::read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
}
// printf( "vt83c461 read cs0 %08x %08x %08x\n", offset, data, mem_mask );
return data;
}
READ32_MEMBER(vt83c461_device::read_cs1)
{
UINT32 data = 0;
if (ACCESSING_BITS_0_15)
{
data = ide_controller_device::read_cs1(space, (offset * 2), mem_mask);
}
else if (ACCESSING_BITS_16_23)
{
data = ide_controller_device::read_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16;
}
// printf( "vt83c461 read cs1 %08x %08x %08x\n", offset, data, mem_mask );
return data;
}
WRITE32_MEMBER(vt83c461_device::write_cs0)
{
// printf( "vt83c461 write cs0 %08x %08x %08x\n", offset, data, mem_mask );
if (ACCESSING_BITS_0_15)
{
ide_controller_device::write_cs0(space, (offset * 2), data, mem_mask);
if (offset == 0 && ACCESSING_BITS_16_31)
ata_interface_device::write_cs0(space, (offset * 2), data >> 16, mem_mask >> 16);
}
else if (ACCESSING_BITS_16_31)
{
ide_controller_device::write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
}
}
WRITE32_MEMBER(vt83c461_device::write_cs1)
{
// printf( "vt83c461 write cs1 %08x %08x %08x\n", offset, data, mem_mask );
if (ACCESSING_BITS_0_7)
{
ide_controller_device::write_cs1(space, (offset * 2), data, mem_mask);
}
else if (ACCESSING_BITS_16_23)
{
ide_controller_device::write_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
}
}

60
src/emu/machine/vt83c461.h Normal file
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@ -0,0 +1,60 @@
/***************************************************************************
vt83c461.h
VIA VT83C461 (IDE Hard Drive controller).
Copyright Nicola Salmoria and the MAME Team.
Visit http://mamedev.org for licensing and usage restrictions.
***************************************************************************/
#pragma once
#ifndef __VT83C461_H__
#define __VT83C461_H__
#include "idectrl.h"
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MCFG_VT83C461_ADD(_tag, _slotintf, _master, _slave, _fixed) \
MCFG_DEVICE_ADD(_tag, VT83C461, 0) \
MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
MCFG_DEVICE_MODIFY(_tag)
#define IDE_CONFIG_REGISTERS 0x10
class vt83c461_device : public ide_controller_device
{
public:
vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ32_MEMBER(read_config);
DECLARE_WRITE32_MEMBER(write_config);
virtual DECLARE_READ32_MEMBER(read_cs0);
virtual DECLARE_READ32_MEMBER(read_cs1);
virtual DECLARE_WRITE32_MEMBER(write_cs0);
virtual DECLARE_WRITE32_MEMBER(write_cs1);
protected:
virtual void device_start();
private:
using ide_controller_device::read_cs0;
using ide_controller_device::read_cs1;
using ide_controller_device::write_cs0;
using ide_controller_device::write_cs1;
UINT8 m_config_unknown;
UINT8 m_config_register[IDE_CONFIG_REGISTERS];
UINT8 m_config_register_num;
};
extern const device_type VT83C461;
#endif

67
src/mame/drivers/jaguar.c
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@ -334,7 +334,7 @@ Notes:
#include "cpu/m68000/m68000.h"
#include "cpu/mips/r3000.h"
#include "cpu/jaguar/jaguar.h"
#include "machine/idectrl.h"
#include "machine/vt83c461.h"
#include "sound/dac.h"
#include "includes/jaguar.h"
#include "emuopts.h"
@ -1077,57 +1077,6 @@ static ADDRESS_MAP_START( jaguar_map, AS_PROGRAM, 16, jaguar_state )
AM_RANGE(0xf1d000, 0xf1dfff) AM_READWRITE(wave_rom_r16, wave_rom_w16 )
ADDRESS_MAP_END
/// hack for 32 big endian bus talking to 16 bit little endian ide
READ32_MEMBER(jaguar_state::vt83c461_r)
{
UINT32 data = 0;
if(offset >= 0x30/4 && offset < 0x40/4)
{
if (ACCESSING_BITS_0_7)
data = m_ide->read_via_config(space, (offset * 4) & 0xf, mem_mask);
}
else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
{
if (ACCESSING_BITS_0_15)
data |= m_ide->read_cs0(space, (offset * 2) & 7, mem_mask);
if (ACCESSING_BITS_16_31)
data |= m_ide->read_cs0(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
}
else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
{
if (ACCESSING_BITS_0_15)
data |= m_ide->read_cs1(space, (offset * 2) & 7, mem_mask);
if (ACCESSING_BITS_16_31)
data |= m_ide->read_cs1(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
}
return data;
}
WRITE32_MEMBER(jaguar_state::vt83c461_w)
{
if(offset >= 0x30/4 && offset < 0x40/4)
{
if (ACCESSING_BITS_0_7)
m_ide->write_via_config(space, (offset * 4) & 0xf, data, mem_mask);
}
else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
{
if (ACCESSING_BITS_0_15)
m_ide->write_cs0(space, (offset * 2) & 7, data, mem_mask);
if (ACCESSING_BITS_16_31)
m_ide->write_cs0(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
}
else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
{
if (ACCESSING_BITS_0_15)
m_ide->write_cs1(space, (offset * 2) & 7, data, mem_mask);
if (ACCESSING_BITS_16_31)
m_ide->write_cs1(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
}
}
/*************************************
@ -1140,7 +1089,9 @@ static ADDRESS_MAP_START( r3000_map, AS_PROGRAM, 32, jaguar_state )
AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_SHARE("sharedram")
AM_RANGE(0x04800000, 0x04bfffff) AM_ROMBANK("maingfxbank")
AM_RANGE(0x04c00000, 0x04dfffff) AM_ROMBANK("mainsndbank")
AM_RANGE(0x04e00000, 0x04e003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
AM_RANGE(0x04e00030, 0x04e0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
AM_RANGE(0x04e001f0, 0x04e001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
AM_RANGE(0x04e003f0, 0x04e003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
AM_RANGE(0x04f00000, 0x04f003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
AM_RANGE(0x04f00400, 0x04f007ff) AM_RAM AM_SHARE("gpuclut")
AM_RANGE(0x04f02100, 0x04f021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
@ -1174,7 +1125,9 @@ static ADDRESS_MAP_START( m68020_map, AS_PROGRAM, 32, jaguar_state )
AM_RANGE(0xa40000, 0xa40003) AM_WRITE(eeprom_enable_w)
AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w)
AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("mainsndbank")
AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
AM_RANGE(0xe00030, 0xe0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
@ -1202,7 +1155,9 @@ static ADDRESS_MAP_START( gpu_map, AS_PROGRAM, 32, jaguar_state )
AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE("sharedram")
AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK("gpugfxbank")
AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("dspsndbank")
AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
AM_RANGE(0xe00030, 0xe0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
@ -1601,7 +1556,7 @@ static MACHINE_CONFIG_START( cojagr3k, jaguar_state )
MCFG_NVRAM_ADD_1FILL("nvram")
MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
MCFG_VT83C461_ADD("ide", ata_devices, "hdd", NULL, true)
MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(jaguar_state, external_int))
/* video hardware */

95
src/mame/drivers/zn.c
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@ -20,7 +20,7 @@
#include "machine/znsec.h"
#include "machine/zndip.h"
#include "machine/ataintf.h"
#include "machine/idectrl.h"
#include "machine/vt83c461.h"
#include "audio/taitosnd.h"
#include "sound/2610intf.h"
#include "sound/ymz280b.h"
@ -46,7 +46,7 @@ public:
m_cbaj_fifo1(*this, "cbaj_fifo1"),
m_cbaj_fifo2(*this, "cbaj_fifo2"),
m_mb3773(*this, "mb3773"),
m_ide(*this, "ide")
m_vt83c461(*this, "ide")
{
}
@ -83,6 +83,10 @@ public:
DECLARE_WRITE8_MEMBER(coh1002m_bank_w);
DECLARE_READ8_MEMBER(cbaj_sound_main_status_r);
DECLARE_READ8_MEMBER(cbaj_sound_z80_status_r);
DECLARE_READ16_MEMBER(vt83c461_16_r);
DECLARE_WRITE16_MEMBER(vt83c461_16_w);
DECLARE_READ16_MEMBER(vt83c461_32_r);
DECLARE_WRITE16_MEMBER(vt83c461_32_w);
DECLARE_DRIVER_INIT(coh1000ta);
DECLARE_DRIVER_INIT(coh1000tb);
DECLARE_DRIVER_INIT(coh1000c);
@ -116,6 +120,8 @@ private:
size_t m_nbajamex_eeprom_size;
UINT8 *m_nbajamex_eeprom;
UINT16 vt83c461_latch;
required_device<psxgpu_device> m_gpu;
required_device<znsec_device> m_znsec0;
required_device<znsec_device> m_znsec1;
@ -126,7 +132,7 @@ private:
optional_device<fifo7200_device> m_cbaj_fifo1;
optional_device<fifo7200_device> m_cbaj_fifo2;
optional_device<mb3773_device> m_mb3773;
optional_device<ide_controller_device> m_ide;
optional_device<vt83c461_device> m_vt83c461;
};
inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fmt, ... )
@ -1343,7 +1349,7 @@ void zn_state::atpsx_dma_read( UINT32 *p_n_psxram, UINT32 n_address, INT32 n_siz
n_size <<= 1;
while( n_size > 0 )
{
psxwriteword( p_n_psxram, n_address, m_ide->read_cs0(space, 0, 0xffff) );
psxwriteword( p_n_psxram, n_address, m_vt83c461->read_cs0(space, (UINT32) 0, (UINT32) 0xffff) );
n_address += 2;
n_size--;
}
@ -1354,18 +1360,81 @@ void zn_state::atpsx_dma_write( UINT32 *p_n_psxram, UINT32 n_address, INT32 n_si
logerror("DMA write from %08x for %d bytes\n", n_address, n_size<<2);
}
READ16_MEMBER(zn_state::vt83c461_16_r)
{
int shift = (16 * (offset & 1));
if( offset >= 0x30 / 2 && offset < 0x40 / 2 )
{
return m_vt83c461->read_config( space, ( offset / 2 ) & 3, mem_mask << shift ) >> shift;
}
else if( offset >= 0x1f0 / 2 && offset < 0x1f8 / 2 )
{
return m_vt83c461->read_cs0( space, ( offset / 2 ) & 1, (UINT32) mem_mask << shift ) >> shift;
}
else if( offset >= 0x3f0 / 2 && offset < 0x3f8 / 2 )
{
return m_vt83c461->read_cs1( space, ( offset / 2 ) & 1, (UINT32) mem_mask << shift ) >> shift;
}
else
{
logerror( "unhandled 16 bit read %04x %04x\n", offset, mem_mask );
return 0xffff;
}
}
WRITE16_MEMBER(zn_state::vt83c461_16_w)
{
int shift = (16 * (offset & 1));
if( offset >= 0x30 / 2 && offset < 0x40 / 2 )
{
m_vt83c461->write_config( space, ( offset / 2 ) & 3, data << shift, mem_mask << shift );
}
else if( offset >= 0x1f0 / 2 && offset < 0x1f8 / 2 )
{
m_vt83c461->write_cs0( space, ( offset / 2 ) & 1, (UINT32) data << shift, (UINT32) mem_mask << shift );
}
else if( offset >= 0x3f0 / 2 && offset < 0x3f8 / 2 )
{
m_vt83c461->write_cs1( space, ( offset / 2 ) & 1, (UINT32) data << shift, (UINT32) mem_mask << shift );
}
else
{
logerror( "unhandled 16 bit write %04x %04x %04x\n", offset, data, mem_mask );
}
}
READ16_MEMBER(zn_state::vt83c461_32_r)
{
if( offset == 0x1f0/2 )
{
UINT32 data = m_vt83c461->read_cs0(space, 0, 0xffffffff);
vt83c461_latch = data >> 16;
return data & 0xffff;
}
else if( offset == 0x1f2/2 )
{
return vt83c461_latch;
}
else
{
logerror( "unhandled 32 bit read %04x %04x\n", offset, mem_mask );
return 0xffff;
}
}
WRITE16_MEMBER(zn_state::vt83c461_32_w)
{
logerror( "unhandled 32 bit write %04x %04x %04x\n", offset, data, mem_mask );
}
static ADDRESS_MAP_START(coh1000w_map, AS_PROGRAM, 32, zn_state)
AM_RANGE(0x1f000000, 0x1f1fffff) AM_ROM AM_REGION("roms", 0)
AM_RANGE(0x1f000000, 0x1f000003) AM_WRITENOP
AM_RANGE(0x1f7e8000, 0x1f7e8003) AM_NOP
// 8/16
AM_RANGE(0x1f7e4030, 0x1f7e403f) AM_DEVREADWRITE8("ide", ide_controller_device, read_via_config, write_via_config, 0xffffffff)
AM_RANGE(0x1f7e41f0, 0x1f7e41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x1f7e43f0, 0x1f7e43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
// 32
AM_RANGE(0x1f7f41f0, 0x1f7f41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
AM_RANGE(0x1f7f43f0, 0x1f7f43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
AM_RANGE(0x1f7e4000, 0x1f7e4fff) AM_READWRITE16(vt83c461_16_r, vt83c461_16_w, 0xffffffff)
AM_RANGE(0x1f7f4000, 0x1f7f4fff) AM_READWRITE16(vt83c461_32_r, vt83c461_32_w, 0xffffffff)
AM_IMPORT_FROM(zn_map)
ADDRESS_MAP_END
@ -1376,7 +1445,7 @@ static MACHINE_CONFIG_DERIVED( coh1000w, zn1_2mb_vram )
MCFG_RAM_MODIFY("maincpu:ram")
MCFG_RAM_DEFAULT_SIZE("8M")
MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
MCFG_VT83C461_ADD("ide", ata_devices, "hdd", NULL, true)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( zn_state::atpsx_dma_read ), (zn_state *) owner ) )
MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( zn_state::atpsx_dma_write ), (zn_state *) owner ) )

6
src/mame/includes/jaguar.h
View File

@ -8,7 +8,7 @@
#include "machine/nvram.h"
#include "sound/dac.h"
#include "machine/eeprom.h"
#include "machine/idectrl.h"
#include "machine/vt83c461.h"
#include "imagedev/snapquik.h"
#ifndef ENABLE_SPEEDUP_HACKS
@ -211,8 +211,6 @@ public:
DECLARE_WRITE32_MEMBER( blitter_w );
DECLARE_READ16_MEMBER( tom_regs_r );
DECLARE_WRITE16_MEMBER( tom_regs_w );
DECLARE_READ32_MEMBER( vt83c461_r );
DECLARE_WRITE32_MEMBER( vt83c461_w );
DECLARE_READ32_MEMBER( cojag_gun_input_r );
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@ -325,5 +323,5 @@ protected:
void jaguar_nvram_load();
void jaguar_nvram_save();
optional_device<eeprom_device> m_eeprom;
optional_device<ide_controller_device> m_ide;
optional_device<vt83c461_device> m_ide;
};