mirror of
https://github.com/holub/mame
synced 2025-07-04 09:28:51 +03:00
tidy up for pull request
This commit is contained in:
Patrick Mackinlay
parent
17e3abc6b7
commit
24dba19f8c
File diff suppressed because it is too large
Load Diff
@ -137,6 +137,7 @@ enum clipper_exception_vectors
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EXCEPTION_INTERRUPT_BASE = 0x800,
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};
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// trap source values are shifted into the correct field in the psw
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enum clipper_cpu_trap_sources
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{
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CTS_NO_CPU_TRAP = 0 << 24,
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@ -157,6 +158,10 @@ enum clipper_memory_trap_sources
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MTS_WRITE_PROTECT_FAULT = 7 << 28,
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};
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// convenience macros for frequently used instruction fields
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#define R1 (m_info.r1)
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#define R2 (m_info.r2)
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// convenience macros for dealing with the psw
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#define PSW(mask) (m_psw & PSW_##mask)
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#define SSW(mask) (m_ssw & SSW_##mask)
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@ -176,27 +181,27 @@ enum clipper_memory_trap_sources
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#define UF_SUB(a, b) ((b > 0) && (a < INT_MIN + b))
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// CLIPPER logic for carry and overflow flags
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#define C_ADD(a, b) ((uint32_t)a + (uint32_t)b < (uint32_t)a)
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#define V_ADD(a, b) (OF_ADD((int32_t)a, (int32_t)b) || UF_ADD((int32_t)a, (int32_t)b))
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#define C_SUB(a, b) ((uint32_t)a < (uint32_t)b)
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#define V_SUB(a, b) (OF_SUB((int32_t)a, (int32_t)b) || UF_SUB((int32_t)a, (int32_t)b))
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#define C_ADD(a, b) ((u32)a + (u32)b < (u32)a)
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#define V_ADD(a, b) (OF_ADD((s32)a, (s32)b) || UF_ADD((s32)a, (s32)b))
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#define C_SUB(a, b) ((u32)a < (u32)b)
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#define V_SUB(a, b) (OF_SUB((s32)a, (s32)b) || UF_SUB((s32)a, (s32)b))
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class clipper_device : public cpu_device
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{
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public:
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clipper_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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clipper_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, u32 clock, const char *shortname, const char *source);
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DECLARE_READ_LINE_MEMBER(ssw) { return m_ssw; }
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bool supervisor_mode() { return SSW(U) == 0; }
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bool mapped_mode() { return SSW(M) != 0; }
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protected:
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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// device_execute_interface overrides
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virtual uint32_t execute_min_cycles() const override { return 1; };
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virtual uint32_t execute_max_cycles() const override { return 1; }; // FIXME: don't know, especially macro instructions
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virtual uint32_t execute_input_lines() const override { return 2; }; // number of input/interrupt lines (irq/nmi)
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virtual u32 execute_min_cycles() const override { return 1; };
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virtual u32 execute_max_cycles() const override { return 1; }; // FIXME: don't know, especially macro instructions
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virtual u32 execute_input_lines() const override { return 2; }; // number of input/interrupt lines (irq/nmi)
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virtual void execute_run() override;
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virtual void execute_set_input(int inputnum, int state) override;
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@ -213,17 +218,17 @@ protected:
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// device_disasm_interface overrides
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virtual uint32_t disasm_min_opcode_bytes() const override { return 2; } // smallest instruction
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virtual uint32_t disasm_max_opcode_bytes() const override { return 8; } // largest instruction
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virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
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virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const u8 *oprom, const u8 *opram, u32 options) override;
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// core registers
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uint32_t m_pc;
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uint32_t m_psw;
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uint32_t m_ssw;
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u32 m_pc;
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u32 m_psw;
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u32 m_ssw;
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// integer registers
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int32_t *m_r; // active registers
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int32_t m_ru[16]; // user registers
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int32_t m_rs[16]; // supervisor registers
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s32 *m_r; // active registers
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s32 m_ru[16]; // user registers
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s32 m_rs[16]; // supervisor registers
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// floating registers
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double m_f[16];
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@ -236,37 +241,54 @@ private:
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address_space *m_data;
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int m_icount;
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int m_interrupt_cycles;
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int m_irq;
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int m_nmi;
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// decoded instruction information
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struct
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{
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// decoded operand information
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union {
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int32_t imm;
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uint32_t r2 : 4;
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uint16_t macro;
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} op;
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u8 opcode, subopcode;
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u8 r1, r2;
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s32 imm;
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u16 macro;
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// total size of instruction in bytes
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uint32_t size;
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u32 size;
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// computed effective address
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uint32_t address;
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u32 address;
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} m_info;
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void clipper_device::decode_instruction(uint16_t insn);
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int clipper_device::execute_instruction(uint16_t insn);
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void clipper_device::decode_instruction(u16 insn);
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int clipper_device::execute_instruction();
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bool clipper_device::evaluate_branch();
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// condition code evaluation
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void clipper_device::evaluate_cc2f(double v0, double v1);
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bool clipper_device::evaluate_branch(uint32_t condition);
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uint32_t clipper_device::intrap(uint32_t vector, uint32_t pc, uint32_t cts = CTS_NO_CPU_TRAP, uint32_t mts = MTS_NO_MEMORY_TRAP);
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uint32_t clipper_device::intrap(u32 vector, u32 pc, u32 cts = CTS_NO_CPU_TRAP, u32 mts = MTS_NO_MEMORY_TRAP);
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};
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extern const device_type CLIPPER;
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class clipper_c100_device : public clipper_device
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{
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public:
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clipper_c100_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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class clipper_c300_device : public clipper_device
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{
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public:
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clipper_c300_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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class clipper_c400_device : public clipper_device
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{
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public:
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clipper_c400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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};
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extern const device_type CLIPPER_C100;
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extern const device_type CLIPPER_C300;
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extern const device_type CLIPPER_C400;
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extern CPU_DISASSEMBLE(clipper);
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#endif /* __CLIPPER_H__ */
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@ -5,10 +5,10 @@
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/*
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* TODO
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* * dynamically switch between C400 and C100/C300 instruction sets
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* * handle failures of addressing mode decoding more elegantly
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* * improve address decoding to use streams
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* * detect various cases of illegal instruction encoding
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* - dynamically switch between C400 and C100/C300 instruction sets
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* - handle failures of addressing mode decoding more elegantly
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* - improve address decoding to use streams
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* - detect various cases of illegal instruction encoding
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*/
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// enable C400 instruction decoding
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@ -72,7 +72,7 @@ static const char *const cc[] =
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/*
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* Decode an addressing mode into a string.
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*/
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char *address (offs_t pc, uint16_t *insn)
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char *address (offs_t pc, u16 *insn)
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{
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static char buffer[32];
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@ -102,8 +102,8 @@ char *address (offs_t pc, uint16_t *insn)
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*/
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CPU_DISASSEMBLE(clipper)
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{
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uint16_t *insn = (uint16_t *)oprom;
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uint32_t flags = DASMFLAG_SUPPORTED;
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u16 *insn = (u16 *)oprom;
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u32 flags = DASMFLAG_SUPPORTED;
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offs_t bytes;
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switch (insn[0] >> 8)
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@ -310,7 +310,7 @@ CPU_DISASSEMBLE(clipper)
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case 0x3f: util::stream_format(stream, "loadfs r%d,f%d", (insn[1] & 0xf0) >> 4, insn[1] & 0xf); break;
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default:
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util::stream_format(stream, "macro 0x%04x 0x%04x ; invalid", insn[0], insn[1]);
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util::stream_format(stream, "macro 0x%04x 0x%04x", insn[0], insn[1]);
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break;
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}
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bytes = 4;
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@ -330,7 +330,7 @@ CPU_DISASSEMBLE(clipper)
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case 0x07: util::stream_format(stream, "loadts r%d,f%d", (insn[1] & 0xf0) >> 4, insn[1] & 0xf); break;
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#endif
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default:
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util::stream_format(stream, "macro 0x%04x %04x", insn[0], insn[1]);
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util::stream_format(stream, "macro 0x%04x 0x%04x", insn[0], insn[1]);
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break;
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}
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bytes = 4;
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@ -1,30 +1,72 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* An implementation of the Fairchild/Intergraph Cache and Memory Management Unit (CAMMU) designed for use with the CLIPPER CPU family.
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*
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* Primary reference: http://bitsavers.trailing-edge.com/pdf/fairchild/clipper/CLIPPER%20C300%2032-Bit%20Compute%20Engine.pdf
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* Another reference: http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-289.pdf
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*
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* This implementation is currently at a very early stage, and is only sufficient to handle the bare minimum of boot/diagnostic code.
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*
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* TODO
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* - almost everything
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* - map registers
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* - refactor hardware tlb
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* - address translation
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* - faults
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* - tlb
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* - cache
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* - bus errors
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*/
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#include "cammu.h"
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#define VERBOSE 0
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// each variant of the cammu has different registers and a different addressing map
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// TODO: decode the cammu registers properly
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DEVICE_ADDRESS_MAP_START(map, 32, cammu_device)
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DEVICE_ADDRESS_MAP_START(map, 32, cammu_c4t_device)
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AM_RANGE(0x000, 0xfff) AM_READWRITE(cammu_r, cammu_w)
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ADDRESS_MAP_END
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const device_type CAMMU = &device_creator<cammu_device>;
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DEVICE_ADDRESS_MAP_START(map, 32, cammu_c4i_device)
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AM_RANGE(0x000, 0xfff) AM_READWRITE(cammu_r, cammu_w)
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ADDRESS_MAP_END
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cammu_device::cammu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, CAMMU, "Cache and MMU", tag, owner, clock, "cammu", __FILE__)
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DEVICE_ADDRESS_MAP_START(map, 32, cammu_c3_device)
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AM_RANGE(0x000, 0xfff) AM_READWRITE(cammu_r, cammu_w)
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ADDRESS_MAP_END
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const device_type CAMMU_C4T = &device_creator<cammu_c4t_device>;
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const device_type CAMMU_C4I = &device_creator<cammu_c4i_device>;
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const device_type CAMMU_C3 = &device_creator<cammu_c3_device>;
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cammu_c4t_device::cammu_c4t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: cammu_device(mconfig, CAMMU_C4T, "C4E/C4T CAMMU", tag, owner, clock, "C4T", __FILE__) { }
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cammu_c4i_device::cammu_c4i_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: cammu_device(mconfig, CAMMU_C4I, "C4I CAMMU", tag, owner, clock, "C4I", __FILE__) { }
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cammu_c3_device::cammu_c3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: cammu_device(mconfig, CAMMU_C4T, "C1/C3 CAMMU", tag, owner, clock, "C3", __FILE__) { }
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cammu_device::cammu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source)
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: device_t(mconfig, type, name, tag, owner, clock, shortname, source)
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, device_memory_interface(mconfig, *this),
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m_main_space_config("main", ENDIANNESS_LITTLE, 32, 32, 0),
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m_io_space_config("io", ENDIANNESS_LITTLE, 32, 32, 0),
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m_boot_space_config("boot", ENDIANNESS_LITTLE, 32, 32, 0),
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m_main_space(nullptr),
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m_io_space(nullptr),
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m_boot_space(nullptr)
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m_boot_space(nullptr),
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m_ssw_func(*this)
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{ }
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void cammu_device::device_start()
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{
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m_ssw_func.resolve_safe(0);
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m_main_space = &space(AS_0);
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m_io_space = &space(AS_1);
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m_boot_space = &space(AS_2);
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@ -48,70 +90,91 @@ const address_space_config *cammu_device::memory_space_config (address_spacenum
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READ32_MEMBER(cammu_device::mmu_r)
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{
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// handle htlb
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u32 ssw = m_ssw_func();
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u32 address = offset << 2;
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//if (m_maincpu->supervisor_mode() && (offset & ~0x1FFF) == 0)
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if ((offset & ~0x1FFF) == 0)
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// in supervisor mode, the first 8 pages are always mapped via the hard-wired tlb
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if ((ssw & 0x40000000) == 0 && (address & ~0x7fff) == 0)
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{
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switch (offset & 0x3C00)
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switch (address & 0xf000)
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{
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case 0x000:
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case 0x400:
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case 0x800:
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case 0xC00:
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return m_main_space->read_dword(offset << 2, mem_mask);
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case 0x0000:
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case 0x1000:
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case 0x1400:
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return m_io_space->read_dword((offset & 0x7ff) << 2, mem_mask);
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case 0x2000:
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case 0x3000:
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// pages 0-3: main space pages 0-3
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return m_main_space->read_dword(address, mem_mask);
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case 0x1800:
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case 0x1C00:
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return m_boot_space->read_dword((offset & 0x7ff) << 2, mem_mask);
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case 0x4000:
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case 0x5000:
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// pages 4-5: i/o space pages 0-1
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return m_io_space->read_dword(address & 0x1fff, mem_mask);
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case 0x6000:
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case 0x7000:
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// pages 6-7: boot space pages 0-1
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return m_boot_space->read_dword(address & 0x1fff, mem_mask);
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}
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}
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// address with upper bytes 0 or 0x7f1
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if ((offset >> 22) == 0x00 || (offset >> 18) == 0x7f1)
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return m_main_space->read_dword(offset << 2, mem_mask);
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// FIXME: currently maps addresses with upper bits 0x00 or 0x7f1 to main memory and everything else to I/O
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if ((address & 0xff000000) == 0x00000000 || (address & 0xfff00000) == 0x7f100000)
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{
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#ifdef ICACHE_ENTRIES
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// if this is an instruction fetch, check the cache first
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if (space.spacenum() == AS_PROGRAM)
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{
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if (m_icache[offset & (ICACHE_ENTRIES-1)].offset != offset)
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{
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m_icache[offset & (ICACHE_ENTRIES - 1)].offset = offset;
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m_icache[offset & (ICACHE_ENTRIES - 1)].data = m_main_space->read_dword(address, mem_mask);
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}
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return m_icache[offset & (ICACHE_ENTRIES - 1)].data;
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}
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else
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#endif
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return m_main_space->read_dword(address, mem_mask);
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}
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else
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return m_io_space->read_dword(offset << 2, mem_mask);
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return m_io_space->read_dword(address, mem_mask);
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}
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WRITE32_MEMBER(cammu_device::mmu_w)
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{
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// handle htlb
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//if (m_maincpu->supervisor_mode() && (offset & ~0x1FFF) == 0)
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if ((offset & ~0x1FFF) == 0)
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u32 ssw = m_ssw_func();
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u32 address = offset << 2;
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// in supervisor mode, the first 8 pages are always mapped via the hard-wired tlb
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if ((ssw & 0x40000000) == 0 && (address & ~0x7fff) == 0)
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{
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switch (offset & 0x3C00)
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switch (address & 0xf000)
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{
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case 0x000:
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case 0x400:
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case 0x800:
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case 0xC00:
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// pages 0-3: main space
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m_main_space->write_dword(offset << 2, data, mem_mask);
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return;
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case 0x0000:
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case 0x1000:
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case 0x1400:
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// pages 4-5: pages 0-1 i/o space
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m_io_space->write_dword((offset & 0x7ff) << 2, data, mem_mask);
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case 0x2000:
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case 0x3000:
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// pages 0-3: main space pages 0-3
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m_main_space->write_dword(address, data, mem_mask);
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return;
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case 0x1800:
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case 0x1C00:
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// pages 6-7: pages 0-1 boot space
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m_boot_space->write_dword((offset & 0x7ff) << 2, data, mem_mask);
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case 0x4000:
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case 0x5000:
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// pages 4-5: i/o space pages 0-1
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m_io_space->write_dword(address & 0x1fff, data, mem_mask);
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return;
|
||||
|
||||
case 0x6000:
|
||||
case 0x7000:
|
||||
// pages 6-7: boot space pages 0-1
|
||||
m_boot_space->write_dword(address & 0x1fff, data, mem_mask);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// address with upper byte 0x00 or upper 3 bytes 0x7f1
|
||||
if ((offset >> 22) == 0x00 || (offset >> 18) == 0x7f1)
|
||||
m_main_space->write_dword(offset << 2, data, mem_mask);
|
||||
// FIXME: currently maps addresses with upper bits 0x00 or 0x7f1 to main memory and everything else to I/O
|
||||
if ((address & 0xff000000) == 0x00000000 || (address & 0xfff00000) == 0x7f100000)
|
||||
m_main_space->write_dword(address, data, mem_mask);
|
||||
else
|
||||
m_io_space->write_dword(offset << 2, data, mem_mask);
|
||||
m_io_space->write_dword(address, data, mem_mask);
|
||||
}
|
||||
|
||||
@ -8,12 +8,22 @@
|
||||
|
||||
#include "emu.h"
|
||||
|
||||
// the following enables a very crude instruction cache - it has known (future)
|
||||
// problems, but speeds up cpu execution quite noticeably in the short term by
|
||||
// avoiding some of the delays in the mame memory subsystem
|
||||
#define ICACHE_ENTRIES 32768
|
||||
|
||||
#define MCFG_CAMMU_SSW_CB(_sswcb) \
|
||||
devcb = &cammu_device::static_set_ssw_callback(*device, DEVCB_##_sswcb);
|
||||
|
||||
class cammu_device : public device_t, public device_memory_interface
|
||||
{
|
||||
public:
|
||||
cammu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
cammu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, uint32_t clock, const char *shortname, const char *source);
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 8);
|
||||
template<class _Object> static devcb_base &static_set_ssw_callback(device_t &device, _Object object) { return downcast<cammu_device &>(device).m_ssw_func.set_callback(object); }
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 32) = 0;
|
||||
|
||||
DECLARE_READ32_MEMBER(mmu_r);
|
||||
DECLARE_WRITE32_MEMBER(mmu_w);
|
||||
@ -30,6 +40,8 @@ protected:
|
||||
virtual const address_space_config *memory_space_config (address_spacenum spacenum) const override;
|
||||
|
||||
private:
|
||||
devcb_read32 m_ssw_func;
|
||||
|
||||
address_space_config m_main_space_config;
|
||||
address_space_config m_io_space_config;
|
||||
address_space_config m_boot_space_config;
|
||||
@ -39,9 +51,43 @@ private:
|
||||
address_space *m_boot_space;
|
||||
|
||||
u32 m_cammu[1024];
|
||||
|
||||
#ifdef ICACHE_ENTRIES
|
||||
struct icache
|
||||
{
|
||||
u32 offset;
|
||||
u32 data;
|
||||
} m_icache[ICACHE_ENTRIES];
|
||||
#endif
|
||||
};
|
||||
|
||||
// device type definition
|
||||
extern const device_type CAMMU;
|
||||
class cammu_c4t_device : public cammu_device
|
||||
{
|
||||
public:
|
||||
cammu_c4t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 32) override;
|
||||
};
|
||||
|
||||
class cammu_c4i_device : public cammu_device
|
||||
{
|
||||
public:
|
||||
cammu_c4i_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 32) override;
|
||||
};
|
||||
|
||||
class cammu_c3_device : public cammu_device
|
||||
{
|
||||
public:
|
||||
cammu_c3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 32) override;
|
||||
};
|
||||
|
||||
// device type definitions
|
||||
extern const device_type CAMMU_C4T;
|
||||
extern const device_type CAMMU_C4I;
|
||||
extern const device_type CAMMU_C3;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user