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srcclean (nw)

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This commit is contained in:
Vas Crabb 2018-09-23 12:22:35 +10:00
parent cb6194cac0
commit 250c06a4d7
83 changed files with 620 additions and 620 deletions
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2
plugins/cheatfind/init.lua
View File

@ -260,7 +260,7 @@ function cheatfind.startplugin()
local formtable = { " I1", " i1", "<I2", ">I2", "<i2", ">i2", "<I4", ">I4", "<i4", ">i4", "<I8", ">I8", "<i8", ">i8", }-- " <f", " >f", " <d", " >d" }
local formname = { "u8", "s8", "little u16", "big u16", "little s16", "big s16",
"little u32", "big u32", "little s32", "big s32", "little u64", "big u64", "little s64", "big s64", }
-- "little float", "big float", "little double", "big double" }
-- "little float", "big float", "little double", "big double" }
local width = 1
local bcd = 0
local align = 0

2
src/devices/bus/abcbus/fd2.cpp
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@ -239,7 +239,7 @@ FLOPPY_FORMATS_END
void abc_fd2_device::device_add_mconfig(machine_config &config)
{
Z80(config, m_maincpu, 4_MHz_XTAL / 2);
Z80(config, m_maincpu, 4_MHz_XTAL / 2);
m_maincpu->set_addrmap(AS_PROGRAM, &abc_fd2_device::abc_fd2_mem);
m_maincpu->set_addrmap(AS_IO, &abc_fd2_device::abc_fd2_io);
m_maincpu->set_daisy_config(daisy_chain);

2
src/devices/bus/abcbus/lux10828.cpp
View File

@ -322,7 +322,7 @@ WRITE_LINE_MEMBER( luxor_55_10828_device::fdc_drq_w )
void luxor_55_10828_device::device_add_mconfig(machine_config &config)
{
Z80(config, m_maincpu, 4_MHz_XTAL / 2);
Z80(config, m_maincpu, 4_MHz_XTAL / 2);
m_maincpu->set_addrmap(AS_PROGRAM, &luxor_55_10828_device::luxor_55_10828_mem);
m_maincpu->set_addrmap(AS_IO, &luxor_55_10828_device::luxor_55_10828_io);
m_maincpu->set_daisy_config(daisy_chain);

2
src/devices/bus/abcbus/lux21046.cpp
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@ -292,7 +292,7 @@ static const z80_daisy_config z80_daisy_chain[] =
void luxor_55_21046_device::device_add_mconfig(machine_config & config)
{
Z80(config, m_maincpu, 16_MHz_XTAL / 4);
Z80(config, m_maincpu, 16_MHz_XTAL / 4);
m_maincpu->set_daisy_config(z80_daisy_chain);
m_maincpu->set_addrmap(AS_PROGRAM, &luxor_55_21046_device::luxor_55_21046_mem);
m_maincpu->set_addrmap(AS_IO, &luxor_55_21046_device::luxor_55_21046_io);

10
src/devices/bus/sbus/artecon.cpp
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@ -4,12 +4,12 @@
Artecon SB-300P 3-serial 1-parallel SBus card skeleton
The Artecon SB series of SBus cards uses up to 4 Cirrus Logic
CL-CD1400 Four-Channel Serial/Parallel Communications Engines.
The Artecon SB series of SBus cards uses up to 4 Cirrus Logic
CL-CD1400 Four-Channel Serial/Parallel Communications Engines.
Each chip supports up to four full-duplex serial channels, or three
full-duplex serial channels and one high-speed bidirectional parallel
channel.
Each chip supports up to four full-duplex serial channels, or three
full-duplex serial channels and one high-speed bidirectional parallel
channel.
***************************************************************************/

34
src/devices/bus/sbus/cgsix.cpp
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@ -106,23 +106,23 @@ uint8_t sbus_cgsix_device::perform_rasterop(uint8_t src, uint8_t dst)
uint8_t value = 0;
switch (rop)
{
case ROP_CLR: break;
case ROP_SRC_NOR_DST: value = ~(s | d); break;
case ROP_NSRC_AND_DST: value = ~s & d; break;
case ROP_NOT_SRC: value = ~s; break;
case ROP_SRC_AND_NDST: value = s & ~d; break;
case ROP_NOT_DST: value = ~d; break;
case ROP_SRC_XOR_DST: value = s ^ d; break;
case ROP_SRC_NAND_DST: value = ~(s & d); break;
case ROP_SRC_AND_DST: value = s & d; break;
case ROP_SRC_XNOR_DST: value = ~(s ^ d); break;
case ROP_DST: value = d; break;
case ROP_NSRC_OR_DST: value = ~s | d; break;
case ROP_SRC: value = s; break;
case ROP_SRC_OR_NDST: value = s | ~d; break;
case ROP_SRC_OR_DST: value = s | d; break;
case ROP_SET: value = 0xff; break;
default: value = 0; break;
case ROP_CLR: break;
case ROP_SRC_NOR_DST: value = ~(s | d); break;
case ROP_NSRC_AND_DST: value = ~s & d; break;
case ROP_NOT_SRC: value = ~s; break;
case ROP_SRC_AND_NDST: value = s & ~d; break;
case ROP_NOT_DST: value = ~d; break;
case ROP_SRC_XOR_DST: value = s ^ d; break;
case ROP_SRC_NAND_DST: value = ~(s & d); break;
case ROP_SRC_AND_DST: value = s & d; break;
case ROP_SRC_XNOR_DST: value = ~(s ^ d); break;
case ROP_DST: value = d; break;
case ROP_NSRC_OR_DST: value = ~s | d; break;
case ROP_SRC: value = s; break;
case ROP_SRC_OR_NDST: value = s | ~d; break;
case ROP_SRC_OR_DST: value = s | d; break;
case ROP_SET: value = 0xff; break;
default: value = 0; break;
}
result |= value & mask;
}

376
src/devices/bus/sbus/cgsix.h
View File

@ -52,113 +52,113 @@ protected:
enum
{
ROP_CLR = 0x00,
ROP_SRC_NOR_DST = 0x01,
ROP_NSRC_AND_DST = 0x02,
ROP_NOT_SRC = 0x03,
ROP_SRC_AND_NDST = 0x04,
ROP_NOT_DST = 0x05,
ROP_SRC_XOR_DST = 0x06,
ROP_SRC_NAND_DST = 0x07,
ROP_SRC_AND_DST = 0x08,
ROP_SRC_XNOR_DST = 0x09,
ROP_DST = 0x0a,
ROP_NSRC_OR_DST = 0x0b,
ROP_SRC = 0x0c,
ROP_SRC_OR_NDST = 0x0d,
ROP_SRC_OR_DST = 0x0e,
ROP_SET = 0x0f
ROP_CLR = 0x00,
ROP_SRC_NOR_DST = 0x01,
ROP_NSRC_AND_DST = 0x02,
ROP_NOT_SRC = 0x03,
ROP_SRC_AND_NDST = 0x04,
ROP_NOT_DST = 0x05,
ROP_SRC_XOR_DST = 0x06,
ROP_SRC_NAND_DST = 0x07,
ROP_SRC_AND_DST = 0x08,
ROP_SRC_XNOR_DST = 0x09,
ROP_DST = 0x0a,
ROP_NSRC_OR_DST = 0x0b,
ROP_SRC = 0x0c,
ROP_SRC_OR_NDST = 0x0d,
ROP_SRC_OR_DST = 0x0e,
ROP_SET = 0x0f
};
enum
{
FBC_MISC_INDEX_SHIFT = 4,
FBC_MISC_INDEX_MOD_SHIFT = 6,
FBC_MISC_BDISP_SHIFT = 7,
FBC_MISC_BREAD_SHIFT = 9,
FBC_MISC_BWRITE1_SHIFT = 11,
FBC_MISC_BWRITE0_SHIFT = 13,
FBC_MISC_DRAW_SHIFT = 15,
FBC_MISC_DATA_SHIFT = 17,
FBC_MISC_VBLANK_SHIFT = 19,
FBC_MISC_BLIT_SHIFT = 20
FBC_MISC_INDEX_SHIFT = 4,
FBC_MISC_INDEX_MOD_SHIFT = 6,
FBC_MISC_BDISP_SHIFT = 7,
FBC_MISC_BREAD_SHIFT = 9,
FBC_MISC_BWRITE1_SHIFT = 11,
FBC_MISC_BWRITE0_SHIFT = 13,
FBC_MISC_DRAW_SHIFT = 15,
FBC_MISC_DATA_SHIFT = 17,
FBC_MISC_VBLANK_SHIFT = 19,
FBC_MISC_BLIT_SHIFT = 20
};
enum
{
FBC_MISC_INDEX_MASK = 0x3,
FBC_MISC_INDEX_MOD_MASK = 0x1,
FBC_MISC_BDISP_MASK = 0x3,
FBC_MISC_BREAD_MASK = 0x3,
FBC_MISC_BWRITE1_MASK = 0x3,
FBC_MISC_BWRITE0_MASK = 0x3,
FBC_MISC_DRAW_MASK = 0x3,
FBC_MISC_DATA_MASK = 0x3,
FBC_MISC_VBLANK_MASK = 0x1,
FBC_MISC_BLIT_MASK = 0x3
FBC_MISC_INDEX_MASK = 0x3,
FBC_MISC_INDEX_MOD_MASK = 0x1,
FBC_MISC_BDISP_MASK = 0x3,
FBC_MISC_BREAD_MASK = 0x3,
FBC_MISC_BWRITE1_MASK = 0x3,
FBC_MISC_BWRITE0_MASK = 0x3,
FBC_MISC_DRAW_MASK = 0x3,
FBC_MISC_DATA_MASK = 0x3,
FBC_MISC_VBLANK_MASK = 0x1,
FBC_MISC_BLIT_MASK = 0x3
};
enum
{
FBC_MISC_BDISP_IGNORE = 0,
FBC_MISC_BDISP_0 = 1,
FBC_MISC_BDISP_1 = 2,
FBC_MISC_BDISP_ILLEGAL = 3,
FBC_MISC_BDISP_IGNORE = 0,
FBC_MISC_BDISP_0 = 1,
FBC_MISC_BDISP_1 = 2,
FBC_MISC_BDISP_ILLEGAL = 3,
FBC_MISC_BREAD_IGNORE = 0,
FBC_MISC_BREAD_0 = 1,
FBC_MISC_BREAD_1 = 2,
FBC_MISC_BREAD_ILLEGAL = 3,
FBC_MISC_BREAD_IGNORE = 0,
FBC_MISC_BREAD_0 = 1,
FBC_MISC_BREAD_1 = 2,
FBC_MISC_BREAD_ILLEGAL = 3,
FBC_MISC_BWRITE1_IGNORE = 0,
FBC_MISC_BWRITE1_ENABLE = 1,
FBC_MISC_BWRITE1_DISABLE = 2,
FBC_MISC_BWRITE1_ILLEGAL = 3,
FBC_MISC_BWRITE1_IGNORE = 0,
FBC_MISC_BWRITE1_ENABLE = 1,
FBC_MISC_BWRITE1_DISABLE = 2,
FBC_MISC_BWRITE1_ILLEGAL = 3,
FBC_MISC_BWRITE0_IGNORE = 0,
FBC_MISC_BWRITE0_ENABLE = 1,
FBC_MISC_BWRITE0_DISABLE = 2,
FBC_MISC_BWRITE0_ILLEGAL = 3,
FBC_MISC_BWRITE0_IGNORE = 0,
FBC_MISC_BWRITE0_ENABLE = 1,
FBC_MISC_BWRITE0_DISABLE = 2,
FBC_MISC_BWRITE0_ILLEGAL = 3,
FBC_MISC_DRAW_IGNORE = 0,
FBC_MISC_DRAW_RENDER = 1,
FBC_MISC_DRAW_PICK = 2,
FBC_MISC_DRAW_ILLEGAL = 3,
FBC_MISC_DRAW_IGNORE = 0,
FBC_MISC_DRAW_RENDER = 1,
FBC_MISC_DRAW_PICK = 2,
FBC_MISC_DRAW_ILLEGAL = 3,
FBC_MISC_DATA_IGNORE = 0,
FBC_MISC_DATA_COLOR8 = 1,
FBC_MISC_DATA_COLOR1 = 2,
FBC_MISC_DATA_HRMONO = 3,
FBC_MISC_DATA_IGNORE = 0,
FBC_MISC_DATA_COLOR8 = 1,
FBC_MISC_DATA_COLOR1 = 2,
FBC_MISC_DATA_HRMONO = 3,
FBC_MISC_BLIT_IGNORE = 0,
FBC_MISC_BLIT_NOSRC = 1,
FBC_MISC_BLIT_SRC = 2,
FBC_MISC_BLIT_ILLEGAL = 3
FBC_MISC_BLIT_IGNORE = 0,
FBC_MISC_BLIT_NOSRC = 1,
FBC_MISC_BLIT_SRC = 2,
FBC_MISC_BLIT_ILLEGAL = 3
};
inline uint32_t fbc_misc_index() { return (m_fbc.m_misc >> FBC_MISC_INDEX_SHIFT) & FBC_MISC_INDEX_MASK; }
inline uint32_t fbc_misc_index_mod() { return (m_fbc.m_misc >> FBC_MISC_INDEX_MOD_SHIFT) & FBC_MISC_INDEX_MOD_MASK; }
inline uint32_t fbc_misc_bdisp() { return (m_fbc.m_misc >> FBC_MISC_BDISP_SHIFT) & FBC_MISC_BDISP_MASK; }
inline uint32_t fbc_misc_bread() { return (m_fbc.m_misc >> FBC_MISC_BREAD_SHIFT) & FBC_MISC_BREAD_MASK; }
inline uint32_t fbc_misc_bwrite1() { return (m_fbc.m_misc >> FBC_MISC_BWRITE1_SHIFT) & FBC_MISC_BWRITE1_MASK; }
inline uint32_t fbc_misc_bwrite0() { return (m_fbc.m_misc >> FBC_MISC_BWRITE0_SHIFT) & FBC_MISC_BWRITE0_MASK; }
inline uint32_t fbc_misc_draw() { return (m_fbc.m_misc >> FBC_MISC_DRAW_SHIFT) & FBC_MISC_DRAW_MASK; }
inline uint32_t fbc_misc_data() { return (m_fbc.m_misc >> FBC_MISC_DATA_SHIFT) & FBC_MISC_DATA_MASK; }
inline uint32_t fbc_misc_blit() { return (m_fbc.m_misc >> FBC_MISC_BLIT_SHIFT) & FBC_MISC_BLIT_MASK; }
inline uint32_t fbc_misc_index() { return (m_fbc.m_misc >> FBC_MISC_INDEX_SHIFT) & FBC_MISC_INDEX_MASK; }
inline uint32_t fbc_misc_index_mod() { return (m_fbc.m_misc >> FBC_MISC_INDEX_MOD_SHIFT) & FBC_MISC_INDEX_MOD_MASK; }
inline uint32_t fbc_misc_bdisp() { return (m_fbc.m_misc >> FBC_MISC_BDISP_SHIFT) & FBC_MISC_BDISP_MASK; }
inline uint32_t fbc_misc_bread() { return (m_fbc.m_misc >> FBC_MISC_BREAD_SHIFT) & FBC_MISC_BREAD_MASK; }
inline uint32_t fbc_misc_bwrite1() { return (m_fbc.m_misc >> FBC_MISC_BWRITE1_SHIFT) & FBC_MISC_BWRITE1_MASK; }
inline uint32_t fbc_misc_bwrite0() { return (m_fbc.m_misc >> FBC_MISC_BWRITE0_SHIFT) & FBC_MISC_BWRITE0_MASK; }
inline uint32_t fbc_misc_draw() { return (m_fbc.m_misc >> FBC_MISC_DRAW_SHIFT) & FBC_MISC_DRAW_MASK; }
inline uint32_t fbc_misc_data() { return (m_fbc.m_misc >> FBC_MISC_DATA_SHIFT) & FBC_MISC_DATA_MASK; }
inline uint32_t fbc_misc_blit() { return (m_fbc.m_misc >> FBC_MISC_BLIT_SHIFT) & FBC_MISC_BLIT_MASK; }
enum
{
FBC_RASTEROP_ROP00_SHIFT = 0,
FBC_RASTEROP_ROP01_SHIFT = 4,
FBC_RASTEROP_ROP10_SHIFT = 8,
FBC_RASTEROP_ROP11_SHIFT = 12,
FBC_RASTEROP_PLOT_SHIFT = 16,
FBC_RASTEROP_RAST_SHIFT = 17,
FBC_RASTEROP_ATTR_SHIFT = 22,
FBC_RASTEROP_POLYG_SHIFT = 24,
FBC_RASTEROP_PATT_SHIFT = 26,
FBC_RASTEROP_PIXEL_SHIFT = 28,
FBC_RASTEROP_PLANE_SHIFT = 30
FBC_RASTEROP_ROP00_SHIFT = 0,
FBC_RASTEROP_ROP01_SHIFT = 4,
FBC_RASTEROP_ROP10_SHIFT = 8,
FBC_RASTEROP_ROP11_SHIFT = 12,
FBC_RASTEROP_PLOT_SHIFT = 16,
FBC_RASTEROP_RAST_SHIFT = 17,
FBC_RASTEROP_ATTR_SHIFT = 22,
FBC_RASTEROP_POLYG_SHIFT = 24,
FBC_RASTEROP_PATT_SHIFT = 26,
FBC_RASTEROP_PIXEL_SHIFT = 28,
FBC_RASTEROP_PLANE_SHIFT = 30
};
enum
@ -167,13 +167,13 @@ protected:
FBC_RASTEROP_ROP01_MASK = 0xf,
FBC_RASTEROP_ROP10_MASK = 0xf,
FBC_RASTEROP_ROP11_MASK = 0xf,
FBC_RASTEROP_PLOT_MASK = 0x1,
FBC_RASTEROP_RAST_MASK = 0x1,
FBC_RASTEROP_ATTR_MASK = 0x3,
FBC_RASTEROP_PLOT_MASK = 0x1,
FBC_RASTEROP_RAST_MASK = 0x1,
FBC_RASTEROP_ATTR_MASK = 0x3,
FBC_RASTEROP_POLYG_MASK = 0x3,
FBC_RASTEROP_PATT_MASK = 0x3,
FBC_RASTEROP_PATT_MASK = 0x3,
FBC_RASTEROP_PIXEL_MASK = 0x3,
FBC_RASTEROP_PLANE_MASK = 0x3
FBC_RASTEROP_PLANE_MASK = 0x3
};
enum
@ -210,124 +210,124 @@ protected:
FBC_RASTEROP_PLANE_MSK = 3
};
inline uint32_t fbc_rasterop_rop00() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP00_SHIFT) & FBC_RASTEROP_ROP00_MASK; }
inline uint32_t fbc_rasterop_rop01() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP01_SHIFT) & FBC_RASTEROP_ROP01_MASK; }
inline uint32_t fbc_rasterop_rop10() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP10_SHIFT) & FBC_RASTEROP_ROP10_MASK; }
inline uint32_t fbc_rasterop_rop11() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP11_SHIFT) & FBC_RASTEROP_ROP11_MASK; }
inline uint32_t fbc_rasterop_plot() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLOT_SHIFT) & FBC_RASTEROP_PLOT_MASK; }
inline uint32_t fbc_rasterop_rast() { return (m_fbc.m_rasterop >> FBC_RASTEROP_RAST_SHIFT) & FBC_RASTEROP_RAST_MASK; }
inline uint32_t fbc_rasterop_attr() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ATTR_SHIFT) & FBC_RASTEROP_ATTR_MASK; }
inline uint32_t fbc_rasterop_polyg() { return (m_fbc.m_rasterop >> FBC_RASTEROP_POLYG_SHIFT) & FBC_RASTEROP_POLYG_MASK; }
inline uint32_t fbc_rasterop_pattern() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PATT_SHIFT) & FBC_RASTEROP_PATT_MASK; }
inline uint32_t fbc_rasterop_pixel() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PIXEL_SHIFT) & FBC_RASTEROP_PIXEL_MASK; }
inline uint32_t fbc_rasterop_plane() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLANE_SHIFT) & FBC_RASTEROP_PLANE_MASK; }
inline uint32_t fbc_rasterop_rop00() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP00_SHIFT) & FBC_RASTEROP_ROP00_MASK; }
inline uint32_t fbc_rasterop_rop01() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP01_SHIFT) & FBC_RASTEROP_ROP01_MASK; }
inline uint32_t fbc_rasterop_rop10() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP10_SHIFT) & FBC_RASTEROP_ROP10_MASK; }
inline uint32_t fbc_rasterop_rop11() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP11_SHIFT) & FBC_RASTEROP_ROP11_MASK; }
inline uint32_t fbc_rasterop_plot() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLOT_SHIFT) & FBC_RASTEROP_PLOT_MASK; }
inline uint32_t fbc_rasterop_rast() { return (m_fbc.m_rasterop >> FBC_RASTEROP_RAST_SHIFT) & FBC_RASTEROP_RAST_MASK; }
inline uint32_t fbc_rasterop_attr() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ATTR_SHIFT) & FBC_RASTEROP_ATTR_MASK; }
inline uint32_t fbc_rasterop_polyg() { return (m_fbc.m_rasterop >> FBC_RASTEROP_POLYG_SHIFT) & FBC_RASTEROP_POLYG_MASK; }
inline uint32_t fbc_rasterop_pattern() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PATT_SHIFT) & FBC_RASTEROP_PATT_MASK; }
inline uint32_t fbc_rasterop_pixel() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PIXEL_SHIFT) & FBC_RASTEROP_PIXEL_MASK; }
inline uint32_t fbc_rasterop_plane() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLANE_SHIFT) & FBC_RASTEROP_PLANE_MASK; }
enum
{
FBC_MISC = 0x004/4,
FBC_CLIP_CHECK = 0x008/4,
FBC_MISC = 0x004/4,
FBC_CLIP_CHECK = 0x008/4,
FBC_STATUS = 0x010/4,
FBC_DRAW_STATUS = 0x014/4,
FBC_STATUS = 0x010/4,
FBC_DRAW_STATUS = 0x014/4,
FBC_BLIT_STATUS = 0x018/4,
FBC_FONT = 0x01c/4,
FBC_FONT = 0x01c/4,
FBC_X0 = 0x080/4,
FBC_Y0 = 0x084/4,
FBC_Z0 = 0x088/4,
FBC_COLOR0 = 0x08c/4,
FBC_X1 = 0x090/4,
FBC_Y1 = 0x094/4,
FBC_Z1 = 0x098/4,
FBC_COLOR1 = 0x09c/4,
FBC_X2 = 0x0a0/4,
FBC_Y2 = 0x0a4/4,
FBC_Z2 = 0x0a8/4,
FBC_COLOR2 = 0x0ac/4,
FBC_X3 = 0x0b0/4,
FBC_Y3 = 0x0b4/4,
FBC_Z3 = 0x0b8/4,
FBC_COLOR3 = 0x0bc/4,
FBC_X0 = 0x080/4,
FBC_Y0 = 0x084/4,
FBC_Z0 = 0x088/4,
FBC_COLOR0 = 0x08c/4,
FBC_X1 = 0x090/4,
FBC_Y1 = 0x094/4,
FBC_Z1 = 0x098/4,
FBC_COLOR1 = 0x09c/4,
FBC_X2 = 0x0a0/4,
FBC_Y2 = 0x0a4/4,
FBC_Z2 = 0x0a8/4,
FBC_COLOR2 = 0x0ac/4,
FBC_X3 = 0x0b0/4,
FBC_Y3 = 0x0b4/4,
FBC_Z3 = 0x0b8/4,
FBC_COLOR3 = 0x0bc/4,
FBC_RASTER_OFFX = 0x0c0/4,
FBC_RASTER_OFFX = 0x0c0/4,
FBC_RASTER_OFFY = 0x0c4/4,
FBC_AUTOINCX = 0x0d0/4,
FBC_AUTOINCY = 0x0d4/4,
FBC_CLIP_MINX = 0x0e0/4,
FBC_CLIP_MINY = 0x0e4/4,
FBC_CLIP_MAXX = 0x0f0/4,
FBC_CLIP_MAXY = 0x0f4/4,
FBC_AUTOINCX = 0x0d0/4,
FBC_AUTOINCY = 0x0d4/4,
FBC_CLIP_MINX = 0x0e0/4,
FBC_CLIP_MINY = 0x0e4/4,
FBC_CLIP_MAXX = 0x0f0/4,
FBC_CLIP_MAXY = 0x0f4/4,
FBC_FCOLOR = 0x100/4,
FBC_BCOLOR = 0x104/4,
FBC_RASTEROP = 0x108/4,
FBC_PLANE_MASK = 0x10c/4,
FBC_PIXEL_MASK = 0x110/4,
FBC_FCOLOR = 0x100/4,
FBC_BCOLOR = 0x104/4,
FBC_RASTEROP = 0x108/4,
FBC_PLANE_MASK = 0x10c/4,
FBC_PIXEL_MASK = 0x110/4,
FBC_PATT_ALIGN = 0x11c/4,
FBC_PATTERN0 = 0x120/4,
FBC_PATTERN1 = 0x124/4,
FBC_PATTERN2 = 0x128/4,
FBC_PATTERN3 = 0x12c/4,
FBC_PATTERN4 = 0x130/4,
FBC_PATTERN5 = 0x134/4,
FBC_PATTERN6 = 0x138/4,
FBC_PATTERN7 = 0x13c/4,
FBC_PATT_ALIGN = 0x11c/4,
FBC_PATTERN0 = 0x120/4,
FBC_PATTERN1 = 0x124/4,
FBC_PATTERN2 = 0x128/4,
FBC_PATTERN3 = 0x12c/4,
FBC_PATTERN4 = 0x130/4,
FBC_PATTERN5 = 0x134/4,
FBC_PATTERN6 = 0x138/4,
FBC_PATTERN7 = 0x13c/4,
FBC_IPOINT_ABSX = 0x800/4,
FBC_IPOINT_ABSX = 0x800/4,
FBC_IPOINT_ABSY = 0x804/4,
FBC_IPOINT_ABSZ = 0x808/4,
FBC_IPOINT_RELX = 0x810/4,
FBC_IPOINT_RELX = 0x810/4,
FBC_IPOINT_RELY = 0x814/4,
FBC_IPOINT_RELZ = 0x818/4,
FBC_IPOINT_R = 0x830/4,
FBC_IPOINT_G = 0x834/4,
FBC_IPOINT_B = 0x838/4,
FBC_IPOINT_A = 0x83c/4,
FBC_IPOINT_R = 0x830/4,
FBC_IPOINT_G = 0x834/4,
FBC_IPOINT_B = 0x838/4,
FBC_IPOINT_A = 0x83c/4,
FBC_ILINE_ABSX = 0x840/4,
FBC_ILINE_ABSY = 0x844/4,
FBC_ILINE_ABSZ = 0x848/4,
FBC_ILINE_RELX = 0x850/4,
FBC_ILINE_RELY = 0x854/4,
FBC_ILINE_RELZ = 0x858/4,
FBC_ILINE_R = 0x870/4,
FBC_ILINE_G = 0x874/4,
FBC_ILINE_B = 0x878/4,
FBC_ILINE_A = 0x87c/4,
FBC_ILINE_ABSX = 0x840/4,
FBC_ILINE_ABSY = 0x844/4,
FBC_ILINE_ABSZ = 0x848/4,
FBC_ILINE_RELX = 0x850/4,
FBC_ILINE_RELY = 0x854/4,
FBC_ILINE_RELZ = 0x858/4,
FBC_ILINE_R = 0x870/4,
FBC_ILINE_G = 0x874/4,
FBC_ILINE_B = 0x878/4,
FBC_ILINE_A = 0x87c/4,
FBC_ITRI_ABSX = 0x880/4,
FBC_ITRI_ABSY = 0x884/4,
FBC_ITRI_ABSZ = 0x888/4,
FBC_ITRI_RELX = 0x890/4,
FBC_ITRI_RELY = 0x894/4,
FBC_ITRI_RELZ = 0x898/4,
FBC_ITRI_R = 0x8b0/4,
FBC_ITRI_G = 0x8b4/4,
FBC_ITRI_B = 0x8b8/4,
FBC_ITRI_A = 0x8bc/4,
FBC_ITRI_ABSX = 0x880/4,
FBC_ITRI_ABSY = 0x884/4,
FBC_ITRI_ABSZ = 0x888/4,
FBC_ITRI_RELX = 0x890/4,
FBC_ITRI_RELY = 0x894/4,
FBC_ITRI_RELZ = 0x898/4,
FBC_ITRI_R = 0x8b0/4,
FBC_ITRI_G = 0x8b4/4,
FBC_ITRI_B = 0x8b8/4,
FBC_ITRI_A = 0x8bc/4,
FBC_IQUAD_ABSX = 0x8c0/4,
FBC_IQUAD_ABSY = 0x8c4/4,
FBC_IQUAD_ABSZ = 0x8c8/4,
FBC_IQUAD_RELX = 0x8d0/4,
FBC_IQUAD_RELY = 0x8d4/4,
FBC_IQUAD_RELZ = 0x8d8/4,
FBC_IQUAD_R = 0x8f0/4,
FBC_IQUAD_G = 0x8f4/4,
FBC_IQUAD_B = 0x8f8/4,
FBC_IQUAD_A = 0x8fc/4,
FBC_IQUAD_ABSX = 0x8c0/4,
FBC_IQUAD_ABSY = 0x8c4/4,
FBC_IQUAD_ABSZ = 0x8c8/4,
FBC_IQUAD_RELX = 0x8d0/4,
FBC_IQUAD_RELY = 0x8d4/4,
FBC_IQUAD_RELZ = 0x8d8/4,
FBC_IQUAD_R = 0x8f0/4,
FBC_IQUAD_G = 0x8f4/4,
FBC_IQUAD_B = 0x8f8/4,
FBC_IQUAD_A = 0x8fc/4,
FBC_IRECT_ABSX = 0x900/4,
FBC_IRECT_ABSY = 0x904/4,
FBC_IRECT_ABSZ = 0x908/4,
FBC_IRECT_RELX = 0x910/4,
FBC_IRECT_RELY = 0x914/4,
FBC_IRECT_RELZ = 0x918/4,
FBC_IRECT_R = 0x930/4,
FBC_IRECT_G = 0x934/4,
FBC_IRECT_B = 0x938/4,
FBC_IRECT_A = 0x93c/4,
FBC_IRECT_ABSX = 0x900/4,
FBC_IRECT_ABSY = 0x904/4,
FBC_IRECT_ABSZ = 0x908/4,
FBC_IRECT_RELX = 0x910/4,
FBC_IRECT_RELY = 0x914/4,
FBC_IRECT_RELZ = 0x918/4,
FBC_IRECT_R = 0x930/4,
FBC_IRECT_G = 0x934/4,
FBC_IRECT_B = 0x938/4,
FBC_IRECT_A = 0x93c/4,
};
struct vertex_t

10
src/devices/bus/sbus/hme.cpp
View File

@ -4,11 +4,11 @@
Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" skeleton
Notable parts on board:
- 1x 32-pin PLCC ROM, label 525 / 1409 / -08 on separate lines
- 1x Sun STP2002QFP, marked 100-4156-05 / 609-0392458 / DP03972
- 1x National Semiconductor DP83840AVCE-1 Ethernet Physical Layer
- 1x National Semiconductor DP83223V Twisted Pair Transceiver
Notable parts on board:
- 1x 32-pin PLCC ROM, label 525 / 1409 / -08 on separate lines
- 1x Sun STP2002QFP, marked 100-4156-05 / 609-0392458 / DP03972
- 1x National Semiconductor DP83840AVCE-1 Ethernet Physical Layer
- 1x National Semiconductor DP83223V Twisted Pair Transceiver
***************************************************************************/

2
src/devices/bus/sbus/sbus.h
View File

@ -106,7 +106,7 @@ protected:
address_space *m_space;
devcb_write_line m_irq_cb[7];
devcb_write32 m_buserr;
devcb_write32 m_buserr;
device_sbus_card_interface *m_device_list[3];

10
src/devices/bus/sbus/sunpc.cpp
View File

@ -4,11 +4,11 @@
Sun SunPC 5x86 Accelerator (501-4230) skeleton
Notable parts on board:
- 1x AMD AM27C256 PLCC ROM
- 1x Motorola SunPC Accelerator 100-3069-03, mfr/date AANL9732
- 6x Cypress CY7B185-10VC 64kBit Static RAM
- 1x AMD 5x86 (under heatsink; markings unknown)
Notable parts on board:
- 1x AMD AM27C256 PLCC ROM
- 1x Motorola SunPC Accelerator 100-3069-03, mfr/date AANL9732
- 6x Cypress CY7B185-10VC 64kBit Static RAM
- 1x AMD 5x86 (under heatsink; markings unknown)
***************************************************************************/

32
src/devices/cpu/sparc/mb86901.cpp
View File

@ -50,7 +50,7 @@ mb86901_device::mb86901_device(const machine_config &mconfig, const char *tag, d
: cpu_device(mconfig, MB86901, tag, owner, clock)
, m_mmu(*this, finder_base::DUMMY_TAG)
{
m_default_config = address_space_config("program", ENDIANNESS_BIG, 32, 32);
m_default_config = address_space_config("program", ENDIANNESS_BIG, 32, 32);
}
@ -471,8 +471,8 @@ void mb86901_device::device_reset()
device_memory_interface::space_config_vector mb86901_device::memory_space_config() const
{
space_config_vector config_vector;
config_vector.push_back(std::make_pair(AS_PROGRAM, &m_default_config));
space_config_vector config_vector;
config_vector.push_back(std::make_pair(AS_PROGRAM, &m_default_config));
return config_vector;
}
@ -3376,26 +3376,26 @@ void mb86901_device::execute_trap()
/* The SPARC Instruction Manual: Version 8, page 159, "Appendix C - ISP Descriptions - C.6. Instruction Dispatch" (SPARCv8.pdf, pg. 156)
illegal_IU_instr :- (
if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
or
( ((op=11) or (op=10)) and (op3=unassigned) )
then 1 else 0
if ( ( (op == 00) and (op2 == 000) ) { UNIMP instruction }
or
( ((op=11) or (op=10)) and (op3=unassigned) )
then 1 else 0
if (illegal_IU_instr = 1) then (
trap <- 1
illegal_instruction <- 1
trap <- 1
illegal_instruction <- 1
);
if ((FPop1 or FPop2 or FBfcc) and ((EF = 0) or (bp_FPU_present = 0))) then (
trap <- 1;
fp_disabled <- 1
trap <- 1;
fp_disabled <- 1
);
if (CPop1 or CPop2 or CBccc) and ((EC = 0) or (bp_CP_present = 0))) then (
trap <- 1;
cp_disabled <- 1
trap <- 1;
cp_disabled <- 1
);
next;
if (trap = 0) then (
{ code for specific instruction, defined below }
{ code for specific instruction, defined below }
);
*/
@ -3653,8 +3653,8 @@ void mb86901_device::run_loop()
{
/*if (HOLD_BUS)
{
m_icount--;
continue;
m_icount--;
continue;
}*/
if (CHECK_DEBUG)

2
src/devices/cpu/sparc/sparc.h
View File

@ -124,7 +124,7 @@ protected:
required_device<sparc_mmu_interface> m_mmu;
// address spaces
address_space_config m_default_config;
address_space_config m_default_config;
// memory access
uint32_t read_sized_word(const uint8_t asi, const uint32_t address, const uint32_t mem_mask);

10
src/devices/cpu/sparc/sparcdefs.h
View File

@ -81,7 +81,7 @@
#define WIM m_wim
#define TBR m_tbr
#define OP_NS (op & 0xc0000000)
#define OP_NS (op & 0xc0000000)
#define OP (op >> 30)
#define OP2 ((op >> 22) & 7)
@ -155,10 +155,10 @@
#define OP_ALU u32(2)
#define OP_LDST u32(3)
#define OP_TYPE0_NS (OP_TYPE0 << 30)
#define OP_CALL_NS (OP_CALL << 30)
#define OP_ALU_NS (OP_ALU << 30)
#define OP_LDST_NS (OP_LDST << 30)
#define OP_TYPE0_NS (OP_TYPE0 << 30)
#define OP_CALL_NS (OP_CALL << 30)
#define OP_ALU_NS (OP_ALU << 30)
#define OP_LDST_NS (OP_LDST << 30)
#define OP2_UNIMP 0
#define OP2_BICC 2

2
src/devices/cpu/z8/z8.cpp
View File

@ -358,7 +358,7 @@ uint8_t z8_device::register_read(uint8_t offset)
{
case Z8_P01M_P1_MODE_OUTPUT:
data = m_output[offset];
break;
break;
case Z8_P01M_P1_MODE_INPUT:
mask = 0xff;
break;

10
src/devices/machine/am79c90.cpp
View File

@ -4,10 +4,10 @@
AMD Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
TODO:
- Communication with the outside world
- Error handling
- Clocks
TODO:
- Communication with the outside world
- Error handling
- Clocks
*****************************************************************************/
@ -512,7 +512,7 @@ WRITE16_MEMBER(am79c90_device::regs_w)
m_mode = init_block[0];
m_physical_addr = ((uint64_t)init_block[3] << 32) | ((uint64_t)init_block[2] << 16) | (uint64_t)init_block[1];
m_logical_addr_filter = ((uint64_t)init_block[7] << 48) | ((uint64_t)init_block[6] << 32)
| ((uint64_t)init_block[5] << 16) | (uint64_t)init_block[4];
| ((uint64_t)init_block[5] << 16) | (uint64_t)init_block[4];
m_recv_ring_addr = (((uint32_t)init_block[9] << 16) | (uint32_t)init_block[8]) & 0x00fffff8;
m_recv_ring_addr |= 0xff000000;
m_transmit_ring_addr = (((uint32_t)init_block[11] << 16) | (uint32_t)init_block[10]) & 0x00fffff8;

8
src/devices/machine/am79c90.h
View File

@ -4,10 +4,10 @@
AMD Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)
TODO:
- Communication with the outside world
- Error handling
- Clocks
TODO:
- Communication with the outside world
- Error handling
- Clocks
******************************************************************************
_____ _____

6
src/devices/machine/hd64610.h
View File

@ -69,9 +69,9 @@ private:
devcb_write_line m_out_irq_cb;
devcb_write_line m_out_1hz_cb;
uint8_t m_regs[0x10]; // Internal registers
int m_hline_state; // H-Start/Stop line
int m_irq_out; // alarm output
uint8_t m_regs[0x10]; // Internal registers
int m_hline_state; // H-Start/Stop line
int m_irq_out; // alarm output
emu_timer *m_counter_timer;
};

12
src/devices/machine/sun4c_mmu.cpp
View File

@ -341,11 +341,11 @@ template uint32_t sun4c_mmu_device::insn_data_r<sun4c_mmu_device::SUPER_DATA>(co
template <sun4c_mmu_device::insn_data_mode MODE>
uint32_t sun4c_mmu_device::insn_data_r(const uint32_t offset, const uint32_t mem_mask)
{
// supervisor program fetches in boot state are special
if (m_fetch_bootrom && MODE == SUPER_INSN)
{
return m_rom_ptr[offset & 0x1ffff];
}
// supervisor program fetches in boot state are special
if (m_fetch_bootrom && MODE == SUPER_INSN)
{
return m_rom_ptr[offset & 0x1ffff];
}
// it's translation time
const uint32_t pmeg = m_curr_segmap_masked[(offset >> 16) & 0xfff];
@ -474,7 +474,7 @@ void sun4c_mmu_device::insn_data_w(const uint32_t offset, const uint32_t data, c
else
{
//logerror("sun4c: INVALID PTE entry %d %08x accessed! data=%08x vaddr=%x PC=%x\n", entry_index, m_pagemap[entry_index].to_uint(), data, offset <<2, m_cpu->pc());
m_host->set_mae();
m_host->set_mae();
m_buserr[0] |= 0x8080; // write cycle, invalid PTE
m_buserr[1] = offset << 2;
if (mem_mask != ~0 && mem_mask != 0xffff0000 && mem_mask != 0xff000000)

2
src/devices/machine/vt82c496.h
View File

@ -20,7 +20,7 @@ public:
// construction/destruction
vt82c496_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
template <typename T> void set_cputag(T &&tag) { m_cpu.set_tag(std::forward<T>(tag)); }
template <typename T> void set_cputag(T &&tag) { m_cpu.set_tag(std::forward<T>(tag)); }
template <typename T> void set_ramtag(T &&tag) { m_ram.set_tag(std::forward<T>(tag)); }
template <typename T> void set_isatag(T &&tag) { m_rom.set_tag(std::forward<T>(tag)); }

4
src/emu/emumem.cpp
View File

@ -1890,7 +1890,7 @@ template<int Width, int AddrShift, endianness_t Endian> void address_space_speci
VPRINTF(("address_space::install_readwrite_port(%s-%s mirror=%s, read=\"%s\" / write=\"%s\")\n",
core_i64_hex_format(addrstart, m_addrchars), core_i64_hex_format(addrend, m_addrchars),
core_i64_hex_format(addrmirror, m_addrchars),
rtag.empty() ? "(none)" : rtag.c_str(), wtag.empty() ? "(none)" : wtag.c_str()));
rtag.empty() ? "(none)" : rtag.c_str(), wtag.empty() ? "(none)" : wtag.c_str()));
offs_t nstart, nend, nmask, nmirror;
check_optimize_mirror("install_readwrite_port", addrstart, addrend, addrmirror, nstart, nend, nmask, nmirror);
@ -1934,7 +1934,7 @@ template<int Width, int AddrShift, endianness_t Endian> void address_space_speci
VPRINTF(("address_space::install_readwrite_bank(%s-%s mirror=%s, read=\"%s\" / write=\"%s\")\n",
core_i64_hex_format(addrstart, m_addrchars), core_i64_hex_format(addrend, m_addrchars),
core_i64_hex_format(addrmirror, m_addrchars),
rtag.empty() ? "(none)" : rtag.c_str(), wtag.empty() ? "(none)" : wtag.c_str()));
rtag.empty() ? "(none)" : rtag.c_str(), wtag.empty() ? "(none)" : wtag.c_str()));
offs_t nstart, nend, nmask, nmirror;
check_optimize_mirror("install_bank_generic", addrstart, addrend, addrmirror, nstart, nend, nmask, nmirror);

12
src/mame/audio/dkong.cpp
View File

@ -1333,8 +1333,8 @@ MACHINE_CONFIG_START(dkong_state::dkong2b_audio)
* P2.Bit2-0 -> select the 256 byte bank for external ROM
*/
LATCH8(config, m_dev_vp2); /* virtual latch for port B */
m_dev_vp2->set_xorvalue(0x20); /* signal is inverted */
LATCH8(config, m_dev_vp2); /* virtual latch for port B */
m_dev_vp2->set_xorvalue(0x20); /* signal is inverted */
m_dev_vp2->read_cb<5>().set(m_dev_6h, FUNC(latch8_device::bit3_r));
m_dev_vp2->write_cb<7>().set("discrete", FUNC(discrete_device::write_line<DS_DISCHARGE_INV>));
@ -1372,8 +1372,8 @@ MACHINE_CONFIG_START(dkong_state::radarscp1_audio)
MCFG_MCS48_PORT_P2_IN_CB(CONSTANT(0))
/* virtual_p2 is not read -see memory map-, all bits are output bits */
latch8_device &vp1(LATCH8(config, "virtual_p1")); /* virtual latch for port A */
vp1.set_xorvalue(0x80); /* signal is inverted */
latch8_device &vp1(LATCH8(config, "virtual_p1")); /* virtual latch for port A */
vp1.set_xorvalue(0x80); /* signal is inverted */
vp1.read_cb<7>().set(m_dev_6h, FUNC(latch8_device::bit3_r));
vp1.read_cb<6>().set("tms", FUNC(m58817_device::status_r));
@ -1405,8 +1405,8 @@ MACHINE_CONFIG_START(dkong_state::dkongjr_audio)
latch8_device &dev_4h(LATCH8(config, "ls259.4h"));
LATCH8(config, m_dev_vp2); /* virtual latch for port B */
m_dev_vp2->set_xorvalue(0x70); /* all signals are inverted */
LATCH8(config, m_dev_vp2); /* virtual latch for port B */
m_dev_vp2->set_xorvalue(0x70); /* all signals are inverted */
m_dev_vp2->read_cb<6>().set(dev_4h, FUNC(latch8_device::bit1_r));
m_dev_vp2->read_cb<5>().set(m_dev_6h, FUNC(latch8_device::bit3_r));
m_dev_vp2->read_cb<4>().set(m_dev_6h, FUNC(latch8_device::bit6_r));

12
src/mame/drivers/akaiax80.cpp
View File

@ -108,12 +108,12 @@ MACHINE_CONFIG_START(ax80_state::ax80)
MCFG_DEVICE_ADD(PPI1_TAG, I8255A, 0)
I8279(config, "kdc", 6554800 / 8); // Keyboard/Display Controller
//kdc.out_irq_calback().set_inputline("maincpu", UPD7810_INTF1); // irq
//kdc.out_sl_callback().set(FUNC(ax80_state::scanlines_w)); // scan SL lines
//kdc.out_disp_callback().set(FUNC(ax80_state::digit_w)); // display A&B
//kdc.in_rl_callback().set(FUNC(ax80_state::kbd_r)) // kbd RL lines
//kdc.in_shift_callback().set_constant(1); // not connected
//kdc.in_ctrl_callback().set_constant(1); // not connected
//kdc.out_irq_calback().set_inputline("maincpu", UPD7810_INTF1); // irq
//kdc.out_sl_callback().set(FUNC(ax80_state::scanlines_w)); // scan SL lines
//kdc.out_disp_callback().set(FUNC(ax80_state::digit_w)); // display A&B
//kdc.in_rl_callback().set(FUNC(ax80_state::kbd_r)) // kbd RL lines
//kdc.in_shift_callback().set_constant(1); // not connected
//kdc.in_ctrl_callback().set_constant(1); // not connected
MACHINE_CONFIG_END
static INPUT_PORTS_START( ax80 )

14
src/mame/drivers/dkmb.cpp
View File

@ -106,7 +106,7 @@ void dkmb_state::main_map(address_map &map)
map(0x020c0000, 0x020c0007).ram(); // write
map(0x020c0010, 0x020c0017).r(FUNC(dkmb_state::unk_20c0010_r)); // read
map(0x04090000, 0x0409ffff).ram(); // size uncertain
map(0x04090000, 0x0409ffff).ram(); // size uncertain
// map(0xff000000, 0xff0fffff) // looks like flash ROM access, mirror of main ROM or just checking if extra exist?
// map(0xff800000, 0xff8fffff) // looks like flash ROM access, mirror of main ROM or just checking if extra exist?
@ -145,12 +145,12 @@ ROM_START( dkmb )
ROM_REGION( 0x1000, "pic", 0 )
/*
Intel HEX format dump. When converted to binary using
"srec_cat.exe 12c508.u12 -intel -o 12c508.bin -binary"
this contains only the string
"Copyright 2001 Core Technologies why are you looking in here?"
in the first 0x80 bytes, which is the unprotected area of the PIC.
the rest is blank, therefore protected and a bad dump
Intel HEX format dump. When converted to binary using
"srec_cat.exe 12c508.u12 -intel -o 12c508.bin -binary"
this contains only the string
"Copyright 2001 Core Technologies why are you looking in here?"
in the first 0x80 bytes, which is the unprotected area of the PIC.
the rest is blank, therefore protected and a bad dump
*/
ROM_LOAD("12c508.u12", 0x000, 0x09db, BAD_DUMP CRC(3adb3e33) SHA1(36a96886d83b64633eea83e57bdfa8a20c6d4f6a) )
ROM_END

4
src/mame/drivers/galaxian.cpp
View File

@ -6468,14 +6468,14 @@ MACHINE_CONFIG_START(galaxian_state::amigo2) // marked "AMI", but similar to abo
MCFG_DEVICE_ADD("audiocpu", Z80, 12_MHz_XTAL / 2 / 2 / 2) /* clock not verified */
MCFG_DEVICE_PROGRAM_MAP(konami_sound_map)
MCFG_DEVICE_IO_MAP(konami_sound_portmap)
MCFG_GENERIC_LATCH_8_ADD("soundlatch")
MCFG_GENERIC_LATCH_8_ADD("soundlatch")
/* sound hardware */
MCFG_DEVICE_ADD("8910.0", AY8910, 12_MHz_XTAL / 2 / 2 / 2) /* matches PCB, needs verification */
MCFG_AY8910_PORT_A_READ_CB(READ8("soundlatch", generic_latch_8_device, read))
MCFG_AY8910_PORT_B_READ_CB(READ8(*this, galaxian_state, konami_sound_timer_r))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.25)
MCFG_DEVICE_ADD("8910.1", AY8910, 12_MHz_XTAL / 2 / 2 / 2) /* matches PCB, needs verification */
MCFG_DEVICE_ADD("8910.1", AY8910, 12_MHz_XTAL / 2 / 2 / 2) /* matches PCB, needs verification */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.25)
MACHINE_CONFIG_END

8
src/mame/drivers/i7000.cpp
View File

@ -381,10 +381,10 @@ MACHINE_CONFIG_START(i7000_state::i7000)
/* Keyboard interface */
i8279_device &kbdc(I8279(config, "i8279", 4000000)); /* guessed value. TODO: verify on PCB */
kbdc.out_sl_callback().set(FUNC(i7000_state::i7000_scanlines_w)); // scan SL lines
kbdc.in_rl_callback().set(FUNC(i7000_state::i7000_kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // TODO: Shift key
kbdc.in_ctrl_callback().set_constant(1); // TODO: Ctrl key
kbdc.out_sl_callback().set(FUNC(i7000_state::i7000_scanlines_w)); // scan SL lines
kbdc.in_rl_callback().set(FUNC(i7000_state::i7000_kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // TODO: Shift key
kbdc.in_ctrl_callback().set_constant(1); // TODO: Ctrl key
/* Cartridge slot */
MCFG_GENERIC_CARTSLOT_ADD("cardslot", generic_romram_plain_slot, "i7000_card")

8
src/mame/drivers/icecold.cpp
View File

@ -386,10 +386,10 @@ MACHINE_CONFIG_START(icecold_state::icecold)
pia2.irqb_handler().set_inputline("maincpu", M6809_IRQ_LINE);
i8279_device &kbdc(I8279(config, "i8279", XTAL(6'000'000)/4));
kbdc.out_irq_callback().set("pia0", FUNC(pia6821_device::cb1_w)); // irq
kbdc.out_sl_callback().set(FUNC(icecold_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(icecold_state::digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(icecold_state::kbd_r)); // kbd RL lines
kbdc.out_irq_callback().set("pia0", FUNC(pia6821_device::cb1_w)); // irq
kbdc.out_sl_callback().set(FUNC(icecold_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(icecold_state::digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(icecold_state::kbd_r)); // kbd RL lines
// 30Hz signal from CH-C of ay0
MCFG_TIMER_DRIVER_ADD_PERIODIC("sint_timer", icecold_state, icecold_sint_timer, attotime::from_hz(30))

10
src/mame/drivers/isbc8010.cpp
View File

@ -225,11 +225,11 @@ MACHINE_CONFIG_START(isbc8010_state::isbc8010)
/* Devices */
// i8279_device &kbdc(I8279(config, "i8279", 3100000)); // based on divider
// kbdc.out_irq_callback().set_inputline("maincpu", I8085_RST55_LINE); // irq
// kbdc.out_sl_callback().set(FUNC(sdk80_state::scanlines_w)); // scan SL lines
// kbdc.out_disp_callback().set(FUNC(sdk80_state::digit_w)); // display A&B
// kbdc.in_rl_callback().set(FUNC(sdk80_state::kbd_r)); // kbd RL lines
// kbdc.in_shift_callback().set_constant(1); // Shift key
// kbdc.out_irq_callback().set_inputline("maincpu", I8085_RST55_LINE); // irq
// kbdc.out_sl_callback().set(FUNC(sdk80_state::scanlines_w)); // scan SL lines
// kbdc.out_disp_callback().set(FUNC(sdk80_state::digit_w)); // display A&B
// kbdc.in_rl_callback().set(FUNC(sdk80_state::kbd_r)); // kbd RL lines
// kbdc.in_shift_callback().set_constant(1); // Shift key
// kbdc.in_ctrl_callback().set_constant(1);
MACHINE_CONFIG_END

74
src/mame/drivers/luckybal.cpp
View File

@ -262,7 +262,7 @@
*********************************************************************/
#define CPU_CLOCK XTAL(12'000'000) // 12MHz. from schematics.
#define CPU_CLOCK XTAL(12'000'000) // 12MHz. from schematics.
#define MCU_CLOCK XTAL(8'000'000)
#define VID_CLOCK XTAL(21'477'272)
@ -341,7 +341,7 @@ private:
void luckybal_state::main_map(address_map &map)
{
map(0x0000, 0xbfff).rom();
map(0xc000, 0xdfff).bankr("bank1"); // Banked ROM.
map(0xc000, 0xdfff).bankr("bank1"); // Banked ROM.
map(0xe000, 0xffff).ram().share("nvram"); // 6264 SRAM
}
@ -434,15 +434,15 @@ READ8_MEMBER(luckybal_state::input_port_c_r)
bit5 = BIT(m_aux->read(), sel_line & 0x07) ? 0xff : 0xdf; // Operator & Page.
bit6 = 0xff;
for (int i = 0; 6 > i; ++i)
{
if (!BIT(mux_player, i) && !BIT(m_keymx[i]->read(), sel_line & 0x07)) // Player buttons.
bit6 &= 0xbf;
}
for (int i = 0; 6 > i; ++i)
{
if (!BIT(mux_player, i) && !BIT(m_keymx[i]->read(), sel_line & 0x07)) // Player buttons.
bit6 &= 0xbf;
}
bit7 = BIT(m_dsw->read(), sel_line & 0x07) ? 0xff : 0x7f; // Dip Switch.
if ((sel_line & 0x07) == 6) m_lamps[37] = (bit5 == 0xff) ? 0 : 1; // Operator lamp.
if ((sel_line & 0x07) == 6) m_lamps[37] = (bit5 == 0xff) ? 0 : 1; // Operator lamp.
ret = bit7 & bit6 & bit5;
return ret;
@ -450,7 +450,7 @@ READ8_MEMBER(luckybal_state::input_port_c_r)
WRITE8_MEMBER(luckybal_state::output_port_c_w)
{
/* Writes 0xF0/0xF1 constantly at the begining... like a watchdog.
/* Writes 0xF0/0xF1 constantly at the begining... like a watchdog.
After a while, just stop (when roulette LEDs are transmitted).
*/
}
@ -468,7 +468,7 @@ static INPUT_PORTS_START( luckybal )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_CODE(KEYCODE_Q) PORT_NAME("Player 1 - Bet")
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_Z) PORT_NAME("Player 1 - Credits OUT")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1) PORT_CODE(KEYCODE_D) PORT_NAME("Player 1 - Right")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1) PORT_CODE(KEYCODE_S) PORT_NAME("Player 1 - Down")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1) PORT_CODE(KEYCODE_S) PORT_NAME("Player 1 - Down")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) // 'Player 1 - Coins' in the schematics. Maybe for another game.
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1) PORT_CODE(KEYCODE_A) PORT_NAME("Player 1 - Left")
@ -478,7 +478,7 @@ static INPUT_PORTS_START( luckybal )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_CODE(KEYCODE_R) PORT_NAME("Player 2 - Bet")
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_X) PORT_NAME("Player 2 - Credits OUT")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) PORT_CODE(KEYCODE_H) PORT_NAME("Player 2 - Right")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_CODE(KEYCODE_G) PORT_NAME("Player 2 - Down")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_CODE(KEYCODE_G) PORT_NAME("Player 2 - Down")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) // 'Player 2 - Coins' in the schematics. Maybe for another game.
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) PORT_CODE(KEYCODE_F) PORT_NAME("Player 2 - Left")
@ -488,7 +488,7 @@ static INPUT_PORTS_START( luckybal )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_CODE(KEYCODE_U) PORT_NAME("Player 3 - Bet")
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_C) PORT_NAME("Player 3 - Credits OUT")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(3) PORT_CODE(KEYCODE_L) PORT_NAME("Player 3 - Right")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(3) PORT_CODE(KEYCODE_K) PORT_NAME("Player 3 - Down")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(3) PORT_CODE(KEYCODE_K) PORT_NAME("Player 3 - Down")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) // 'Player 3 - Coins' in the schematics. Maybe for another game.
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3) PORT_CODE(KEYCODE_J) PORT_NAME("Player 3 - Left")
@ -498,7 +498,7 @@ static INPUT_PORTS_START( luckybal )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_CODE(KEYCODE_LALT) PORT_NAME("Player 4 - Bet")
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_V) PORT_NAME("Player 4 - Credits OUT")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(4) PORT_CODE(KEYCODE_7) PORT_NAME("Player 4 - Right")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(4) PORT_CODE(KEYCODE_PGDN) PORT_NAME("Player 4 - Down")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(4) PORT_CODE(KEYCODE_PGDN) PORT_NAME("Player 4 - Down")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) // 'Player 4 - Coins' in the schematics. Maybe for another game.
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(4) PORT_CODE(KEYCODE_8) PORT_NAME("Player 4 - Left")
@ -508,7 +508,7 @@ static INPUT_PORTS_START( luckybal )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_CODE(KEYCODE_LCONTROL) PORT_NAME("Player 5 - Bet")
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_B) PORT_NAME("Player 5 - Credits OUT")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(5) PORT_CODE(KEYCODE_LEFT) PORT_NAME("Player 5 - Right")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(5) PORT_CODE(KEYCODE_UP) PORT_NAME("Player 5 - Down")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(5) PORT_CODE(KEYCODE_UP) PORT_NAME("Player 5 - Down")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) // 'Player 5 - Coins' in the schematics. Maybe for another game.
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(5) PORT_CODE(KEYCODE_RIGHT) PORT_NAME("Player 5 - Left")
@ -518,7 +518,7 @@ static INPUT_PORTS_START( luckybal )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("Player 6 - Bet")
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_CODE(KEYCODE_N) PORT_NAME("Player 6 - Credits OUT")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(6) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("Player 6 - Right")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(6) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("Player 6 - Down")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(6) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("Player 6 - Down")
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) // 'Player 6 - Coins' in the schematics. Maybe for another game.
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(6) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("Player 6 - Left")
@ -673,17 +673,17 @@ void luckybal_state::init_luckybala()
}
/* The following patches are to avoid hardware verifications through
the unemulated synchronic serial comm of the z180...
*/
rom[0x571] = 0x68; //31
rom[0x572] = 0xE8; //4C
rom[0x573] = 0x18; //42
rom[0x574] = 0x98; //39
rom[0x575] = 0x58; //36
rom[0x16E1] = 0x0D; //OC
rom[0x1D65] = 0x0E; //0C
rom[0x4499] = 0x00; //FF <------- Checksum.
rom[0x4AB6] = 0xAF; //B9
the unemulated synchronic serial comm of the z180...
*/
rom[0x571] = 0x68; //31
rom[0x572] = 0xE8; //4C
rom[0x573] = 0x18; //42
rom[0x574] = 0x98; //39
rom[0x575] = 0x58; //36
rom[0x16E1] = 0x0D; //OC
rom[0x1D65] = 0x0E; //0C
rom[0x4499] = 0x00; //FF <------- Checksum.
rom[0x4AB6] = 0xAF; //B9
membank("bank1")->configure_entries(0, 0x40, &rom[0x10000], 0x2000);
}
@ -700,17 +700,17 @@ void luckybal_state::init_luckybald()
}
/* The following patches are to avoid hardware verifications through
the unemulated synchronic serial comm of the z180...
*/
rom[0x571] = 0x68; //31
rom[0x572] = 0xE8; //4C
rom[0x573] = 0x18; //42
rom[0x574] = 0x98; //39
rom[0x575] = 0x58; //36
rom[0x16C1] = 0x0D; //OC
rom[0x1D45] = 0x0E; //0C
rom[0x44A9] = 0x00; //FF <------- Checksum.
rom[0x4AC6] = 0xAF; //B9
the unemulated synchronic serial comm of the z180...
*/
rom[0x571] = 0x68; //31
rom[0x572] = 0xE8; //4C
rom[0x573] = 0x18; //42
rom[0x574] = 0x98; //39
rom[0x575] = 0x58; //36
rom[0x16C1] = 0x0D; //OC
rom[0x1D45] = 0x0E; //0C
rom[0x44A9] = 0x00; //FF <------- Checksum.
rom[0x4AC6] = 0xAF; //B9
membank("bank1")->configure_entries(0, 0x40, &rom[0x10000], 0x2000);
}

6
src/mame/drivers/marywu.cpp
View File

@ -194,9 +194,9 @@ MACHINE_CONFIG_START(marywu_state::marywu)
//TODO: figure out what each bit is mapped to in the 80c31 ports P1 and P3
/* Keyboard & display interface */
i8279_device &kbdc(I8279(config, "i8279", XTAL(10'738'635))); // should it be perhaps a fraction of the XTAL clock ?
kbdc.out_sl_callback().set(FUNC(marywu_state::multiplex_7seg_w)); // select block of 7seg modules by multiplexing the SL scan lines
kbdc.in_rl_callback().set(FUNC(marywu_state::keyboard_r)); // keyboard Return Lines
i8279_device &kbdc(I8279(config, "i8279", XTAL(10'738'635))); // should it be perhaps a fraction of the XTAL clock ?
kbdc.out_sl_callback().set(FUNC(marywu_state::multiplex_7seg_w)); // select block of 7seg modules by multiplexing the SL scan lines
kbdc.in_rl_callback().set(FUNC(marywu_state::keyboard_r)); // keyboard Return Lines
kbdc.out_disp_callback().set(FUNC(marywu_state::display_7seg_data_w));
/* Video */

14
src/mame/drivers/maygay1b.cpp
View File

@ -811,16 +811,16 @@ MACHINE_CONFIG_START(maygay1b_state::maygay_m1)
MCFG_TIMER_DRIVER_ADD_PERIODIC("nmitimer", maygay1b_state, maygay1b_nmitimer_callback, attotime::from_hz(75)) // freq?
i8279_device &kbdc(I8279(config, "i8279", M1_MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(maygay1b_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(maygay1b_state::lamp_data_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(maygay1b_state::kbd_r)); // kbd RL lines
i8279_device &kbdc(I8279(config, "i8279", M1_MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(maygay1b_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(maygay1b_state::lamp_data_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(maygay1b_state::kbd_r)); // kbd RL lines
#ifndef USE_MCU
// on M1B there is a 2nd i8279, on M1 / M1A a 8051 handles this task!
i8279_device &kbdc2(I8279(config, "i8279_2", M1_MASTER_CLOCK/4)); // unknown clock
kbdc2.out_sl_callback().set(FUNC(maygay1b_state::scanlines_2_w)); // scan SL lines
kbdc2.out_disp_callback().set(FUNC(maygay1b_state::lamp_data_2_w)); // display A&B
i8279_device &kbdc2(I8279(config, "i8279_2", M1_MASTER_CLOCK/4)); // unknown clock
kbdc2.out_sl_callback().set(FUNC(maygay1b_state::scanlines_2_w)); // scan SL lines
kbdc2.out_disp_callback().set(FUNC(maygay1b_state::lamp_data_2_w)); // display A&B
#endif
MCFG_DEVICE_ADD("reel0", REEL, STARPOINT_48STEP_REEL, 1, 3, 0x09, 4)

8
src/mame/drivers/maygayv1.cpp
View File

@ -914,10 +914,10 @@ MACHINE_CONFIG_START(maygayv1_state::maygayv1)
MCFG_MC68681_IRQ_CALLBACK(WRITELINE(*this, maygayv1_state, duart_irq_handler))
MCFG_MC68681_A_TX_CALLBACK(WRITELINE(*this, maygayv1_state, duart_txa))
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(maygayv1_state::strobe_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(maygayv1_state::lamp_data_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(maygayv1_state::kbd_r)); // kbd RL lines
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(maygayv1_state::strobe_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(maygayv1_state::lamp_data_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(maygayv1_state::kbd_r)); // kbd RL lines
SPEAKER(config, "mono").front_center();

10
src/mame/drivers/mmd1.cpp
View File

@ -519,11 +519,11 @@ MACHINE_CONFIG_START(mmd1_state::mmd2)
config.set_default_layout(layout_mmd2);
/* Devices */
i8279_device &kbdc(I8279(config, "i8279", 400000)); // based on divider
kbdc.out_sl_callback().set(FUNC(mmd1_state::mmd2_scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(mmd1_state::mmd2_digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(mmd1_state::mmd2_kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // Shift key
i8279_device &kbdc(I8279(config, "i8279", 400000)); // based on divider
kbdc.out_sl_callback().set(FUNC(mmd1_state::mmd2_scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(mmd1_state::mmd2_digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(mmd1_state::mmd2_kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // Shift key
kbdc.in_ctrl_callback().set_constant(1);
MACHINE_CONFIG_END

2
src/mame/drivers/namcos2.cpp
View File

@ -457,7 +457,7 @@ Custom Chips: Final Lap Assault LuckyWld System21
C45 Land Generator * *
C65 I/O Controller (older) * *
C67 TMS320C25 (DSP int rom)
C68 I/O Controller (newer) * *
C68 I/O Controller (newer) * *
C70 *
C95 * *
C102 ROZ:Memory Access Control *

2
src/mame/drivers/namcos21.cpp
View File

@ -41,7 +41,7 @@ Winning Run
posirq effects for bitmap layer not working
NOTES:
NOTES:
Winning Run
Winning Run 91

78
src/mame/drivers/namcos21_c67.cpp
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Phil Stroffolino
/*
NOTES:
NOTES:
Air Combat:
priority issues
@ -17,44 +17,44 @@ TODO: Map lamps/vibration outputs as used by StarBlade (and possibly other tit
DSP RAM is shared with the 68000 CPUs and master DSP.
The memory map below reflects DSP RAM as seen by the 68000 CPUs.
0x200000: ROM:
0x200010: RAM:
0x200020: PTR:
0x200024: <checksum>
0x200028: <checksum>
0x200030: SMU: // "NO RESPONS" (DSP)
0x200040: IDC: // "NO RESPONS" (DSP)
0x200050: CPU: BOOTING..COMPLETE
0x200060: DSP:
0x200070: CRC: OK from cpu
0x200080: CRC: from dsp
0x200090: ID:
0x2000a0: B-M:
0x2000b0: P-M:
0x2000c0: S-M:
0x200100 status: 2=upload needed, 4=error (abort)
0x200102 status
0x200104 0x0002
0x200106 addr written by main cpu
0x20010a point rom checksum (starblade expects 0xed53)
0x20010c point rom checksum (starblade expects 0xd5df)
0x20010e 1 : upload-code-to-dsp request trigger
0x200110 status
0x200112 status
0x200114 master dsp code size
0x200116 slave dsp code size
0x200120 upload source1 addr hi
0x200122 upload source1 addr lo
0x200124 upload source2 addr hi
0x200126 upload source2 addr lo
0x200200 enable
0x200202 status
0x200206 work page select
0x200208 0xa2c2 (air combat)
0x208000..0x2080ff camera attributes for page#0
0x208200..0x208fff 3d object attribute display list for page#0
0x20c000..0x20c0ff camera attributes for page#1
0x20c200..0x20cfff 3d object attribute display list for page#1
0x200000: ROM:
0x200010: RAM:
0x200020: PTR:
0x200024: <checksum>
0x200028: <checksum>
0x200030: SMU: // "NO RESPONS" (DSP)
0x200040: IDC: // "NO RESPONS" (DSP)
0x200050: CPU: BOOTING..COMPLETE
0x200060: DSP:
0x200070: CRC: OK from cpu
0x200080: CRC: from dsp
0x200090: ID:
0x2000a0: B-M:
0x2000b0: P-M:
0x2000c0: S-M:
0x200100 status: 2=upload needed, 4=error (abort)
0x200102 status
0x200104 0x0002
0x200106 addr written by main cpu
0x20010a point rom checksum (starblade expects 0xed53)
0x20010c point rom checksum (starblade expects 0xd5df)
0x20010e 1 : upload-code-to-dsp request trigger
0x200110 status
0x200112 status
0x200114 master dsp code size
0x200116 slave dsp code size
0x200120 upload source1 addr hi
0x200122 upload source1 addr lo
0x200124 upload source2 addr hi
0x200126 upload source2 addr lo
0x200200 enable
0x200202 status
0x200206 work page select
0x200208 0xa2c2 (air combat)
0x208000..0x2080ff camera attributes for page#0
0x208200..0x208fff 3d object attribute display list for page#0
0x20c000..0x20c0ff camera attributes for page#1
0x20c200..0x20cfff 3d object attribute display list for page#1
Starblade Cybersled AirCombat22 Solvalou
[400]:= 00 0000 00 0000 00 0000 00 0000

20
src/mame/drivers/namcos21_de.cpp
View File

@ -11,16 +11,16 @@ Driver's Eyes works,
-The left, center and right screens have separate programs and boards, each would work independently.
About projection angles of left and right screen, the angle is correct on "DRIVER'S EYES" title screen, however in the tracks of demo mode it doesn't seem correct.
(probably wants angle sent by main board?)
(probably wants angle sent by main board?)
-On demo screen, should fog effects be turned off?
NOTES:
NOTES:
Driver's Eyes
not yet working
Driver's Eyes
not yet working
TODO:
TODO:
Driver's Eyes
add communications for Left and Right screen (linked C139 or something else?)
@ -710,12 +710,12 @@ static INPUT_PORTS_START( driveyes )
INPUT_PORTS_END
/*
Note, only the main screen PCB stack has voice roms populated
the sound program also differs on the side screen sets
Note, only the main screen PCB stack has voice roms populated
the sound program also differs on the side screen sets
pcb_0 = left
pcb_1 = center
pcb_2 = right
pcb_0 = left
pcb_1 = center
pcb_2 = right
*/
ROM_START( driveyes )

4
src/mame/drivers/nforcepc.cpp
View File

@ -9,7 +9,7 @@
- nForce 415-D northbridge
- nForce MCP-D southbridge (with integrated APU)
- ITE IT8703F-A SuperIO
- Asus AS99127F chip
- Asus AS99127F chip
- An AMD Athlon XP processor
- An IDE hard disk
- A floppy disk drive
@ -173,7 +173,7 @@ MACHINE_CONFIG_START(nforcepc_state::nforcepc)
MCFG_DEVICE_IO_MAP(nforce_map_io)
MCFG_DEVICE_ADD(":pci", PCI_ROOT, 0)
MCFG_DEVICE_ADD(":pci:00.0", CRUSH11, 0, "maincpu", 2 * 1024 * 1024)
/* MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pci:07.0:pic8259_master", pic8259_device, inta_cb)
/* MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pci:07.0:pic8259_master", pic8259_device, inta_cb)
MCFG_I386_SMIACT(WRITELINE("pci:00.0", i82439hx_host_device, smi_act_w))
i82371sb_isa_device &isa(I82371SB_ISA(config, ":pci:07.0", 0));

8
src/mame/drivers/peyper.cpp
View File

@ -626,10 +626,10 @@ MACHINE_CONFIG_START(peyper_state::peyper)
/* Devices */
i8279_device &kbdc(I8279(config, "i8279", 2500000));
kbdc.out_sl_callback().set(FUNC(peyper_state::col_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(peyper_state::disp_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(peyper_state::sw_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // Shift key
kbdc.out_sl_callback().set(FUNC(peyper_state::col_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(peyper_state::disp_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(peyper_state::sw_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // Shift key
kbdc.in_ctrl_callback().set_constant(1);
MACHINE_CONFIG_END

2
src/mame/drivers/route16.cpp
View File

@ -1043,7 +1043,7 @@ ROM_START( jongpute )
ROM_REGION( 0x10000, "cpu2", 0 )
ROM_LOAD( "j6", 0x0000, 0x1000, CRC(54b349b0) SHA1(e5620b85a24a35d995860c7121f1ddf16f7ea168) )
/* maybe used for pseudo sampling voice, "reach", that is not emulated yet */
/* maybe used for pseudo sampling voice, "reach", that is not emulated yet */
ROM_REGION( 0x1000, "unknown", 0 )
ROM_LOAD( "j1", 0x0000, 0x1000, CRC(6d6ba272) SHA1(a4efd8daddbbf595ee46484578f544d7ed84e090) )

12
src/mame/drivers/sdk85.cpp
View File

@ -167,12 +167,12 @@ MACHINE_CONFIG_START(sdk85_state::sdk85)
config.set_default_layout(layout_sdk85);
/* Devices */
i8279_device &kdc(I8279(config, "kdc", 6.144_MHz_XTAL / 2)); // Keyboard/Display Controller (A13)
kdc.out_irq_callback().set_inputline("maincpu", I8085_RST55_LINE); // irq
kdc.out_sl_callback().set(FUNC(sdk85_state::scanlines_w)); // scan SL lines
kdc.out_disp_callback().set(FUNC(sdk85_state::digit_w)); // display A&B
kdc.in_rl_callback().set(FUNC(sdk85_state::kbd_r)); // kbd RL lines
kdc.in_shift_callback().set_constant(1); // Shift key
i8279_device &kdc(I8279(config, "kdc", 6.144_MHz_XTAL / 2)); // Keyboard/Display Controller (A13)
kdc.out_irq_callback().set_inputline("maincpu", I8085_RST55_LINE); // irq
kdc.out_sl_callback().set(FUNC(sdk85_state::scanlines_w)); // scan SL lines
kdc.out_disp_callback().set(FUNC(sdk85_state::digit_w)); // display A&B
kdc.in_rl_callback().set(FUNC(sdk85_state::kbd_r)); // kbd RL lines
kdc.in_shift_callback().set_constant(1); // Shift key
kdc.in_ctrl_callback().set_constant(1);
MACHINE_CONFIG_END

10
src/mame/drivers/sdk86.cpp
View File

@ -169,11 +169,11 @@ MACHINE_CONFIG_START(sdk86_state::sdk86)
usart_clock.signal_handler().set(I8251_TAG, FUNC(i8251_device::write_txc));
usart_clock.signal_handler().append(I8251_TAG, FUNC(i8251_device::write_rxc));
i8279_device &kbdc(I8279(config, "i8279", 2500000)); // based on divider
kbdc.out_sl_callback().set(FUNC(sdk86_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(sdk86_state::digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(sdk86_state::kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(0); // Shift key
i8279_device &kbdc(I8279(config, "i8279", 2500000)); // based on divider
kbdc.out_sl_callback().set(FUNC(sdk86_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(sdk86_state::digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(sdk86_state::kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(0); // Shift key
kbdc.in_ctrl_callback().set_constant(0);
MCFG_DEVICE_ADD("port1", I8255A, 0)

2
src/mame/drivers/segae.cpp
View File

@ -363,7 +363,7 @@ private:
required_device<cpu_device> m_maincpu;
required_device<sega315_5124_device> m_vdp1;
required_device<sega315_5124_device> m_vdp2;
required_device<i8255_device> m_ppi;
required_device<i8255_device> m_ppi;
optional_shared_ptr<uint8_t> m_decrypted_opcodes;
required_memory_region m_maincpu_region;

8
src/mame/drivers/selz80.cpp
View File

@ -242,10 +242,10 @@ MACHINE_CONFIG_START(selz80_state::selz80)
MCFG_RS232_CTS_HANDLER(WRITELINE("uart", i8251_device, write_cts))
i8279_device &kbdc(I8279(config, "i8279", 5000000 / 2)); // based on divider
kbdc.out_sl_callback().set(FUNC(selz80_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(selz80_state::digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(selz80_state::kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // Shift key
kbdc.out_sl_callback().set(FUNC(selz80_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(selz80_state::digit_w)); // display A&B
kbdc.in_rl_callback().set(FUNC(selz80_state::kbd_r)); // kbd RL lines
kbdc.in_shift_callback().set_constant(1); // Shift key
kbdc.in_ctrl_callback().set_constant(1);
MACHINE_CONFIG_END

12
src/mame/drivers/sun4.cpp
View File

@ -476,12 +476,12 @@
#define DMA_BYTE_COUNT (2)
#define DMA_XTAL (25_MHz_XTAL)
#define AUXIO_DENSITY (0x20)
#define AUXIO_DISK_CHG (0x10)
#define AUXIO_DRIVE_SEL (0x08)
#define AUXIO_TC (0x04)
#define AUXIO_EJECT (0x02)
#define AUXIO_LED (0x01)
#define AUXIO_DENSITY (0x20)
#define AUXIO_DISK_CHG (0x10)
#define AUXIO_DRIVE_SEL (0x08)
#define AUXIO_TC (0x04)
#define AUXIO_EJECT (0x02)
#define AUXIO_LED (0x01)
namespace
{

24
src/mame/drivers/turbo.cpp
View File

@ -870,10 +870,10 @@ MACHINE_CONFIG_START(turbo_state::turbo)
m_i8255_3->in_pb_callback().set_ioport("DSW2");
m_i8255_3->out_pc_callback().set(FUNC(turbo_state::turbo_ppi3c_w));
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(turbo_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(turbo_state::digit_w)); // display A&B
kbdc.in_rl_callback().set_ioport("DSW1"); // kbd RL lines
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(turbo_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(turbo_state::digit_w)); // display A&B
kbdc.in_rl_callback().set_ioport("DSW1"); // kbd RL lines
ls259_device &outlatch(LS259(config, "outlatch")); // IC125 - outputs passed through CN5
outlatch.q_out_cb<0>().set(FUNC(turbo_state::coin_meter_1_w));
@ -915,10 +915,10 @@ MACHINE_CONFIG_START(turbo_state::subroc3d)
m_i8255_1->out_pb_callback().set(FUNC(turbo_state::subroc3d_sound_b_w));
m_i8255_1->out_pc_callback().set(FUNC(turbo_state::subroc3d_sound_c_w));
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(turbo_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(turbo_state::digit_w)); // display A&B
kbdc.in_rl_callback().set_ioport("DSW1"); // kbd RL lines
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(turbo_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(turbo_state::digit_w)); // display A&B
kbdc.in_rl_callback().set_ioport("DSW1"); // kbd RL lines
/* video hardware */
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_turbo)
@ -963,10 +963,10 @@ MACHINE_CONFIG_START(turbo_state::buckrog)
m_i8255_1->out_pb_callback().set(FUNC(turbo_state::buckrog_sound_b_w));
m_i8255_1->out_pc_callback().set(FUNC(turbo_state::buckrog_ppi1c_w));
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(turbo_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(turbo_state::digit_w)); // display A&B
kbdc.in_rl_callback().set_ioport("DSW1"); // kbd RL lines
i8279_device &kbdc(I8279(config, "i8279", MASTER_CLOCK/4)); // unknown clock
kbdc.out_sl_callback().set(FUNC(turbo_state::scanlines_w)); // scan SL lines
kbdc.out_disp_callback().set(FUNC(turbo_state::digit_w)); // display A&B
kbdc.in_rl_callback().set_ioport("DSW1"); // kbd RL lines
/* video hardware */
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_turbo)

4
src/mame/drivers/vgmplay.cpp
View File

@ -1526,8 +1526,8 @@ void vgmplay_device::execute_run()
}
//else if ((offset & 0x7f) == 0x15 && m_nes_apu_channel_hack[chip] == -2 && (m_file->read_byte(m_pc + 2) & 0x1f) != 0)
//{
// osd_printf_error("bad rip false positive, late enabling nesapu.%d channels %x/%x\n", chip, m_pc, m_io->read_dword(REG_SIZE));
// m_nes_apu_channel_hack[chip] = -1;
// osd_printf_error("bad rip false positive, late enabling nesapu.%d channels %x/%x\n", chip, m_pc, m_io->read_dword(REG_SIZE));
// m_nes_apu_channel_hack[chip] = -1;
//}
if (offset & 0x80)

2
src/mame/drivers/x68k.cpp
View File

@ -1695,7 +1695,7 @@ void x68ksupr_state::x68ksupr(machine_config &config)
void x68ksupr_state::x68kxvi(machine_config &config)
{
add_cpu(config, M68000, &x68ksupr_state::x68kxvi_map, 33.333_MHz_XTAL / 2); /* 16 MHz (nominally) */
add_cpu(config, M68000, &x68ksupr_state::x68kxvi_map, 33.333_MHz_XTAL / 2); /* 16 MHz (nominally) */
x68ksupr_base(config);
}

2
src/mame/includes/namcofl.h
View File

@ -58,7 +58,7 @@ private:
required_device<namco_c123tmap_device> m_c123tmap;
required_device<namco_c169roz_device> m_c169roz;
required_device<namco_c355spr_device> m_c355spr;
required_device<cpu_device> m_mcu;
required_device<cpu_device> m_mcu;
required_ioport m_in0;
required_ioport m_in1;
required_ioport m_in2;

2
src/mame/includes/namconb1.h
View File

@ -102,7 +102,7 @@ private:
required_device<namco_c355spr_device> m_c355spr;
optional_device<namco_c169roz_device> m_c169roz; // NB1 only, not NA1
required_device<screen_device> m_screen;
required_device<cpu_device> m_mcu;
required_device<cpu_device> m_mcu;
required_device<eeprom_parallel_28xx_device> m_eeprom;
required_ioport m_p1;
required_ioport m_p2;

2
src/mame/machine/namco_c139.cpp
View File

@ -8,7 +8,7 @@
TODO:
- Make this to actually work!
- Is RAM shared with a specific CPU other than master/slave?
- is this another MCU with internal ROM?
- is this another MCU with internal ROM?
***************************************************************************/

2
src/mame/machine/namcos21_dsp_c67.cpp
View File

@ -9,7 +9,7 @@ used by Star Blade, Cybersled
TODO: handle protection properly and with callbacks
handle splitting of workload across slaves
remove hacks!
remove hacks!
some of the list processing should probably be in the 3d device, split it out
*/

2
src/mame/machine/namcos21_dsp_c67.h
View File

@ -16,7 +16,7 @@ class namcos21_dsp_c67_device : public device_t
{
public:
enum
{ /* Namco System21 */
{ /* Namco System21 */
NAMCOS21_AIRCOMBAT = 0x4000,
NAMCOS21_STARBLADE,
NAMCOS21_CYBERSLED,

2
src/mame/video/galaxian.cpp
View File

@ -1064,7 +1064,7 @@ void galaxian_state::sfx_draw_background(bitmap_rgb32 &bitmap, const rectangle &
{
/* current schematics are unreadable, assuming like Turtles */
bitmap.fill(rgb_t(m_background_red * 0x55, m_background_green * 0x47, m_background_blue * 0x55), cliprect);
scramble_draw_stars(bitmap, cliprect, 256);
scramble_draw_stars(bitmap, cliprect, 256);
}

16
src/mame/video/namco_c123tmap.cpp
View File

@ -2,16 +2,16 @@
// copyright-holders:David Haywood, Phil Stroffolino
/*
C123 Tilemaps
used by
namcos2.cpp (all games)
namcofl.cpp (all games)
namconb1.cpp (all games)
C123 Tilemaps
used by
namcos2.cpp (all games)
namcofl.cpp (all games)
namconb1.cpp (all games)
should be used by
namcos1.cpp (all games)
should be used by
namcos1.cpp (all games)
(TODO: merge with namcos1.cpp implementation)
(TODO: merge with namcos1.cpp implementation)
*/
#include "emu.h"

14
src/mame/video/namco_c355spr.cpp
View File

@ -2,13 +2,13 @@
// copyright-holders:David Haywood, Phil Stroffolino
/*
C355 Zooming sprites
used by
namcofl.cpp (all games)
namconb1.cpp (all games)
gal3.cpp (all games)
namcos21.cpp (Driver's Eyes, Solvalou, Starblade, Air Combat, Cyber Sled) (everything except Winning Run series)
namcos2.cpp (Steel Gunner, Steel Gunner 2, Lucky & Wild, Suzuka 8 Hours, Suzuka 8 Hours 2)
C355 Zooming sprites
used by
namcofl.cpp (all games)
namconb1.cpp (all games)
gal3.cpp (all games)
namcos21.cpp (Driver's Eyes, Solvalou, Starblade, Air Combat, Cyber Sled) (everything except Winning Run series)
namcos2.cpp (Steel Gunner, Steel Gunner 2, Lucky & Wild, Suzuka 8 Hours, Suzuka 8 Hours 2)
*/

8
src/mame/video/namcos21_3d.cpp
View File

@ -258,10 +258,10 @@ void namcos21_3d_device::draw_quad(int sx[4], int sy[4], int zcode[4], int color
n21_vertex a, b, c, d;
int depthcueenable = 1;
/*
0x0000..0x1fff sprite palettes (0x20 sets of 0x100 colors)
0x2000..0x3fff polygon palette bank0 (0x10 sets of 0x200 colors or 0x20 sets of 0x100 colors)
0x4000..0x5fff polygon palette bank1 (0x10 sets of 0x200 colors or 0x20 sets of 0x100 colors)
0x6000..0x7fff polygon palette bank2 (0x10 sets of 0x200 colors or 0x20 sets of 0x100 colors)
0x0000..0x1fff sprite palettes (0x20 sets of 0x100 colors)
0x2000..0x3fff polygon palette bank0 (0x10 sets of 0x200 colors or 0x20 sets of 0x100 colors)
0x4000..0x5fff polygon palette bank1 (0x10 sets of 0x200 colors or 0x20 sets of 0x100 colors)
0x6000..0x7fff polygon palette bank2 (0x10 sets of 0x200 colors or 0x20 sets of 0x100 colors)
*/

56
src/mame/video/namcos2_roz.cpp
View File

@ -2,14 +2,14 @@
// copyright-holders:David Haywood, Phil Stroffolino
/*
Namco System 2 ROZ Tilemap - found on Namco System 2 video board (standard type)
Namco System 2 ROZ Tilemap - found on Namco System 2 video board (standard type)
based on namcoic.txt this probably consists of the following
C102 - Controls CPU access to ROZ Memory Area.
(anything else?)
based on namcoic.txt this probably consists of the following
C102 - Controls CPU access to ROZ Memory Area.
(anything else?)
used by the following drivers
namcos2.cpp (all games EXCEPT Final Lap 1,2,3 , Lucky & Wild , Steel Gunner 1,2 , Suzuka 8 Hours 1,2 , Metal Hawk)
used by the following drivers
namcos2.cpp (all games EXCEPT Final Lap 1,2,3 , Lucky & Wild , Steel Gunner 1,2 , Suzuka 8 Hours 1,2 , Metal Hawk)
*/
@ -113,30 +113,30 @@ draw_roz_helper(
if (bitmap.bpp() == 16)
{
/* On many processors, the simple approach of an outer loop over the
rows of the destination bitmap with an inner loop over the columns
of the destination bitmap has poor performance due to the order
that memory in the source bitmap is referenced when rotation
approaches 90 or 270 degrees. The reason is that the inner loop
ends up reading pixels not sequentially in the source bitmap, but
instead at rozInfo->incxx increments, which is at its maximum at 90
degrees of rotation. This means that only a few (or as few as
one) source pixels are in each cache line at a time.
rows of the destination bitmap with an inner loop over the columns
of the destination bitmap has poor performance due to the order
that memory in the source bitmap is referenced when rotation
approaches 90 or 270 degrees. The reason is that the inner loop
ends up reading pixels not sequentially in the source bitmap, but
instead at rozInfo->incxx increments, which is at its maximum at 90
degrees of rotation. This means that only a few (or as few as
one) source pixels are in each cache line at a time.
Instead of the above, this code iterates in NxN blocks through the
destination bitmap. This has more overhead when there is little or
no rotation, but much better performance when there is closer to 90
degrees of rotation (as long as the chunk of the source bitmap that
corresponds to an NxN destination block fits in cache!).
Instead of the above, this code iterates in NxN blocks through the
destination bitmap. This has more overhead when there is little or
no rotation, but much better performance when there is closer to 90
degrees of rotation (as long as the chunk of the source bitmap that
corresponds to an NxN destination block fits in cache!).
N is defined by ROZ_BLOCK_SIZE below; the best N is one that is as
big as possible but at the same time not too big to prevent all of
the source bitmap pixels from fitting into cache at the same time.
Keep in mind that the block of source pixels used can be somewhat
scattered in memory. 8x8 works well on the few processors that
were tested; 16x16 seems to work even better for more modern
processors with larger caches, but since 8x8 works well enough and
is less likely to result in cache misses on processors with smaller
caches, it is used.
N is defined by ROZ_BLOCK_SIZE below; the best N is one that is as
big as possible but at the same time not too big to prevent all of
the source bitmap pixels from fitting into cache at the same time.
Keep in mind that the block of source pixels used can be somewhat
scattered in memory. 8x8 works well on the few processors that
were tested; 16x16 seems to work even better for more modern
processors with larger caches, but since 8x8 works well enough and
is less likely to result in cache misses on processors with smaller
caches, it is used.
*/
#define ROZ_BLOCK_SIZE 8

68
src/mame/video/namcos2_sprite.cpp
View File

@ -2,18 +2,18 @@
// copyright-holders:David Haywood, Phil Stroffolino
/*
Namco System 2 Sprites - found on Namco System 2 video board (standard type)
Namco System 2 Sprites - found on Namco System 2 video board (standard type)
based on namcoic.txt this probably consists of the following
C106 - Generates memory output clocks to generate X-Axis Zoom for Line Buffer Writes
C134 - Object Memory Address Generator. Sequences the sprite memory contents to the hardware.
C135 - Checks is object is displayed on Current output line.
C146 - Steers the Decode Object Pixel data to the correct line buffer A or B
based on namcoic.txt this probably consists of the following
C106 - Generates memory output clocks to generate X-Axis Zoom for Line Buffer Writes
C134 - Object Memory Address Generator. Sequences the sprite memory contents to the hardware.
C135 - Checks is object is displayed on Current output line.
C146 - Steers the Decode Object Pixel data to the correct line buffer A or B
Metal Hawk requires a different draw function, so might use a different chip unless the hookup is just scrambled (needs checking)
Metal Hawk requires a different draw function, so might use a different chip unless the hookup is just scrambled (needs checking)
used by the following drivers
namcos2.cpp (all games EXCEPT Steel Gunner, Steel Gunner 2, Lucky & Wild, Suzuka 8 Hours, Suzuka 8 Hours 2 which use the newer Namco NB1 style sprites, see namco_c355spr.cpp)
used by the following drivers
namcos2.cpp (all games EXCEPT Steel Gunner, Steel Gunner 2, Lucky & Wild, Suzuka 8 Hours, Suzuka 8 Hours 2 which use the newer Namco NB1 style sprites, see namco_c355spr.cpp)
*/
@ -125,31 +125,31 @@ void namcos2_sprite_device::zdrawgfxzoom(
/* this code was previously shared with the c355 where this was needed
if( m_palxor )
{
for( x=sx; x<ex; x++ )
{
int c = source[x_index>>16];
if( c != 0xff )
{
if( pri[x]<=zpos )
{
switch( c )
{
case 0:
dest[x] = 0x4000|(dest[x]&0x1fff);
break;
case 1:
dest[x] = 0x6000|(dest[x]&0x1fff);
break;
default:
dest[x] = pal[c];
break;
}
pri[x] = zpos;
}
}
x_index += dx;
}
y_index += dy;
for( x=sx; x<ex; x++ )
{
int c = source[x_index>>16];
if( c != 0xff )
{
if( pri[x]<=zpos )
{
switch( c )
{
case 0:
dest[x] = 0x4000|(dest[x]&0x1fff);
break;
case 1:
dest[x] = 0x6000|(dest[x]&0x1fff);
break;
default:
dest[x] = pal[c];
break;
}
pri[x] = zpos;
}
}
x_index += dx;
}
y_index += dy;
}
else
*/

4
src/mame/video/powervr2.cpp
View File

@ -1804,8 +1804,8 @@ void powervr2_device::process_ta_fifo()
if (paratype == 7)
{
if ((global_paratype == 5) ||
(tafifo_listtype == DISPLAY_LIST_OPAQUE_MOD) ||
(tafifo_listtype == DISPLAY_LIST_TRANS_MOD))
(tafifo_listtype == DISPLAY_LIST_OPAQUE_MOD) ||
(tafifo_listtype == DISPLAY_LIST_TRANS_MOD))
{
tafifo_vertexwords = 16;
}

2
src/osd/modules/render/d3d/d3dhlsl.cpp
View File

@ -826,7 +826,7 @@ int shaders::create_resources()
phosphor_effect->add_uniform("Phosphor", uniform::UT_VEC3, uniform::CU_PHOSPHOR_LIFE);
post_effect->add_uniform("ShadowAlpha", uniform::UT_FLOAT, uniform::CU_POST_SHADOW_ALPHA);
post_effect->add_uniform("ShadowAlpha", uniform::UT_FLOAT, uniform::CU_POST_SHADOW_ALPHA);
post_effect->add_uniform("ShadowCount", uniform::UT_VEC2, uniform::CU_POST_SHADOW_COUNT);
post_effect->add_uniform("ShadowUV", uniform::UT_VEC2, uniform::CU_POST_SHADOW_UV);
post_effect->add_uniform("ShadowUVOffset", uniform::UT_VEC2, uniform::CU_POST_SHADOW_UV_OFFSET);