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https://github.com/holub/mame
synced 2025-05-22 13:48:55 +03:00
Cleanups and version bump.
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49bc4d3ac2
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@ -8,22 +8,22 @@ TO DO:
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- sound
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- sound
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- input
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- input
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Has 36 pin Cherry master looking edge connector
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Has 36 pin Cherry master looking edge connector
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.u12 2764 stickered 1
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.u12 2764 stickered 1
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.u19 27256 stickered 2
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.u19 27256 stickered 2
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.u15 tibpal16l8-25 (checksum was 0)
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.u15 tibpal16l8-25 (checksum was 0)
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.u56 tibpal16l8-25 (checksum was 0)
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.u56 tibpal16l8-25 (checksum was 0)
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.u38 82s123
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.u38 82s123
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.u53 82s123
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.u53 82s123
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Z80 x2
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Z80 x2
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Altera Ep1810LC-45
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Altera Ep1810LC-45
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20.000 MHz crystal
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20.000 MHz crystal
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video 464p10 x4 (board silcksreeend 4416)
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video 464p10 x4 (board silcksreeend 4416)
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AY-3-8912A
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AY-3-8912A
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ROM text showed SUPER LUCKY ROULETTE LEISURE ENT
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ROM text showed SUPER LUCKY ROULETTE LEISURE ENT
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*/
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*/
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#include "driver.h"
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#include "driver.h"
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@ -75,8 +75,8 @@ static WRITE8_HANDLER( testfx_w )
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/*
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/*
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static READ8_HANDLER( test_r )
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static READ8_HANDLER( test_r )
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{
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{
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logerror("Read unknown port $f5 at %04x\n",cpu_get_pc(space->cpu));
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logerror("Read unknown port $f5 at %04x\n",cpu_get_pc(space->cpu));
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return mame_rand(space->machine) & 0x00ff;
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return mame_rand(space->machine) & 0x00ff;
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}
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}
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*/
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*/
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@ -1382,7 +1382,7 @@ static TIMER_CALLBACK(hbin)
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dc_sysctrl_regs[SB_ISTNRM] |= IST_HBL_IN; // H Blank-in interrupt
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dc_sysctrl_regs[SB_ISTNRM] |= IST_HBL_IN; // H Blank-in interrupt
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dc_update_interrupt_status(machine);
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dc_update_interrupt_status(machine);
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// printf("hbin on scanline %d\n",scanline);
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// printf("hbin on scanline %d\n",scanline);
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scanline++;
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scanline++;
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@ -394,14 +394,14 @@ static void draw_sprites(running_machine* const machine, bitmap_t* const bitmap)
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for (x = 0; x <= big; ++x)
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for (x = 0; x <= big; ++x)
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{
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{
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int const tile = code ^ (x << big_xshift) ^ (y << big_yshift);
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int const tile = code ^ (x << big_xshift) ^ (y << big_yshift);
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drawgfx(bitmap, gfx,
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drawgfx(bitmap, gfx,
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tile,
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tile,
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color,
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color,
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flipx,flipy,
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flipx,flipy,
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sx + 16*x, sy + 16*y,
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sx + 16*x, sy + 16*y,
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0, TRANSPARENCY_PEN, 15);
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0, TRANSPARENCY_PEN, 15);
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++sprites_drawn;
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++sprites_drawn;
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if (sprites_drawn >= 96)
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if (sprites_drawn >= 96)
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return;
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return;
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@ -436,7 +436,7 @@ static void erase_sprites(running_machine* const machine, bitmap_t* const bitmap
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for (x = 0; x < sp_bitmap->width; ++x)
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for (x = 0; x < sp_bitmap->width; ++x)
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{
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{
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UINT16* const ptr = BITMAP_ADDR16(sp_bitmap, y, x);
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UINT16* const ptr = BITMAP_ADDR16(sp_bitmap, y, x);
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if ( (*ptr & 0xf0) == stencil_palette ) { *ptr = 15; }
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if ( (*ptr & 0xf0) == stencil_palette ) { *ptr = 15; }
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////// Before modified, clears palettes 0-B and F, and leaves C-E on screen
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////// Before modified, clears palettes 0-B and F, and leaves C-E on screen
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////// But I'm sure "Ninja Kid II" clears F, and leaves 0-E
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////// But I'm sure "Ninja Kid II" clears F, and leaves 0-E
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@ -246,19 +246,19 @@ WRITE8_HANDLER( system1_sprite_collision_reset_w )
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* Video RAM access
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* Video RAM access
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*
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*
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*************************************/
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*************************************/
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INLINE void videoram_wait_states(const device_config *cpu)
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INLINE void videoram_wait_states(const device_config *cpu)
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{
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{
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/* The main Z80's CPU clock is halted whenever an access to VRAM happens,
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/* The main Z80's CPU clock is halted whenever an access to VRAM happens,
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and is only restarted by the FIXST signal, which occurs once every
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and is only restarted by the FIXST signal, which occurs once every
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'n' pixel clocks. 'n' is determined by the horizontal control PAL. */
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'n' pixel clocks. 'n' is determined by the horizontal control PAL. */
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/* this assumes 4 5MHz pixel clocks per FIXST, or 8*4 20MHz CPU clocks,
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/* this assumes 4 5MHz pixel clocks per FIXST, or 8*4 20MHz CPU clocks,
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and is based on a dump of 315-5137 */
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and is based on a dump of 315-5137 */
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const UINT32 cpu_cycles_per_fixst = 4 * 4;
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const UINT32 cpu_cycles_per_fixst = 4 * 4;
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const UINT32 fixst_offset = 2 * 4;
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const UINT32 fixst_offset = 2 * 4;
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UINT32 cycles_until_next_fixst = cpu_cycles_per_fixst - ((cpu_get_total_cycles(cpu) - fixst_offset) % cpu_cycles_per_fixst);
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UINT32 cycles_until_next_fixst = cpu_cycles_per_fixst - ((cpu_get_total_cycles(cpu) - fixst_offset) % cpu_cycles_per_fixst);
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cpu_adjust_icount(cpu, -cycles_until_next_fixst);
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cpu_adjust_icount(cpu, -cycles_until_next_fixst);
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}
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}
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@ -9,4 +9,4 @@
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***************************************************************************/
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***************************************************************************/
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const char build_version[] = "0.130u3 ("__DATE__")";
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const char build_version[] = "0.130u4 ("__DATE__")";
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