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Cleanups and version bump.

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This commit is contained in:
Aaron Giles 2009-04-16 07:48:39 +00:00
parent 49bc4d3ac2
commit 25ba9bfc08
5 changed files with 23 additions and 23 deletions
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4
src/mame/drivers/roul.c
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@ -75,8 +75,8 @@ static WRITE8_HANDLER( testfx_w )
/*
static READ8_HANDLER( test_r )
{
logerror("Read unknown port $f5 at %04x\n",cpu_get_pc(space->cpu));
return mame_rand(space->machine) & 0x00ff;
logerror("Read unknown port $f5 at %04x\n",cpu_get_pc(space->cpu));
return mame_rand(space->machine) & 0x00ff;
}
*/

2
src/mame/video/dc.c
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@ -1382,7 +1382,7 @@ static TIMER_CALLBACK(hbin)
dc_sysctrl_regs[SB_ISTNRM] |= IST_HBL_IN; // H Blank-in interrupt
dc_update_interrupt_status(machine);
// printf("hbin on scanline %d\n",scanline);
// printf("hbin on scanline %d\n",scanline);
scanline++;

6
src/mame/video/system1.c
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@ -250,11 +250,11 @@ WRITE8_HANDLER( system1_sprite_collision_reset_w )
INLINE void videoram_wait_states(const device_config *cpu)
{
/* The main Z80's CPU clock is halted whenever an access to VRAM happens,
and is only restarted by the FIXST signal, which occurs once every
'n' pixel clocks. 'n' is determined by the horizontal control PAL. */
and is only restarted by the FIXST signal, which occurs once every
'n' pixel clocks. 'n' is determined by the horizontal control PAL. */
/* this assumes 4 5MHz pixel clocks per FIXST, or 8*4 20MHz CPU clocks,
and is based on a dump of 315-5137 */
and is based on a dump of 315-5137 */
const UINT32 cpu_cycles_per_fixst = 4 * 4;
const UINT32 fixst_offset = 2 * 4;
UINT32 cycles_until_next_fixst = cpu_cycles_per_fixst - ((cpu_get_total_cycles(cpu) - fixst_offset) % cpu_cycles_per_fixst);

2
src/version.c
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@ -9,4 +9,4 @@
***************************************************************************/
const char build_version[] = "0.130u3 ("__DATE__")";
const char build_version[] = "0.130u4 ("__DATE__")";