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Merge pull request #1784 from JoakimLarsson/lwriterII_1

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WIP Apple Laser Writer II NT and some SCC improvements
This commit is contained in:
Vas Crabb 2016-12-01 06:05:05 +11:00 committed by GitHub
commit 2624c067a0
6 changed files with 296 additions and 79 deletions
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1
scripts/target/mame/mess.lua
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@ -1384,6 +1384,7 @@ files {
MAME_DIR .. "src/mame/drivers/lisa.cpp",
MAME_DIR .. "src/mame/includes/lisa.h",
MAME_DIR .. "src/mame/machine/lisa.cpp",
MAME_DIR .. "src/mame/drivers/lwriter.cpp",
MAME_DIR .. "src/mame/drivers/mac128.cpp",
MAME_DIR .. "src/mame/drivers/mac.cpp",
MAME_DIR .. "src/mame/includes/mac.h",

136
src/devices/machine/z80scc.cpp
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@ -81,14 +81,15 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
#define VERBOSE 0
#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
#define LOG(x) {} LOGPRINT(x)
#define LOGR(x) {} LOGPRINT(x)
#define LOGR(x) {}
#define LOGSETUP(x) {} LOGPRINT(x)
#define LOGINT(x) {} LOGPRINT(x)
#define LOGTX(x) {} LOGPRINT(x)
#define LOGRCV(x) {} LOGPRINT(x)
#define LOGCTS(x) {} LOGPRINT(x)
#define LOGDCD(x) {} LOGPRINT(x)
#define LOGSYNC(x) {} LOGPRINT(x)
#define LOGINT(x) {}
#define LOGCMD(x) {}
#define LOGTX(x) {}
#define LOGRCV(x) {}
#define LOGCTS(x) {}
#define LOGDCD(x) {}
#define LOGSYNC(x) {}
#if VERBOSE == 2
#define logerror printf
#endif
@ -1321,7 +1322,7 @@ uint8_t z80scc_channel::do_sccreg_rr0()
{
uint8_t rr0 = m_rr0;
LOGINT(("%s %c %s <- %02x\n",tag(), 'A' + m_index, FUNCNAME, m_rr0));
LOG(("%s %c %s <- %02x\n",tag(), 'A' + m_index, FUNCNAME, m_rr0));
if (m_extint_latch == 1)
{
rr0 &= ((~m_wr15) | WR15_WR7PRIME | WR15_STATUS_FIFO); // clear enabled bits, saving 2 unrelated bits
@ -1330,7 +1331,7 @@ uint8_t z80scc_channel::do_sccreg_rr0()
}
else
{
LOGINT(("- %c returning unlatched value: %02x\n", 'A' + m_index, rr0));
LOG(("- %c returning unlatched value: %02x\n", 'A' + m_index, rr0));
}
return rr0;
@ -1626,30 +1627,6 @@ uint8_t z80scc_channel::control_read()
return data;
}
/* CRC Initialization Code handling - candidate for breaking out in a z80sio_base class
Handle the WR0 CRC Reset/Init bits separatelly, needed by derived devices separatelly from the commands */
void z80scc_channel::do_sccreg_wr0_resets(uint8_t data)
{
LOG(("%s(%02x) %s",FUNCNAME, data, tag()));
switch (data & WR0_CRC_RESET_CODE_MASK)
{
case WR0_CRC_RESET_NULL:
LOG((" CRC_RESET_NULL\n"));
break;
case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */
LOGSYNC((" CRC_RESET_RX - not implemented\n"));
break;
case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */
LOGSYNC((" CRC_RESET_TX - not implemented\n"));
break;
case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the RRO register) */
LOGSYNC((" CRC_RESET_TX_UNDERRUN - not implemented\n"));
break;
default: /* Will not happen unless someone messes with the mask */
logerror(" Wrong CRC reset/init command:%02x\n", data & WR0_CRC_RESET_CODE_MASK);
}
}
/**/
void z80scc_channel::do_sccreg_wr0(uint8_t data)
{
@ -1688,7 +1665,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
(there are two transitions), another interrupt is not generated. Exceptions to this
rule are detailed in the RR0 description.*/
LOGINT(("%s %s %c - Reset External/Status Interrupt, latch %s\n", m_owner->tag(), FUNCNAME, 'A' + m_index,
LOGCMD(("%s %c - Reset External/Status Interrupt, latch %s\n", m_owner->tag(), 'A' + m_index,
m_extint_latch == 1? "is released" : "was already released"));
// Release latch if no other external or status sources are active
if ((m_extint_latch = m_uart->update_extint(m_index)) == 0)
@ -1702,18 +1679,18 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
if (m_uart->m_variant & (SET_NMOS))
{
logerror("WR0 SWI ack command not supported on NMOS\n");
LOGINT(("\"%s\" %s: %c : Reset Highest IUS command not available on NMOS!\n", m_owner->tag(), FUNCNAME, 'A' + m_index));
LOGCMD(("%s: %c : WR0_RESET_HIGHEST_IUS command not available on NMOS!\n", m_owner->tag(), 'A' + m_index));
}
else
{
LOGINT(("\"%s\" %s: %c : Reset Highest IUS\n", m_owner->tag(), FUNCNAME, 'A' + m_index));
LOGCMD(("%s: %c : Reset Highest IUS\n", m_owner->tag(), 'A' + m_index));
// loop over all interrupt sources
for (auto & elem : m_uart->m_int_state)
{
// find the first channel with an interrupt requested
if (elem & Z80_DAISY_INT)
{
LOGINT(("- %c found IUS bit to clear\n", 'A' + m_index));
LOGCMD(("- %c found IUS bit to clear\n", 'A' + m_index));
elem = 0; // Clear IUS bit (called IEO in z80 daisy lingo)
m_uart->check_interrupts();
break;
@ -1727,30 +1704,44 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
data with the special condition is held in the Receive FIFO until this command is issued. If either
of these modes is selected and this command is issued before the data has been read from the
Receive FIFO, the data is lost */
LOG(("\"%s\" %s: %c : WR0_ERROR_RESET\n", m_owner->tag(), FUNCNAME, 'A' + m_index));
//do_sccreg_wr0(data); // reset status registers
LOGCMD(("%s: %c : WR0_ERROR_RESET - not implemented\n", m_owner->tag(), 'A' + m_index));
m_rx_fifo_rp_step(); // Reset error state in fifo and unlock it. unlock == step to next slot in fifo.
break;
case WR0_SEND_ABORT:
data &= 0xef; // convert SCC SEND_ABORT command to a SIO SEND_ABORT command and fall through
/* The following commands relies on the SIO default behviour */
case WR0_NULL:
LOG(("\"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index));
case WR0_SEND_ABORT: // Flush transmitter and Send 8-13 bits of '1's, used with SDLC
LOGCMD(("%s: %c : WR0_SEND_ABORT - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_ENABLE_INT_NEXT_RX:
// enable interrupt on next receive character
LOG(("\"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index));
case WR0_NULL: // Do nothing
LOGCMD(("%s: %c : WR0_NULL\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_ENABLE_INT_NEXT_RX: // enable interrupt on next receive character
LOGCMD(("%s: %c : WR0_ENABLE_INT_NEXT\n", m_owner->tag(), 'A' + m_index));
m_rx_first = 1;
break;
case WR0_RESET_TX_INT:
// reset transmitter interrupt pending
LOG(("\"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index));
logerror("\"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index);
case WR0_RESET_TX_INT: // reset transmitter interrupt pending
LOGCMD(("%s: %c : WR0_RESET_TX_INT - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
default:
break;
}
do_sccreg_wr0_resets(data);
/* CRC Initialization Code handling */
switch (data & WR0_CRC_RESET_CODE_MASK)
{
case WR0_CRC_RESET_NULL:
LOGCMD((" CRC_RESET_NULL\n"));
break;
case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */
LOGCMD((" CRC_RESET_RX - not implemented\n"));
break;
case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */
LOGCMD((" CRC_RESET_TX - not implemented\n"));
break;
case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the RRO register) */
LOGCMD((" CRC_RESET_TX_UNDERRUN - not implemented\n"));
break;
default: /* Will not happen unless someone messes with the mask */
logerror(" Wrong CRC reset/init command:%02x\n", data & WR0_CRC_RESET_CODE_MASK);
}
if ( m_uart->m_variant & SET_Z85X3X)
{
@ -2278,27 +2269,14 @@ uint8_t z80scc_channel::data_read()
data = m_rx_fifo_rp_data();
// load error status from the FIFO
m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo_rp]; // TODO: Status FIFO needs to be fixed
m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo_rp];
// trigger interrup and lock the fifo if an error is present
// trigger interrupt and lock the fifo if an error is present
if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR))
{
logerror("Rx Error %02x\n", m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR));
switch (m_wr1 & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_FIRST:
if (!m_rx_first)
{
m_uart->trigger_interrupt(m_index, INT_SPECIAL);
}
break;
case WR1_RX_INT_ALL_PARITY:
case WR1_RX_INT_ALL:
m_uart->trigger_interrupt(m_index, INT_SPECIAL);
break;
}
}
else
{
// decrease FIFO pointer
@ -2446,22 +2424,30 @@ void z80scc_channel::data_write(uint8_t data)
//-------------------------------------------------
// receive_data - receive data word into fifo
// receive_data - put received data word into fifo
//-------------------------------------------------
void z80scc_channel::receive_data(uint8_t data)
{
LOG(("\"%s\": %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data));
LOG(("\"%s\": %c : Received Data Byte '%c'/%02x put into FIFO\n", m_owner->tag(), 'A' + m_index, isprint(data) ? data : ' ', data));
if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
{
// receive overrun error detected
m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR; // = m_rx_error; TODO: Status FIFO needs to be fixed
m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR;
// store received character but do not step the fifo
m_rx_data_fifo[m_rx_fifo_wp] = data;
logerror("Receive_data() Error %02x\n", m_rx_error_fifo[m_rx_fifo_wp] & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR));
}
else
{
m_rx_error_fifo[m_rx_fifo_wp] &= ~RR1_RX_OVERRUN_ERROR; // = m_rx_error; TODO: Status FIFO needs to be fixed
m_rx_error_fifo[m_rx_fifo_wp] &= ~RR1_RX_OVERRUN_ERROR;
// store received character
m_rx_data_fifo[m_rx_fifo_wp] = data;
m_rx_fifo_wp++;
if (m_rx_fifo_wp >= m_rx_fifo_sz)
{
@ -2469,13 +2455,9 @@ void z80scc_channel::receive_data(uint8_t data)
}
}
// store received character
m_rx_data_fifo[m_rx_fifo_wp] = data;
m_rr0 |= RR0_RX_CHAR_AVAILABLE;
#if 0 // interrupt on exit from fifo
// receive interrupt
// receive interrupt on FIRST and ALL character
switch (m_wr1 & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_FIRST:
@ -2487,12 +2469,10 @@ void z80scc_channel::receive_data(uint8_t data)
}
break;
case WR1_RX_INT_ALL_PARITY:
case WR1_RX_INT_ALL:
m_uart->trigger_interrupt(m_index, INT_RECEIVE);
break;
}
#endif
}

1
src/emu/drivers/xtal.h
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@ -173,6 +173,7 @@ enum
XTAL_21_3MHz = 21300000,
XTAL_21_4772MHz = 21477272, /* BMC bowling, some Data East 90's games, Vtech Socrates; (6x NTSC subcarrier) */
XTAL_22MHz = 22000000,
XTAL_22_3210MHz = 22321000, /* Apple LaserWriter II NT */
XTAL_22_1184MHz = 22118400, /* Amusco Poker */
XTAL_23_9616MHz = 23961600, /* Osborne 4 (Vixen) */
XTAL_24MHz = 24000000, /* Mario, 80's Data East games, 80's Konami games */

231
src/mame/drivers/lwriter.cpp Normal file
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@ -0,0 +1,231 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
/******************************************************************************
Apple LaserWriter II NT driver
TODO:
- Figure out what VIA pins is connected to switch on front that selects LocalTalk
- Let the board identify itself to a emulated mac driver so it displays the printer icon on the desktop
- Everything else
******************************************************************************/
/*
* Hardware: 68000@11.16 MHz
8530 SCC
6523 TPI or 6522 VIA on newer pcb:s
2MB DRAM
2KB SRAM
custom 335-0022 EEPROM
1MB ROM
+------------------------------------------------------------------------------------------------------------------------+=====+
| 1 2 3 4 5 6 7 8 9 10 11 | #
| +------+ +------+ +---------+ +-------+ +------+ +-+ | #
|A |511000| | F257 | |335-0022 | | 0296 | |22.3210 | | J2| #
| +------+ +------+ |EEPROM | +-------+ +-------+ |XTAL | | | | #
|B |511000| | RP2B | +---------+ | | +------+ | | | #
| +------+ +------+ | 68000 | +-------+ +-------+ +-+ | #
|C |511000| | F257 | | | | 0558 | | F175 | +-+ | #
| +------+ +------+ +---------+ | | +-------+ +-------+ | | | #
|D |511000| +------+ |Am9128-10| | | +-------+ +-------+ +-------+ | | | #
| +------+ | F257 | |SRAM | | | | 0559 | | 0557 | | LS393 | | | | #
|E |511000| +------+ +---------+ | | +-------+ +-------+ +-------+ +-+ | F #
| +------+ +------+ +---------+ | | +------+ | #
|F |511000| | F138 | |Am9128-10| | | +-----------------+ |26LS32| J3| R #
| +------+ +------+ |SRAM | | | | Z8530B1C | +------+ | #
|G |511000| +--------++ | | | SCC | |26LS32| | O #
| +------+ +------+ | F244 | | | +----+ +-----------------+ +------+ | #
|H |511000| | RP2H | +--------+ +-------+ |7705| +------+ | N #
| +------+ +------+ | F244 | +----+ +-----------------+ |26LS30| | #
|J |511000| | 0259 | +--------+-+----------+ o------o | 338-6523 | +------+ | T #
| +------+ +------+ | TC531000 | TC531000 | | CONN | | TPI | |26LS30| | #
|K |511000| +------+ | ROM H3 | ROM L3 | +------+ | == | +-----------------+ +------+ | #
| +------+ | RP2L | +----------+----------+ | F02 | | == | +-------+ | #
|L |511000| +------+ +----------+----------+ +------+ | == | | LS14 | | #
| +------+ | 0259 | | TC531000 | TC531000 | +------++------+ | == | +-------+ | #
|M |511000| +------+ | ROM H2 | ROM L2 | |67L401|| LS166| | == | | LS14 | | #
| +------+ +------+ +----------+----------+ +------++------+ | == | +-------+ +------+ | #
|N |511000| | F245 | +----------+----------+ +------++------+ | == | | 0440A| | #
| +------+ +------+ | TC531000 | TC531000 | |67L401|| LS00 | | == | +------+ | #
|P |511000| +------+ | ROM H1 | ROM L1 | +------++------+ o------o +------+ | #
| +------+ | F245 | +----------+----------+ +-------+ |TL497 | | #
|R |511000| +------+ +----------+----------+ | LS273 | +------+ | #
| +------+ +------+ | TC531000 | TC531000 | +-------+ | #
|S |511000| | RP2S | | ROM H0 | ROM L0 | | LS05 | | #
| +------+ +------+ +----------+----------+ +------+ (c)1987 J4| #
| DRAM LASERWRITER II NT Apple Computer 640-4105 | #
+------------------------------------------------------------------------------------------------------------------------+=====+
*/
#define TPI 0 //The TPI is used on the original M6009 board but the first dump is from a newer that uses a VIA
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "bus/rs232/rs232.h"
#include "machine/z80scc.h"
#if TPI
#include "machine/6525tpi.h"
#else
#include "machine/6522via.h"
#endif
class lwriter_state : public driver_device
{
public:
lwriter_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_scc(*this, "scc")
, m_via(*this, "via")
{ }
DECLARE_READ16_MEMBER (bootvect_r);
DECLARE_WRITE16_MEMBER (bootvect_w);
virtual void machine_start () override;
virtual void machine_reset () override;
private:
required_device<cpu_device> m_maincpu;
required_device<scc8530_device> m_scc;
#if TPI
#define tpi6523_device tpi6525_device/* TODO: define a type for the TPI6523 of its own in the device header file */
required_device<tpi6523_device> m_tpi;
#else
required_device<via6522_device> m_via;
#endif
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
uint16_t *m_sysrom;
uint16_t m_sysram[2];
};
static ADDRESS_MAP_START (maincpu_map, AS_PROGRAM, 16, lwriter_state)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00000000, 0x00000007) AM_ROM AM_READ(bootvect_r) /* ROM mirror just during reset */
AM_RANGE(0x00000000, 0x00000007) AM_RAM AM_WRITE(bootvect_w) /* After first write we act as RAM */
AM_RANGE(0x00000008, 0x001fffff) AM_RAM /* 2 Mb DRAM */
AM_RANGE(0x00200000, 0x003fffff) AM_ROM AM_REGION("roms", 0)
AM_RANGE(0x00c00000, 0x00c00001) AM_DEVWRITE8("scc", scc8530_device, ca_w, 0x00ff)
AM_RANGE(0x00c00004, 0x00c00005) AM_DEVWRITE8("scc", scc8530_device, da_w, 0x00ff)
AM_RANGE(0x00a00000, 0x00a00001) AM_DEVREAD8 ("scc", scc8530_device, ca_r, 0xff00)
AM_RANGE(0x00a00004, 0x00a00005) AM_DEVREAD8 ("scc", scc8530_device, da_r, 0xff00)
AM_RANGE(0x00c00002, 0x00c00003) AM_DEVWRITE8("scc", scc8530_device, cb_w, 0x00ff)
AM_RANGE(0x00c00006, 0x00c00007) AM_DEVWRITE8("scc", scc8530_device, db_w, 0x00ff)
AM_RANGE(0x00a00002, 0x00a00003) AM_DEVREAD8 ("scc", scc8530_device, cb_r, 0xff00)
AM_RANGE(0x00a00006, 0x00a00007) AM_DEVREAD8 ("scc", scc8530_device, db_r, 0xff00)
#if TPI
AM_RANGE(0x00e00010, 0x00e0001f) AM_DEVREADWRITE8 ("tpi", tpi6523_device, read, write, 0x00ff) // Used on older boards, needs proper mapping
#else
AM_RANGE(0x00e00000, 0x00e0001f) AM_DEVREADWRITE8 ("via", via6522_device, read, write, 0x00ff)
#endif
ADDRESS_MAP_END
static INPUT_PORTS_START( lwriter )
INPUT_PORTS_END
/* Start it up */
void lwriter_state::machine_start()
{
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (uint16_t*)(memregion ("roms")->base ());
}
void lwriter_state::machine_reset ()
{
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (uint16_t*)(memregion ("roms")->base ());
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
READ16_MEMBER (lwriter_state::bootvect_r){
return m_sysrom[offset];
}
WRITE16_MEMBER (lwriter_state::bootvect_w){
m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
}
#define CPU_CLK (XTAL_22_3210MHz / 2) // Based on pictures form here: http://picclick.co.uk/Apple-Postscript-LaserWriter-IINT-Printer-640-4105-M6009-Mainboard-282160713108.html#&gid=1&pid=7
#define RXC_CLK ((CPU_CLK - (87 * 16 * 70)) / 3) // Tuned to get 9600 baud according to manual, needs rework based on real hardware
static MACHINE_CONFIG_START( lwriter, lwriter_state )
MCFG_CPU_ADD("maincpu", M68000, CPU_CLK)
MCFG_CPU_PROGRAM_MAP(maincpu_map)
MCFG_SCC8530_ADD("scc", CPU_CLK, RXC_CLK, 0, RXC_CLK, 0)
/* Port A */
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_txd))
MCFG_Z80SCC_OUT_DTRA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_dtr))
MCFG_Z80SCC_OUT_RTSA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_rts))
/* Port B */
MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_txd))
MCFG_Z80SCC_OUT_DTRB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_dtr))
MCFG_Z80SCC_OUT_RTSB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_rts))
MCFG_RS232_PORT_ADD ("rs232a", default_rs232_devices, "terminal")
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("scc", scc8530_device, rxa_w))
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("scc", scc8530_device, ctsa_w))
MCFG_RS232_PORT_ADD ("rs232b", default_rs232_devices, "terminal")
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("scc", scc8530_device, rxb_w))
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("scc", scc8530_device, ctsb_w))
#if TPI
MCFG_DEVICE_ADD("tpi", TPI6525, 0)
#else
MCFG_DEVICE_ADD("via", VIA6522, 0)
#endif
MACHINE_CONFIG_END
/* SCC init sequence
* :scc B Reg 09 <- c0 - Master Interrupt Control - Device reset
* -
* :scc A Reg 0f <- 00 - External/Status Control Bits - Disable all
* :scc B Reg 05 <- 02 - Tx setup: 5 bits, Tx disable, RTS:1 DTR:0
* :scc B Reg 05 <- 00 - Tx setup: 5 bits, Tx disable, RTS:0 DTR:0
* -
* :scc A Reg 09 <- c0 - Master Interrupt Control - Device reset
*
* -
* :scc A Reg 0f <- 00 - External/Status Control Bits - Disable all
* :scc A Reg 04 <- 4c - Setting up Asynchrounous mode: 2 Stop bits, No parity, 16x clock
* :scc A Reg 0b <- 50 - Clock Mode Control - TTL clk on RTxC, Rx and Tx clks from BRG, TRxC is input
* :scc A Reg 0e <- 00 - Misc Control Bits - BRG clk is RTxC, BRG is disabled
* :scc A Reg 0c <- 0a - Low byte of baudrate generator constant
* :scc A Reg 0d <- 00 - Hi byte of baudrate generator constant
* :scc A Reg 0e <- 01 - BRG enabled with external clk from RTxC
* :scc A Reg 0a <- 00 - Synchronous parameters, all turned off
* :scc A Reg 03 <- c1 - Rx setup: 8 bits, Rx enabled
* :scc A Reg 05 <- 6a - Tx setup: 8 bits, Tx enable, RTS:1 DTR:0
* -
* :scc A Reg 01 <- 00 - Rx interrupt disabled
* :scc A Reg 01 <- 30 - Wait/Ready on receive, Rx int an all characters, parity affect vector
* :scc A Reg 00 <- 30 - Error Reset command
* -
* :scc A Reg 01 <- 01 - External interrupt enabled, Rx ints disabled
* :scc A Reg 00 <- 30 - Error Reset command
* :scc A Reg 00 <- 30 - Error Reset command
* - last three loops
*/
ROM_START(lwriter)
ROM_REGION16_BE (0x1000000, "roms", 0)
ROM_LOAD16_BYTE ("342-0545.l0", 0x000001, 0x20000, CRC (6431742d) SHA1 (040bd5b84b49b86f2b0fe9ece378bbc7a10a94ec))
ROM_LOAD16_BYTE ("342-0546.h0", 0x000000, 0x20000, CRC (c592bfb7) SHA1 (b595ae225238f7fabd1566a3133ea6154e082e2d))
ROM_LOAD16_BYTE ("342-0547.l1", 0x040001, 0x20000, CRC (205a5ea8) SHA1 (205fefbb5c67a07d57cb6184c69648321a34a8fe))
ROM_LOAD16_BYTE ("342-0548.h1", 0x040000, 0x20000, CRC (f616e1c3) SHA1 (b9e2cd4d07990b2d1936be97b6e89ef21f06b462))
ROM_LOAD16_BYTE ("342-0549.l2", 0x080001, 0x20000, CRC (0b0b051a) SHA1 (64a80085001570c3f99d9865031715bf49bd7698))
ROM_LOAD16_BYTE ("342-0550.h2", 0x080000, 0x20000, CRC (82adcf85) SHA1 (e2ab728afdae802c0c67fc25c9ba278b9cb04e31))
ROM_LOAD16_BYTE ("342-0551.l3", 0x0c0001, 0x20000, CRC (176b3346) SHA1 (eb8dfc7e44f2bc884097e51a47e2f10ee091c9e9))
ROM_LOAD16_BYTE ("342-0552.h3", 0x0c0000, 0x20000, CRC (69b175c6) SHA1 (a84c82be1ec7e373bb097ee74b941920a3b091aa))
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT, COMPANY, FULLNAME, FLAGS */
CONS( 1988, lwriter, 0, 0, lwriter, lwriter, driver_device, 0, "Apple", "Apple Laser Writer II NT", MACHINE_IS_SKELETON)

3
src/mame/mame.lst
View File

@ -17313,6 +17313,9 @@ trojanj // 4/1986 (c) 1986 (Japan)
trojanr // 4/1986 (c) 1986 + Romstar
fball //
@source:lwriter.cpp
lwriter // Apple LaserWriter
@source:lynx.cpp
lynx // Atari Lynx Handheld

1
src/mame/mess.flt
View File

@ -309,6 +309,7 @@ lisa.cpp
llc.cpp
lola8a.cpp
lviv.cpp
lwriter.cpp
lynx.cpp
m20.cpp
m24.cpp