From 262fbb40095b4e6484997bb28ecb17f674b04a34 Mon Sep 17 00:00:00 2001 From: Ted Green Date: Fri, 18 Mar 2016 14:06:52 -0600 Subject: [PATCH] Added Big Buck Hunter II --- src/mame/drivers/iteagle.cpp | 30 ++++++++++++++-- src/mame/machine/iteagle_fpga.cpp | 59 +++++++++++++++++++++++-------- src/mame/machine/iteagle_fpga.h | 5 ++- src/mame/mame.lst | 1 + 4 files changed, 77 insertions(+), 18 deletions(-) diff --git a/src/mame/drivers/iteagle.cpp b/src/mame/drivers/iteagle.cpp index ff6b387bc45..cc58445128f 100644 --- a/src/mame/drivers/iteagle.cpp +++ b/src/mame/drivers/iteagle.cpp @@ -142,11 +142,11 @@ void iteagle_state::machine_reset() { } -#define PCI_ID_IDE ":pci:06.0" +#define PCI_ID_IDE ":pci:06.0" // Primary IDE Control ":pci:06.1" // Seconday IDE Control ":pci:06.2" #define PCI_ID_SOUND ":pci:07.0" -#define PCI_ID_FPGA ":pci:08.0" +#define PCI_ID_FPGA ":pci:08.0" #define PCI_ID_VIDEO ":pci:09.0" #define PCI_ID_EEPROM ":pci:0a.0" @@ -228,7 +228,15 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( bbhsc, iteagle ) MCFG_DEVICE_MODIFY(PCI_ID_FPGA) - MCFG_ITEAGLE_FPGA_INIT(0x02000600, 0x0c0a0a) + // 0xXX01XXXX = tournament board + MCFG_ITEAGLE_FPGA_INIT(0x02010600, 0x0c0a0a) + MCFG_DEVICE_MODIFY(PCI_ID_EEPROM) + MCFG_ITEAGLE_EEPROM_INIT(0x0000, 0x7) +MACHINE_CONFIG_END + +static MACHINE_CONFIG_DERIVED( bbh2sp, iteagle ) + MCFG_DEVICE_MODIFY(PCI_ID_FPGA) + MCFG_ITEAGLE_FPGA_INIT(0x02000602, 0x0d0a0a) MCFG_DEVICE_MODIFY(PCI_ID_EEPROM) MCFG_ITEAGLE_EEPROM_INIT(0x0000, 0x7) MACHINE_CONFIG_END @@ -538,6 +546,21 @@ ROM_START( bbhsc ) DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" ) DISK_IMAGE( "bbhsc_v1.50.07_cf", 0, SHA1(21dcf1f7e5ab901ac64e6afb099c35e273b3bf1f) ) /* Build 16:35:34, Feb 26 2002 - 4gb Compact Flash conversion */ ROM_END + //DISK_IMAGE( "bbhsc_v1.50.07_cf", 0, SHA1(21dcf1f7e5ab901ac64e6afb099c35e273b3bf1f) ) /* Build 16:35:34, Feb 26 2002 - 4gb Compact Flash conversion */ + //DISK_IMAGE( "bbhsc_v1.60.01", 0, SHA1(8554fdd7193ee27c0fe8ca921aa8db9c0378b313) ) + +ROM_START( bbh2sp ) + EAGLE_BIOS + + ROM_REGION( 0x0880, "atmel", 0 ) /* Atmel 90S2313 AVR internal CPU code */ + ROM_LOAD( "bbh2-us.u53", 0x0000, 0x0880, NO_DUMP ) + + DISK_REGION( PCI_ID_IDE":ide:0:hdd:image" ) + DISK_IMAGE( "bbh2sp_v2.02.11", 0, SHA1(63e41cca534f4774bfba4b4dda9620fe805029b4) ) +ROM_END + //DISK_IMAGE( "bbh2sp_v2.02.08", 0, SHA1(13b9b4ea0465f55dd1c7bc6e2f962c3c9b9566bd) ) + //DISK_IMAGE( "bbh2sp_v2.02.09", 0, SHA1(fac3963b6da35a8c8b00f6826bc10e9c7230b1d6) ) + //DISK_IMAGE( "bbh2sp_v2.02.11", 0, SHA1(63e41cca534f4774bfba4b4dda9620fe805029b4) ) ROM_START( bbhcotw ) /* This version is meant for 8meg GREEN board PCBs */ EAGLE_BIOS @@ -570,4 +593,5 @@ GAME( 2004, gtfore05b, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "I GAME( 2004, gtfore05c, gtfore05, gtfore05, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2005 Extra (v5.00.00)", 0 ) GAME( 2005, gtfore06, iteagle, gtfore06, iteagle, driver_device, 0, ROT0, "Incredible Technologies", "Golden Tee Fore! 2006 Complete (v6.00.01)", 0 ) GAME( 2002, bbhsc, iteagle, bbhsc, bbh, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter - Shooter's Challenge (v1.50.07)", MACHINE_NOT_WORKING ) // doesn't boot +GAME( 2002, bbh2sp, iteagle, bbh2sp, bbh, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter II - Sportsman's Paradise (v2.02.11)", MACHINE_NOT_WORKING ) // SW51-2 needs to be off GAME( 2006, bbhcotw, iteagle, bbhcotw, bbh, driver_device, 0, ROT0, "Incredible Technologies", "Big Buck Hunter Call of the Wild (v3.02.5)", MACHINE_NOT_WORKING ) // random lockups diff --git a/src/mame/machine/iteagle_fpga.cpp b/src/mame/machine/iteagle_fpga.cpp index 40e1a9bb19e..8035156edae 100644 --- a/src/mame/machine/iteagle_fpga.cpp +++ b/src/mame/machine/iteagle_fpga.cpp @@ -73,9 +73,11 @@ void iteagle_fpga_device::device_reset() m_seq_rem1 = 0; m_seq_rem2 = 0; + // Nibble starting at bit 20 is resolution, byte 0 is atmel response // 0x00080000 and interrupt starts reading from 0x14 // 0x02000000 and interrupt starts reading from 0x18 - m_fpga_regs[0x04/4] = 0x00000000; // Nibble starting at bit 20 is resolution, byte 0 is atmel response + // Write 0x01000000 is a global interrupt clear + m_fpga_regs[0x04/4] = 0x00000000; m_prev_reg = 0; m_serial_str.clear(); @@ -89,6 +91,7 @@ void iteagle_fpga_device::device_reset() m_serial_com1[0] = 0x2c; m_serial_com2[0] = 0x2c; m_serial_com3[0] = 0x2c; + m_serial_rx3.clear(); } void iteagle_fpga_device::update_sequence(UINT32 data) @@ -144,7 +147,7 @@ void iteagle_fpga_device::update_sequence_eg1(UINT32 data) m_seq = (m_seq>>9) | ((feed&0x1ff)<<15); m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff); } - if (0 && LOG_FPGA) + if (0 && LOG_FPGA) logerror("%s:fpga update_sequence In: %02X Seq: %06X Out: %02X other %02X%02X%02X\n", machine().describe_context(), data, m_seq, m_fpga_regs[offset]&0xff, m_seq_rem2, m_seq_rem1, val1); } @@ -154,7 +157,7 @@ void iteagle_fpga_device::update_sequence_eg1(UINT32 data) //------------------------------------------------- void iteagle_fpga_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr) { - if (m_fpga_regs[0x4/4]&0x01000000) { + if (m_fpga_regs[0x4/4] & 0x01000000) { //m_fpga_regs[0x04/4] |= 0x02080000; m_fpga_regs[0x04/4] |= 0x00080000; m_cpu->set_input_line(m_irq_num, ASSERT_LINE); @@ -179,7 +182,6 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r ) if (LOG_FPGA && !ACCESSING_BITS_0_7) logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; - case 0x08/4: result = ((machine().root_device().ioport("TRACKY1")->read()&0xff)<<8) | (machine().root_device().ioport("TRACKX1")->read()&0xff); if (LOG_FPGA && m_prev_reg!=offset) @@ -195,7 +197,7 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r ) if (LOG_FPGA) logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; - case 0x0c/4: // 1d = modem byte + case 0x0c/4: // result = (result & 0xFFFF0000) | ((m_serial_com1[m_serial_idx]&0xff)<<8) | (m_serial_com0[m_serial_idx]&0xff); if (ACCESSING_BITS_0_15) { m_serial_data = false; @@ -210,12 +212,25 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r ) m_serial_data = false; m_serial_idx = 0; } + if (ACCESSING_BITS_24_31) { + if (!m_serial_rx3.empty()) { + logerror("fpga_r: read byte: %c\n", m_serial_rx3.at(0)); + result = (result & 0x00FFFFFF) | (m_serial_rx3.at(0)<<24); + m_serial_rx3.erase(m_serial_rx3.begin()); + } + if (m_serial_rx3.empty()) { + m_serial_com3[0] &= ~0x1; + m_serial_com3[3] &= ~0x20; + m_cpu->set_input_line(4, CLEAR_LINE); + } + } if (LOG_FPGA) logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; default: if (LOG_FPGA) logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + osd_printf_debug("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; } if (offset!=0x4/4) @@ -236,9 +251,12 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) update_sequence(data & 0xff); if (0 && LOG_FPGA) logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); - } + } else if (ACCESSING_BITS_8_15) { + // Interrupt enable? + if (LOG_FPGA) + logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + } else if (ACCESSING_BITS_24_31 && (data & 0x01000000)) { // Interrupt clear/enable - if (ACCESSING_BITS_24_31 && (data & 0x01000000)) { m_cpu->set_input_line(m_irq_num, CLEAR_LINE); // Not sure what value to use here, needed for lightgun m_timer->adjust(attotime::from_hz(59)); @@ -295,7 +313,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) if (m_serial_str.size()==0) m_serial_str = "com1: "; m_serial_str += (data>>24)&0xff; - if (1 || ((data>>24)&0xff)==0xd) { + if (1) { if (LOG_SERIAL) logerror("%s\n", m_serial_str.c_str()); osd_printf_debug("%s\n", m_serial_str.c_str()); m_serial_str.clear(); @@ -326,7 +344,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) if (m_serial_str.size()==0) m_serial_str = "com2: "; m_serial_str += (data>>16)&0xff; - if (1 || ((data>>16)&0xff)==0xd) { + if (1) { if (LOG_SERIAL) logerror("%s\n", m_serial_str.c_str()); osd_printf_debug("%s\n", m_serial_str.c_str()); m_serial_str.clear(); @@ -339,6 +357,15 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) if (((data>>24)&0xff)==0xd) { if (LOG_SERIAL) logerror("%s\n", m_serial_str.c_str()); osd_printf_debug("%s\n", m_serial_str.c_str()); + if (m_serial_str.find("ATI5") != -1) + m_serial_rx3 += "OK\r181\r"; + else if (m_serial_str.find("ATS0?") != -1) + m_serial_rx3 += "0\r"; + else + m_serial_rx3 += "OK\r"; + m_serial_com3[0] |= 0x1; + m_serial_com3[3] = 0x20; + m_cpu->set_input_line(4, ASSERT_LINE); m_serial_str.clear(); } } @@ -348,6 +375,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) default: if (LOG_FPGA) logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + osd_printf_debug("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); break; } } @@ -362,7 +390,7 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) void iteagle_fpga_device::nvram_default() { - memset(m_rtc_regs, 0, sizeof(m_rtc_regs)); + memset(m_rtc_regs, 0x0, sizeof(m_rtc_regs)); } //------------------------------------------------- @@ -466,7 +494,8 @@ ADDRESS_MAP_END // 0x6 = OperID // 0xe = SW Version // 0xf = 0x01 for extra courses -// 0x7f = checksum +// 0x3e = 0x0002 for good nvram +// 0x3f = checksum static const UINT16 iteagle_default_eeprom[0x40] = { 0xd000,0x0022,0x0000,0x0003,0x1209,0x1111,0x2222,0x1234, @@ -652,7 +681,7 @@ void iteagle_ide_device::device_reset() { pci_device::device_reset(); memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs)); - m_ctrl_regs[0x10/4] = 0x00070000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3. Bit 0 might be lan chip present. + m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3. Bit 0 might be lan chip present. memset(m_rtc_regs, 0, sizeof(m_rtc_regs)); m_rtc_regs[0xa] = 0x20; // 32.768 MHz m_rtc_regs[0xb] = 0x02; // 24-hour format @@ -667,6 +696,7 @@ READ32_MEMBER( iteagle_ide_device::ctrl_r ) case 0x0/4: if (LOG_IDE_REG) logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + osd_printf_debug("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; case 0x70/4: if (ACCESSING_BITS_8_15) { @@ -696,6 +726,7 @@ READ32_MEMBER( iteagle_ide_device::ctrl_r ) default: if (LOG_IDE_REG) logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + osd_printf_debug("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; } return result; @@ -737,7 +768,7 @@ READ32_MEMBER( iteagle_ide_device::ide_r ) if (m_irq_num!=-1 && m_irq_status==1) { m_irq_status = 0; m_cpu->set_input_line(m_irq_num, CLEAR_LINE); - if (LOG_IDE) + if (LOG_IDE_CTRL) logerror("%s:ide_r Clearing interrupt\n", machine().describe_context()); } } @@ -752,7 +783,7 @@ WRITE32_MEMBER( iteagle_ide_device::ide_w ) if (m_irq_num!=-1 && m_irq_status==1) { m_irq_status = 0; m_cpu->set_input_line(m_irq_num, CLEAR_LINE); - if (LOG_IDE) + if (LOG_IDE_CTRL) logerror("%s:ide_w Clearing interrupt\n", machine().describe_context()); } } diff --git a/src/mame/machine/iteagle_fpga.h b/src/mame/machine/iteagle_fpga.h index fe5f9a76687..890683c4d70 100644 --- a/src/mame/machine/iteagle_fpga.h +++ b/src/mame/machine/iteagle_fpga.h @@ -10,6 +10,8 @@ #include "machine/idectrl.h" #include "machine/eepromser.h" +//MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id) + #define MCFG_ITEAGLE_FPGA_ADD(_tag, _cpu_tag, _irq_num) \ MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_FPGA, 0x55CC33AA, 0xAA, 0xAAAAAA, 0x00) \ downcast(device)->set_irq_info(_cpu_tag, _irq_num); @@ -18,7 +20,7 @@ downcast(device)->set_init_info(_version, _seq_init); #define MCFG_ITEAGLE_EEPROM_ADD(_tag) \ - MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_EEPROM, 0x80861229, 0x00, 0x088000, 0x00) + MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_EEPROM, 0x80861229, 0x02, 0x020000, 0x00) #define MCFG_ITEAGLE_EEPROM_INIT(_sw_version, _hw_version) \ downcast(device)->set_info(_sw_version, _hw_version); @@ -61,6 +63,7 @@ private: UINT32 m_prev_reg; std::string m_serial_str; + std::string m_serial_rx3; UINT8 m_serial_idx; bool m_serial_data; UINT8 m_serial_com0[0x10]; diff --git a/src/mame/mame.lst b/src/mame/mame.lst index 5922ef777c0..10d623840a1 100644 --- a/src/mame/mame.lst +++ b/src/mame/mame.lst @@ -14207,6 +14207,7 @@ iskr1031 // istellar // (c) 1983 Funai / Gakken @source:iteagle.cpp +bbh2sp // bbhcotw // bbhsc // carnking //