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https://github.com/holub/mame
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rx01_cpu: Start executing some instructions (nw)
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AJR
parent
0d06ae9f4d
commit
2645475b75
@ -10,24 +10,33 @@
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#include "rx01.h"
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#include "rx01dasm.h"
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//#define VERBOSE 1
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#include "logmacro.h"
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// device type definition
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DEFINE_DEVICE_TYPE(RX01_CPU, rx01_cpu_device, "rx01_cpu", "DEC RX01 CPU")
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rx01_cpu_device::rx01_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: cpu_device(mconfig, RX01_CPU, tag, owner, clock)
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, m_rom_config("program", ENDIANNESS_LITTLE, 8, 12, 0)
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, m_inst_config("program", ENDIANNESS_LITTLE, 8, 12, 0)
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, m_sp_config("scratchpad", ENDIANNESS_LITTLE, 8, 4, 0, address_map_constructor(FUNC(rx01_cpu_device::scratchpad_map), this))
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, m_rom_cache(nullptr)
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, m_inst_cache(nullptr)
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, m_sp_cache(nullptr)
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, m_pc(0)
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, m_ppc(0)
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, m_mb(0)
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, m_br_condition(false)
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, m_inst_disable(false)
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, m_inst_repeat(false)
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, m_cntr(0)
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, m_sr(0)
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, m_spar(0)
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, m_bar(0)
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, m_crc(0)
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, m_flag(false)
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, m_icount(0)
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{
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m_rom_config.m_is_octal = true;
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m_inst_config.m_is_octal = true;
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m_sp_config.m_is_octal = true;
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}
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@ -44,14 +53,14 @@ void rx01_cpu_device::scratchpad_map(address_map &map)
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device_memory_interface::space_config_vector rx01_cpu_device::memory_space_config() const
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{
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return space_config_vector {
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std::make_pair(AS_PROGRAM, &m_rom_config),
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std::make_pair(AS_PROGRAM, &m_inst_config),
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std::make_pair(AS_DATA, &m_sp_config)
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};
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}
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void rx01_cpu_device::device_start()
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{
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m_rom_cache = space(AS_PROGRAM).cache<0, 0, ENDIANNESS_LITTLE>();
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m_inst_cache = space(AS_PROGRAM).cache<0, 0, ENDIANNESS_LITTLE>();
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m_sp_cache = space(AS_DATA).cache<0, 0, ENDIANNESS_LITTLE>();
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set_icountptr(m_icount);
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@ -71,28 +80,146 @@ void rx01_cpu_device::device_start()
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// Save state registration
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save_item(NAME(m_pc));
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save_item(NAME(m_ppc));
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save_item(NAME(m_mb));
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save_item(NAME(m_br_condition));
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save_item(NAME(m_inst_disable));
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save_item(NAME(m_inst_repeat));
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save_item(NAME(m_cntr));
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save_item(NAME(m_sr));
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save_item(NAME(m_spar));
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save_item(NAME(m_bar));
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save_item(NAME(m_crc));
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save_item(NAME(m_flag));
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}
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void rx01_cpu_device::device_reset()
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{
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// Clear address registers, counters and flags
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m_pc = 0;
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m_mb = 0;
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m_inst_disable = false;
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m_inst_repeat = false;
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m_bar = 0;
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m_cntr = 0;
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m_sr = 0;
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m_spar = 0;
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m_flag = false;
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}
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u8 rx01_cpu_device::mux_out()
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{
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return BIT(m_mb, 0) ? m_sp_cache->read_byte(m_spar) : m_inst_cache->read_byte(m_pc);
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}
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bool rx01_cpu_device::test_condition()
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{
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switch (m_mb & 074)
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{
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case 020:
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return BIT(m_sr, 7);
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case 024:
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return m_cntr == 0377;
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case 030:
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return BIT(m_crc, 0);
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case 074:
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return m_flag;
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default:
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LOG("%04o: Unhandled branch condition %d\n", m_ppc, (m_mb & 074) >> 2);
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return true;
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}
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}
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void rx01_cpu_device::execute_run()
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{
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// TODO
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debugger_instruction_hook(m_pc);
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m_icount = 0;
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while (m_icount > 0)
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{
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if (m_inst_disable)
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{
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if ((m_mb & 0302) == 0202)
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m_pc = u16(m_mb & 074) << 6 | mux_out();
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else if (BIT(m_mb, 6) && m_br_condition)
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m_pc = ((m_pc + 1) & 07400) | mux_out();
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else
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m_pc = (m_pc + 1) & 07777;
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m_inst_disable = false;
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m_inst_repeat = false;
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}
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else
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{
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if (!m_inst_repeat)
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{
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m_ppc = m_pc;
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debugger_instruction_hook(m_pc);
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m_mb = m_inst_cache->read_byte(m_pc);
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m_pc = (m_pc + 1) & 03777;
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}
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if (BIT(m_mb, 6))
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{
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m_br_condition = test_condition() == BIT(m_mb, 1);
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if (BIT(m_mb, 7))
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{
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m_inst_disable = m_cntr == 0377 || m_br_condition;
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m_inst_repeat = m_cntr != 0377 && !m_br_condition;
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m_cntr++;
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}
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else
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m_inst_disable = true;
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}
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else if (BIT(m_mb, 7))
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{
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if (BIT(m_mb, 1))
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m_inst_disable = true;
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else
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m_spar = (m_mb & 074) >> 2;
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}
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else switch (m_mb & 074)
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{
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case 044:
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if (BIT(m_mb, 1))
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m_bar = (m_bar + 1) & 07777;
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else
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m_bar = BIT(m_mb, 0) ? 0 : 06000;
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break;
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case 060:
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m_flag = (!BIT(m_mb, 0) && m_flag) || (BIT(m_mb, 1) && !m_flag);
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break;
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case 064:
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m_sp_cache->write_byte(m_spar, m_sr);
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break;
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case 070:
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if (BIT(m_mb, 1))
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m_cntr++;
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else
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m_cntr = mux_out();
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m_inst_disable = !BIT(m_mb, 0);
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break;
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case 074:
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if ((m_mb & 3) == 1)
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m_sr = m_cntr;
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else
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m_sr = (m_sr << 1) | (BIT(m_mb, 0) ? 0 /*sep_data()*/ : BIT(m_mb, 1));
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break;
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default:
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LOG("%04o: Unimplemented instruction %03o\n", m_ppc, m_mb);
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break;
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}
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}
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m_icount--;
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}
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}
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void rx01_cpu_device::state_string_export(const device_state_entry &entry, std::string &str) const
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@ -27,6 +27,8 @@ protected:
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virtual void device_reset() override;
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// device_execute_interface overrides
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virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 4 - 1) / 4; }
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virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 4); }
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virtual void execute_run() override;
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// device_disasm_interface overrides
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@ -41,19 +43,29 @@ protected:
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private:
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void scratchpad_map(address_map &map);
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// internal helpers
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u8 mux_out();
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bool test_condition();
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// address spaces
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address_space_config m_rom_config;
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address_space_config m_inst_config;
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address_space_config m_sp_config;
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memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_rom_cache;
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memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_inst_cache;
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memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_sp_cache;
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// internal state
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u16 m_pc;
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u16 m_ppc;
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u8 m_mb;
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bool m_br_condition;
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bool m_inst_disable;
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bool m_inst_repeat;
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u8 m_cntr;
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u8 m_sr;
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u8 m_spar;
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u16 m_bar;
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u16 m_crc;
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bool m_flag;
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s32 m_icount;
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};
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