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upd1771: Very small documentation update. no whatsnew.
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@ -80,8 +80,8 @@
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L -> selector of left or right half of the ram word
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?bits:
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D (having to do with the DAC)
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N (having to do with the pseudorandom noise interrupt, namely setting the clock divider ratio for the PRNG clock vs cpu clock)
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MODE (enabling/disabling/acking the noise interrupt, and the tone interrupts (there are four!))
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N (3 bits? having to do with the pseudorandom noise interrupt, namely setting the clock divider ratio for the PRNG clock vs cpu clock)
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MODE (5 or more bits? enabling/disabling/acking the noise interrupt, and the tone interrupts (there are four!))
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SP (the stack pointer, probably 5 bits, points to the stack ram; may encompass H and L as above!)
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FLO: unsure. quite possibly 'flag overflow' used for branching. there likely exists other flags as well...
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ODF: 'output data flag?', selects which half of a selected ram word is output to the dac not really sure of this?
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@ -145,8 +145,7 @@
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(NOTE: the photomicrograph in the bristow book makes it fairly clear due to
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pad thicknessess that the real VCC is pin 8 and the real GND is pin 14.
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Pins 16 and 17 are some sort of ?mode? inputs but could be the /EXTINT pin too?
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Pin 15 MIGHT be the reset pin or could be a TEST pin. RESET could also be pin 7.)
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The function of pin 7 is unknown.
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Pins 11 and 13 go to a special circuit, which according to kevtris's analysis
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of my schematics, consist of a balanced output (not unlike XLR cables),
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