mirror of
https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
swtpc09: add hard disk support for the DMAF3 controller
This uses the WD1000 driver. The DMAF2/3 6844 DMA support had to be improved to support multiple channels, and now supports a separate high addresses for each channel. It now also support addresses increasing or decreasing. These controllers use different DMA channels for the floppy and the hard disk, and also a tape archiver which is not yet implemented. This gets UniFLEX running using a hard disk for storage, and does not appear to regress the floppy support or other variants using the DMAF2.
This commit is contained in:
68bit
parent
ae4a4581bc
commit
27d2ae2cf6
@ -470,10 +470,7 @@ WRITE8_MEMBER( wd1000_device::write )
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// bit 6,5 : sector size (0: 256, 1: 512, 3: 128)
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// bit 4,3 : drive select (0,1,2,3)
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// bit 2,1,0: head select (0-7)
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uint8_t ecc = BIT(data, 7);
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uint8_t sec_size = (data & 0x60) >> 5;
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uint8_t drive = (data & 0x18) >> 3;
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uint8_t head = data & 0x7;
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m_sdh = data;
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// Update the drive ready flag in the status register which
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@ -564,7 +561,6 @@ void wd1000_device::cmd_restore()
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void wd1000_device::cmd_read_sector()
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{
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hard_disk_file *file = m_drives[drive()].drive->get_hard_disk_file();
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hard_disk_info *info = hard_disk_get_info(file);
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uint8_t dma = BIT(m_command, 3);
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hard_disk_read(file, get_lbasector(), m_buffer);
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@ -26,7 +26,6 @@
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#include "emu.h"
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#include "includes/swtpc09.h"
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#include "bus/ss50/interface.h"
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#include "machine/input_merger.h"
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#include "formats/flex_dsk.h"
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#include "formats/uniflex_dsk.h"
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@ -49,7 +48,7 @@
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F000 - F01F DMAF2 MC6844 DMAC
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F020 - F023 DMAF2 WD1791 FDC
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F024 - F03F DMAF2 Drive select register
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F040 - F041 DMAF2 DMA Address register
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F040 - F041 DMAF2 DMA Address register, and interrupt enable, latch.
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F800 - FFFF ROM
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FFF0 - FFFF DAT RAM (only for writes)
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@ -59,9 +58,17 @@
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F000 - F01F DMAF3 MC6844 DMAC
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F020 - F023 DMAF3 WD1791 FDC
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F024 - F024 DMAF3 Drive select register
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F025 - F025 DMAF3 DMA Address register
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F030 - F03F DMAF3 WD1000
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F040 - F04F DMAF3 6522 VIA
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F025 - F025 DMAF3 74LS374 latch for 4 extended address lines (bits 0-3), DMA.
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F030 - F03F DMAF3 HDC WD1000
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F040 - F04F DMAF3 VIA6522
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F050 - F050 DMAF3 HDC head load toggle
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F051 - F051 DMAF3 Winchester software reset
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F052 - F052 DMAF3 Archive reset
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F053 - F053 DMAF3 Archive clear
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F060 - ???? DMAF3 archive DMA preset
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F100 - ???? CDS disk 0 controller
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F300 - ???? CDS disk 1 controller
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***************************************************************************/
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@ -92,10 +99,12 @@ void swtpc09_state::flex_dmaf2_mem(address_map &map)
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// MPID
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map(0xfe080, 0xfe083).mirror(0xc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write));
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map(0xfe090, 0xfe097).mirror(0x8).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write));
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// DMAF2
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map(0xff000, 0xff01f).rw(FUNC(swtpc09_state::m6844_r), FUNC(swtpc09_state::m6844_w));
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map(0xff020, 0xff023).rw(FUNC(swtpc09_state::dmaf2_fdc_r), FUNC(swtpc09_state::dmaf2_fdc_w));
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map(0xff024, 0xff03f).rw(FUNC(swtpc09_state::dmaf2_control_reg_r), FUNC(swtpc09_state::dmaf2_control_reg_w));
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map(0xff040, 0xff040).rw(FUNC(swtpc09_state::dmaf2_dma_address_reg_r), FUNC(swtpc09_state::dmaf2_dma_address_reg_w));
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map(0xff800, 0xfffff).rom().region("bankdev", 0xff800);
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}
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@ -178,10 +187,12 @@ void swtpc09_state::uniflex_dmaf3_mem(address_map &map)
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map(0xff020, 0xff023).rw(FUNC(swtpc09_state::dmaf3_fdc_r), FUNC(swtpc09_state::dmaf3_fdc_w));
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map(0xff024, 0xff024).rw(FUNC(swtpc09_state::dmaf3_control_reg_r), FUNC(swtpc09_state::dmaf3_control_reg_w));
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map(0xff025, 0xff025).rw(FUNC(swtpc09_state::dmaf3_dma_address_reg_r), FUNC(swtpc09_state::dmaf3_dma_address_reg_w));
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map(0xff030, 0xff03f).rw(m_hdc, FUNC(wd1000_device::read), FUNC(wd1000_device::write));
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map(0xff040, 0xff04f).m(m_via, FUNC(via6522_device::map));
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// DMAF3 WD1000
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map(0xff030, 0xff03f).rw(FUNC(swtpc09_state::dmaf3_wd_r), FUNC(swtpc09_state::dmaf3_wd_w));
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map(0xff050, 0xff050).rw(FUNC(swtpc09_state::dmaf3_hdc_control_r), FUNC(swtpc09_state::dmaf3_hdc_control_w));
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map(0xff051, 0xff051).rw(FUNC(swtpc09_state::dmaf3_hdc_reset_r), FUNC(swtpc09_state::dmaf3_hdc_reset_w));
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map(0xff052, 0xff052).rw(FUNC(swtpc09_state::dmaf3_archive_reset_r), FUNC(swtpc09_state::dmaf3_archive_reset_w));
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map(0xff053, 0xff053).rw(FUNC(swtpc09_state::dmaf3_archive_clear_r), FUNC(swtpc09_state::dmaf3_archive_clear_w));
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map(0xff800, 0xfffff).rom().region("bankdev", 0xff800);
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}
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@ -506,12 +517,25 @@ void swtpc09_state::swtpc09d3(machine_config &config)
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m_fdc->drq_wr_callback().set(FUNC(swtpc09_state::fdc_drq_w));
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m_fdc->sso_wr_callback().set(FUNC(swtpc09_state::fdc_sso_w));
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// Hard disk
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WD1000(config, m_hdc, 5_MHz_XTAL);
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m_hdc->intrq_wr_callback().set(FUNC(swtpc09_state::dmaf3_hdc_intrq_w));
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m_hdc->drq_wr_callback().set(FUNC(swtpc09_state::dmaf3_hdc_drq_w));
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HARDDISK(config, "hdc:0", 0);
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HARDDISK(config, "hdc:1", 0);
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HARDDISK(config, "hdc:2", 0);
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HARDDISK(config, "hdc:3", 0);
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via6522_device &via(VIA6522(config, "via", 4_MHz_XTAL / 4));
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via.readpa_handler().set(FUNC(swtpc09_state::dmaf3_via_read_porta));
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via.readpb_handler().set(FUNC(swtpc09_state::dmaf3_via_read_portb));
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via.writepa_handler().set(FUNC(swtpc09_state::dmaf3_via_write_porta));
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via.writepb_handler().set(FUNC(swtpc09_state::dmaf3_via_write_portb));
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//via.ca1_handler().set(FUNC(swtpc09_state::dmaf3_via_write_ca1));
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via.irq_handler().set(FUNC(swtpc09_state::dmaf3_via_irq));
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INPUT_MERGER_ALL_HIGH(config, "via_cb2").output_handler().set(m_via, FUNC(via6522_device::write_cb2));
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}
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@ -18,7 +18,9 @@
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#include "machine/6840ptm.h"
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#include "machine/6821pia.h"
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#include "machine/6522via.h"
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#include "machine/input_merger.h"
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#include "imagedev/harddriv.h"
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#include "machine/wd1000.h"
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#include "machine/bankdev.h"
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#include "machine/mc14411.h"
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@ -37,7 +39,9 @@ public:
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, m_floppy1(*this, "fdc:1")
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, m_floppy2(*this, "fdc:2")
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, m_floppy3(*this, "fdc:3")
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, m_hdc(*this, "hdc")
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, m_via(*this, "via")
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, m_via_cb2(*this, "via_cb2")
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, m_dat(*this, "dat")
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, m_bankdev(*this, "bankdev")
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, m_maincpu_clock(*this, "maincpu_clock")
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@ -82,6 +86,7 @@ private:
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DECLARE_READ8_MEMBER( dmaf3_via_read_porta );
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DECLARE_READ8_MEMBER( dmaf3_via_read_portb );
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DECLARE_WRITE8_MEMBER( dmaf3_via_write_porta );
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DECLARE_WRITE8_MEMBER( dmaf3_via_write_portb );
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DECLARE_WRITE_LINE_MEMBER( dmaf3_via_irq );
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TIMER_CALLBACK_MEMBER(floppy_motor_callback);
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@ -100,8 +105,16 @@ private:
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DECLARE_READ8_MEMBER ( dmaf3_control_reg_r );
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DECLARE_WRITE8_MEMBER ( dmaf3_control_reg_w );
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DECLARE_READ8_MEMBER( dmaf3_wd_r );
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DECLARE_WRITE8_MEMBER( dmaf3_wd_w );
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DECLARE_WRITE_LINE_MEMBER(dmaf3_hdc_intrq_w);
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DECLARE_WRITE_LINE_MEMBER( dmaf3_hdc_drq_w );
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DECLARE_READ8_MEMBER( dmaf3_hdc_control_r );
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DECLARE_WRITE8_MEMBER( dmaf3_hdc_control_w );
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DECLARE_READ8_MEMBER( dmaf3_hdc_reset_r );
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DECLARE_WRITE8_MEMBER( dmaf3_hdc_reset_w );
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DECLARE_READ8_MEMBER( dmaf3_archive_reset_r );
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DECLARE_WRITE8_MEMBER( dmaf3_archive_reset_w );
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DECLARE_READ8_MEMBER( dmaf3_archive_clear_r );
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DECLARE_WRITE8_MEMBER( dmaf3_archive_clear_w );
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DECLARE_WRITE8_MEMBER(dat_w);
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DECLARE_READ8_MEMBER(main_r);
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@ -122,7 +135,6 @@ private:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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void swtpc09_fdc_dma_transfer();
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void swtpc09_irq_handler(uint8_t peripheral, uint8_t state);
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void floppy_motor_trigger();
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@ -144,7 +156,10 @@ private:
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optional_device<floppy_connector> m_floppy2;
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optional_device<floppy_connector> m_floppy3;
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optional_device<wd1000_device> m_hdc;
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optional_device<via6522_device> m_via;
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optional_device<input_merger_device> m_via_cb2;
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required_shared_ptr<uint8_t> m_dat;
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required_device<address_map_bank_device> m_bankdev;
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required_ioport m_maincpu_clock;
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@ -158,15 +173,17 @@ private:
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uint8_t m_pia_counter; // this is the counter on pia porta
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uint8_t m_fdc_dma_address_reg; // dmaf2 or dmaf3 dma extended address reg
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uint8_t m_dmaf_high_address[4]; // dmaf2 or dmaf3 dma extended address reg
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uint8_t m_dmaf2_interrupt_enable;
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uint8_t m_system_type; // flag to indicate hw and rom combination
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uint8_t m_fdc_status; // for floppy controller
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int m_floppy_motor_on;
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emu_timer *m_floppy_motor_timer;
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floppy_image_device *m_fdc_floppy; // Current selected floppy.
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uint8_t m_fdc_side; // Current floppy side.
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uint8_t m_via_ca1_input; // dmaf3 fdc interrupt is connected here
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uint8_t m_dmaf3_via_porta;
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uint8_t m_dmaf3_via_portb;
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uint8_t m_active_interrupt;
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uint8_t m_interrupt;
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@ -180,6 +197,20 @@ private:
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int active;
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int address;
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int counter;
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// Channel control register.
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// bit 0: Read / Write mode
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// bit 1: Mode control B
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// bit 2: Mode control A
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// bit 3: Address up (0) / down (1).
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// bit 4: Not used
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// bit 5: Not used
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// bit 6: Busy / Ready. Read only. Set when request
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// made. Cleared when transfer completed.
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// bit 7: DMA end flag. Read only? Set when transfer
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// completed. Cleared when control register
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// read. Sets IRQ.
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// Mode control A,B: 0,0 Mode2; 0,1 Mode 3; 1,0 Mode 0;
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// 1,1 Undefined.
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uint8_t control;
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int start_address;
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int start_counter;
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@ -188,8 +219,17 @@ private:
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/* 6844 description */
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m6844_channel_data m_m6844_channel[4];
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uint8_t m_m6844_priority;
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// Interrupt control register.
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// Bit 0-3: channel interrupt enable, 1 enabled, 0 masked.
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// Bit 4-6: unused
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// Bit 7: Read only. Set to 1 when IRQ asserted. Clear when the
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// control register associated with the channel that caused the
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// interrut is read.
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uint8_t m_m6844_interrupt;
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uint8_t m_m6844_chain;
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void m6844_update_interrupt();
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void m6844_fdc_dma_transfer(uint8_t channel);
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void m6844_hdc_dma_transfer(uint8_t channel);
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};
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#endif // MAME_INCLUDES_SWTPC09_H
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@ -227,8 +227,6 @@ WRITE8_MEMBER ( swtpc09_state::dmaf2_fdc_w )
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// TODO Does access to the dmaf2 fdc also trigger the motor timer.
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floppy_motor_trigger();
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// TODO how does the DMAF2 use the FDC SSO output?
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if (offset == 0) {
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validate_floppy_side(data);
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data = validate_fdc_sector_size(data);
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@ -237,24 +235,37 @@ WRITE8_MEMBER ( swtpc09_state::dmaf2_fdc_w )
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m_fdc->fd1797_device::write(offset, data);
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}
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/* DMAF2 dma extended address register */
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/* DMAF2 dma extended address register latch. */
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READ8_MEMBER ( swtpc09_state::dmaf2_dma_address_reg_r )
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{
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return m_fdc_dma_address_reg;
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// This does not appear to be readable.
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logerror("%s Unexpected read of DMAF2 DMA address reg\n", machine().describe_context());
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return 0x00;
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}
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WRITE8_MEMBER ( swtpc09_state::dmaf2_dma_address_reg_w )
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{
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m_fdc_dma_address_reg = data;
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// This latch appears to be write-only, there is no reader function.
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// The DMAF2 has a single latch for the high address bits, so it would
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// appear to apply for all DMA channels. These outputs are inverted
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// which cancels the inversion of the data lines.
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m_dmaf_high_address[0] = data & 0x0f;
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m_dmaf_high_address[1] = data & 0x0f;
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m_dmaf_high_address[2] = data & 0x0f;
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m_dmaf_high_address[3] = data & 0x0f;
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// bit 4 controls a gate enable/disable for DMAF2 fdc irq line
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if ((m_fdc_dma_address_reg & 0x10) && (m_system_type == UNIFLEX_DMAF2 || m_system_type == FLEX_DMAF2))
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m_dmaf2_interrupt_enable = !BIT(data, 4);
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if (!m_dmaf2_interrupt_enable)
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swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); //then clear the irq to cpu
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}
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/* DMAF2 fdc control register */
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READ8_MEMBER ( swtpc09_state::dmaf2_control_reg_r )
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{
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// TODO is this readable?
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logerror("%s Unexpected read from DMAF2 control reg\n", machine().describe_context());
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return m_fdc_status;
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}
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@ -262,71 +273,33 @@ WRITE8_MEMBER ( swtpc09_state::dmaf2_control_reg_w )
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{
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floppy_image_device *floppy = nullptr;
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// TODO what to do if multiple drives are selected?
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if (!BIT(data, 0) + !BIT(data, 1) + !BIT(data, 2) + !BIT(data, 3) > 1)
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{
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logerror("%s Unexpected DMAF2 has multiple drives selected: %d %d %d %d\n", machine().describe_context(), !BIT(data, 0), !BIT(data, 1), !BIT(data, 2), !BIT(data, 3));
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}
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// The DMAF2 data lines are inverted.
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data = ~data & 0xff;
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if (!BIT(data, 0)) floppy = m_floppy0->get_device();
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if (!BIT(data, 1)) floppy = m_floppy1->get_device();
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if (!BIT(data, 2)) floppy = m_floppy2->get_device();
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if (!BIT(data, 3)) floppy = m_floppy3->get_device();
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// TODO what to do if multiple drives are selected?
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if (BIT(data, 0) + BIT(data, 1) + BIT(data, 2) + BIT(data, 3) > 1)
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logerror("%s Unexpected DMAF2 has multiple drives selected: %d %d %d %d\n", machine().describe_context(), BIT(data, 0), BIT(data, 1), BIT(data, 2), BIT(data, 3));
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if (BIT(data, 0)) floppy = m_floppy0->get_device();
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if (BIT(data, 1)) floppy = m_floppy1->get_device();
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if (BIT(data, 2)) floppy = m_floppy2->get_device();
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if (BIT(data, 3)) floppy = m_floppy3->get_device();
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m_fdc->set_floppy(floppy);
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m_fdc_floppy = floppy;
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if (floppy)
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{
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uint8_t side = !BIT(data, 4);
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uint8_t side = BIT(data, 4);
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floppy->ss_w(side);
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m_fdc_side = side;
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}
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uint8_t dden = !BIT(data, 5);
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uint8_t dden = BIT(data, 5);
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dden = validate_fdc_dden(dden);
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m_fdc->dden_w(dden);
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}
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/* FDC controller dma transfer */
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void swtpc09_state::swtpc09_fdc_dma_transfer()
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{
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uint32_t offset;
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address_space &space = *m_banked_space;
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offset = (m_fdc_dma_address_reg & 0x0f)<<16;
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if (m_m6844_channel[0].active == 1) //active dma transfer
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{
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if (!(m_m6844_channel[0].control & 0x01)) // dma write to memory
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{
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uint8_t data = m_fdc->data_r();
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space.write_byte(m_m6844_channel[0].address + offset, data);
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}
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else
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{
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uint8_t data = space.read_byte(m_m6844_channel[0].address + offset);
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|
||||
m_fdc->data_w(data);
|
||||
}
|
||||
|
||||
m_m6844_channel[0].address++;
|
||||
m_m6844_channel[0].counter--;
|
||||
|
||||
if (m_m6844_channel[0].counter == 0) // dma transfer has finished
|
||||
{
|
||||
m_m6844_channel[0].control |= 0x80; // set dend flag
|
||||
if (m_m6844_interrupt & 0x01) // interrupt for channel 0 is enabled?
|
||||
{
|
||||
m_m6844_interrupt |= 0x80; // set bit 7 to indicate active interrupt
|
||||
swtpc09_irq_handler(DMAC_IRQ, ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* common interrupt handler */
|
||||
void swtpc09_state::swtpc09_irq_handler(uint8_t peripheral, uint8_t state)
|
||||
{
|
||||
@ -356,22 +329,26 @@ void swtpc09_state::swtpc09_irq_handler(uint8_t peripheral, uint8_t state)
|
||||
/* handlers for fdc */
|
||||
WRITE_LINE_MEMBER( swtpc09_state::fdc_intrq_w )
|
||||
{
|
||||
if ( m_system_type == UNIFLEX_DMAF3 ) //IRQ from 1791 is connect into VIA ca2
|
||||
if ( m_system_type == UNIFLEX_DMAF3 )
|
||||
{
|
||||
// IRQ from 1791 is connected into VIA CB2 inverted, and
|
||||
// connected to VIA port B bit 2 without inversion.
|
||||
if (state)
|
||||
{
|
||||
m_fdc_status |= 0x40;
|
||||
m_via->write_cb2(0); //fdc interrupt is connected to CA1
|
||||
m_dmaf3_via_porta &= 0xfb; //clear pa3
|
||||
//m_via->write_porta(m_dmaf3_via_porta); //and connected to PA3
|
||||
//m_via->write_cb2(0);
|
||||
m_via_cb2->in_w<0>(0);
|
||||
m_dmaf3_via_portb |= 0x04;
|
||||
//m_via->write_portb(m_dmaf3_via_portb);
|
||||
//swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_fdc_status &= ~0x40;
|
||||
m_via->write_cb2(1);
|
||||
m_dmaf3_via_porta |= 0x04; //and connected to PA3
|
||||
//m_via->write_porta(m_dmaf3_via_porta); //and connected to PA3
|
||||
//m_via->write_cb2(1);
|
||||
m_via_cb2->in_w<0>(1);
|
||||
m_dmaf3_via_portb &= 0xfb;
|
||||
//m_via->write_portb(m_dmaf3_via_portb);
|
||||
//swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
@ -380,7 +357,7 @@ WRITE_LINE_MEMBER( swtpc09_state::fdc_intrq_w )
|
||||
if (state)
|
||||
{
|
||||
m_fdc_status |= 0x40;
|
||||
if (!(m_fdc_dma_address_reg & 0x10)) // is dmaf2 fdc irq enabled
|
||||
if (m_dmaf2_interrupt_enable)
|
||||
{
|
||||
swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
|
||||
}
|
||||
@ -388,7 +365,7 @@ WRITE_LINE_MEMBER( swtpc09_state::fdc_intrq_w )
|
||||
else
|
||||
{
|
||||
m_fdc_status &= ~0x40;
|
||||
if (!(m_fdc_dma_address_reg & 0x10)) // is dmaf2 fdc irq enabled
|
||||
if (m_dmaf2_interrupt_enable)
|
||||
{
|
||||
swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
|
||||
}
|
||||
@ -401,7 +378,9 @@ WRITE_LINE_MEMBER( swtpc09_state::fdc_drq_w )
|
||||
if (state)
|
||||
{
|
||||
m_fdc_status |= 0x80;
|
||||
swtpc09_fdc_dma_transfer();
|
||||
// The DMAF2 schematic shows an input to two pins on the 6844,
|
||||
// it might also trigger channel 1.
|
||||
m6844_fdc_dma_transfer(0);
|
||||
}
|
||||
else
|
||||
m_fdc_status &= 0x7f;
|
||||
@ -409,7 +388,7 @@ WRITE_LINE_MEMBER( swtpc09_state::fdc_drq_w )
|
||||
|
||||
WRITE_LINE_MEMBER( swtpc09_state::fdc_sso_w )
|
||||
{
|
||||
// Doese the DMAF2 or DMAF3 use the SSO output?
|
||||
// The DMAF2 and DMAF3 do not appear to use a SSO output?
|
||||
}
|
||||
|
||||
/*********************************************************************/
|
||||
@ -445,7 +424,18 @@ READ8_MEMBER( swtpc09_state::dmaf3_via_read_porta )
|
||||
|
||||
READ8_MEMBER( swtpc09_state::dmaf3_via_read_portb )
|
||||
{
|
||||
return 0xff;
|
||||
// Bit 0 - output ?
|
||||
// Bit 1 - output, tape drive request strobe.
|
||||
// Bit 2 - input, WD1791 FDC interrupt.
|
||||
// Bit 3 - input ?
|
||||
// Bit 4 - input, tape drive ready
|
||||
// Bit 5 - input, tape drive exception, timer 2.
|
||||
// Bit 6 - input ?
|
||||
// Bit 7 - output, UniFLEX configures a timer to toggle this output.
|
||||
|
||||
// Set the tape drive exception bit to avoid detection, otherwise
|
||||
// UniFLEX gets stuck in a loop trying to open the archive driver.
|
||||
return m_dmaf3_via_portb | 0x20;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( swtpc09_state::dmaf3_via_write_porta )
|
||||
@ -453,6 +443,11 @@ WRITE8_MEMBER( swtpc09_state::dmaf3_via_write_porta )
|
||||
m_dmaf3_via_porta &= data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( swtpc09_state::dmaf3_via_write_portb )
|
||||
{
|
||||
m_dmaf3_via_portb &= data;
|
||||
}
|
||||
|
||||
//WRITE_LINE_MEMBER( swtpc09_state::dmaf3_via_write_ca1 )
|
||||
//{
|
||||
// return m_via_ca1_input;
|
||||
@ -471,17 +466,28 @@ WRITE_LINE_MEMBER( swtpc09_state::dmaf3_via_irq )
|
||||
/* DMAF3 dma extended address register */
|
||||
READ8_MEMBER ( swtpc09_state::dmaf3_dma_address_reg_r )
|
||||
{
|
||||
return m_fdc_dma_address_reg;
|
||||
// TODO is this readable?
|
||||
logerror("%s Unexpected read of DMAF3 DMA address reg\n", machine().describe_context());
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER ( swtpc09_state::dmaf3_dma_address_reg_w )
|
||||
{
|
||||
m_fdc_dma_address_reg = data;
|
||||
// Based on source code comments it appears that there are four high
|
||||
// address latches, one for each DMA channel. TODO check hardware or a
|
||||
// schematic.
|
||||
uint8_t channel = (data & 0x30) >> 4;
|
||||
m_dmaf_high_address[channel] = data & 0x0f;
|
||||
|
||||
// Bit 6 controls the 'archive edge select'.
|
||||
// Bit 7 controls the DMA halt versus bus-req mode.
|
||||
}
|
||||
|
||||
/* DMAF3 fdc control register */
|
||||
READ8_MEMBER ( swtpc09_state::dmaf3_control_reg_r )
|
||||
{
|
||||
// TODO is this readable?
|
||||
logerror("%s Unexpected read from DMAF3 control reg\n", machine().describe_context());
|
||||
return m_fdc_status;
|
||||
}
|
||||
|
||||
@ -491,9 +497,7 @@ WRITE8_MEMBER ( swtpc09_state::dmaf3_control_reg_w )
|
||||
|
||||
// TODO multiple selected?
|
||||
if (BIT(data, 0) + BIT(data, 1) + BIT(data, 2) + BIT(data, 3) > 1)
|
||||
{
|
||||
logerror("%s Unexpected DMAF3 has multiple drives selected: %d %d %d %d\n", machine().describe_context(), !BIT(data, 0), !BIT(data, 1), !BIT(data, 2), !BIT(data, 3));
|
||||
}
|
||||
logerror("%s Unexpected DMAF3 has multiple drives selected: %d %d %d %d\n", machine().describe_context(), BIT(data, 0), BIT(data, 1), BIT(data, 2), BIT(data, 3));
|
||||
|
||||
if (BIT(data, 0)) floppy = m_floppy0->get_device();
|
||||
if (BIT(data, 1)) floppy = m_floppy1->get_device();
|
||||
@ -515,17 +519,74 @@ WRITE8_MEMBER ( swtpc09_state::dmaf3_control_reg_w )
|
||||
m_fdc->dden_w(dden);
|
||||
}
|
||||
|
||||
// DMAF3 WD1000
|
||||
// TODO. The following might help:
|
||||
// http://www.bitsavers.org/pdf/westernDigital/WD100x/WD1000_OEM_Manual.pdf
|
||||
// DMAF3 WD1000 hard disk controller.
|
||||
|
||||
READ8_MEMBER( swtpc09_state::dmaf3_wd_r )
|
||||
WRITE_LINE_MEMBER( swtpc09_state::dmaf3_hdc_intrq_w )
|
||||
{
|
||||
return 0x00;
|
||||
// The IRQ from WD1000 is connected into VIA CB2 inverted, and perhaps
|
||||
// connected to a VIA port B bit 3?
|
||||
if (state)
|
||||
{
|
||||
m_via_cb2->in_w<1>(0);
|
||||
//m_dmaf3_via_portb &= 0xf7;
|
||||
//m_via->write_portb(m_dmaf3_via_portb);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_via_cb2->in_w<1>(1);
|
||||
//m_dmaf3_via_portb |= 0x08;
|
||||
//m_via->write_portb(m_dmaf3_via_portb);
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER ( swtpc09_state::dmaf3_wd_w )
|
||||
WRITE_LINE_MEMBER( swtpc09_state::dmaf3_hdc_drq_w )
|
||||
{
|
||||
if (state)
|
||||
m6844_hdc_dma_transfer(1);
|
||||
}
|
||||
|
||||
READ8_MEMBER( swtpc09_state::dmaf3_hdc_control_r )
|
||||
{
|
||||
// TODO head load toggle?
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER ( swtpc09_state::dmaf3_hdc_control_w )
|
||||
{
|
||||
// TODO head load toggle?
|
||||
}
|
||||
|
||||
READ8_MEMBER( swtpc09_state::dmaf3_hdc_reset_r )
|
||||
{
|
||||
// TODO reset?
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER ( swtpc09_state::dmaf3_hdc_reset_w )
|
||||
{
|
||||
// TODO reset
|
||||
}
|
||||
|
||||
READ8_MEMBER( swtpc09_state::dmaf3_archive_reset_r )
|
||||
{
|
||||
// TODO
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER ( swtpc09_state::dmaf3_archive_reset_w )
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
READ8_MEMBER( swtpc09_state::dmaf3_archive_clear_r )
|
||||
{
|
||||
// TODO
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER ( swtpc09_state::dmaf3_archive_clear_w )
|
||||
{
|
||||
// TODO
|
||||
}
|
||||
|
||||
|
||||
@ -566,6 +627,110 @@ WRITE8_MEMBER(swtpc09_state::main_w)
|
||||
|
||||
/* MC6844 DMA controller I/O */
|
||||
|
||||
|
||||
void swtpc09_state::m6844_update_interrupt()
|
||||
{
|
||||
uint8_t interrupt = 0;
|
||||
|
||||
interrupt |= BIT(m_m6844_channel[0].control, 7) & BIT(m_m6844_interrupt, 0);
|
||||
interrupt |= BIT(m_m6844_channel[1].control, 7) & BIT(m_m6844_interrupt, 1);
|
||||
interrupt |= BIT(m_m6844_channel[2].control, 7) & BIT(m_m6844_interrupt, 2);
|
||||
interrupt |= BIT(m_m6844_channel[3].control, 7) & BIT(m_m6844_interrupt, 3);
|
||||
|
||||
if (interrupt)
|
||||
{
|
||||
if (!(m_m6844_interrupt & 0x80))
|
||||
{
|
||||
// Set interrupt indication bit 7.
|
||||
m_m6844_interrupt |= 0x80;
|
||||
swtpc09_irq_handler(DMAC_IRQ, ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (m_m6844_interrupt & 0x80)
|
||||
{
|
||||
// Clear interrupt indication bit 7.
|
||||
m_m6844_interrupt &= 0x7f;
|
||||
swtpc09_irq_handler(DMAC_IRQ, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void swtpc09_state::m6844_fdc_dma_transfer(uint8_t channel)
|
||||
{
|
||||
uint32_t offset;
|
||||
address_space &space = *m_banked_space;
|
||||
|
||||
offset = m_dmaf_high_address[channel] << 16;
|
||||
|
||||
if (m_m6844_channel[channel].active == 1) //active dma transfer
|
||||
{
|
||||
if (!(m_m6844_channel[channel].control & 0x01)) // dma write to memory
|
||||
{
|
||||
uint8_t data = m_fdc->data_r();
|
||||
|
||||
space.write_byte(m_m6844_channel[channel].address + offset, data);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t data = space.read_byte(m_m6844_channel[channel].address + offset);
|
||||
|
||||
m_fdc->data_w(data);
|
||||
}
|
||||
|
||||
if (m_m6844_channel[channel].control & 0x08)
|
||||
m_m6844_channel[channel].address--;
|
||||
else
|
||||
m_m6844_channel[channel].address++;
|
||||
|
||||
m_m6844_channel[channel].counter--;
|
||||
|
||||
if (m_m6844_channel[channel].counter == 0) // dma transfer has finished
|
||||
{
|
||||
m_m6844_channel[channel].control |= 0x80; // set dend flag
|
||||
m6844_update_interrupt();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void swtpc09_state::m6844_hdc_dma_transfer(uint8_t channel)
|
||||
{
|
||||
uint32_t offset;
|
||||
address_space &space = *m_banked_space;
|
||||
|
||||
offset = m_dmaf_high_address[channel] << 16;
|
||||
|
||||
if (m_m6844_channel[channel].active == 1) //active dma transfer
|
||||
{
|
||||
if (!(m_m6844_channel[channel].control & 0x01)) // dma write to memory
|
||||
{
|
||||
uint8_t data = m_hdc->data_r();
|
||||
|
||||
space.write_byte(m_m6844_channel[channel].address + offset, data);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t data = space.read_byte(m_m6844_channel[channel].address + offset);
|
||||
|
||||
m_hdc->data_w(data);
|
||||
}
|
||||
|
||||
if (m_m6844_channel[channel].control & 0x08)
|
||||
m_m6844_channel[channel].address--;
|
||||
else
|
||||
m_m6844_channel[channel].address++;
|
||||
|
||||
m_m6844_channel[channel].counter--;
|
||||
|
||||
if (m_m6844_channel[channel].counter == 0) // dma transfer has finished
|
||||
{
|
||||
m_m6844_channel[channel].control |= 0x80; // set dend flag
|
||||
m6844_update_interrupt();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( swtpc09_state::m6844_r )
|
||||
{
|
||||
uint8_t result = 0;
|
||||
@ -612,15 +777,13 @@ READ8_MEMBER( swtpc09_state::m6844_r )
|
||||
case 0x13:
|
||||
result = m_m6844_channel[offset - 0x10].control;
|
||||
|
||||
/* a read here clears the DMA end flag */
|
||||
// A read here clears the 'DMA end' flag of the
|
||||
// associated channel.
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
m_m6844_channel[offset - 0x10].control &= ~0x80;
|
||||
if (m_m6844_interrupt & 0x80) // if interrupt is active, then clear
|
||||
{
|
||||
swtpc09_irq_handler(0x01, CLEAR_LINE);
|
||||
m_m6844_interrupt &= 0x7f; // clear interrupt indication bit 7
|
||||
}
|
||||
if (m_m6844_interrupt & 0x80)
|
||||
m6844_update_interrupt();
|
||||
}
|
||||
break;
|
||||
|
||||
@ -742,6 +905,7 @@ WRITE8_MEMBER( swtpc09_state::m6844_w )
|
||||
/* interrupt control */
|
||||
case 0x15:
|
||||
m_m6844_interrupt = (m_m6844_interrupt & 0x80) | (data & 0x7f);
|
||||
m6844_update_interrupt();
|
||||
break;
|
||||
|
||||
/* chaining control */
|
||||
@ -775,6 +939,11 @@ void swtpc09_state::machine_reset()
|
||||
m_brg->rsa_w(baud_rate_high);
|
||||
m_brg->rsb_w(1);
|
||||
|
||||
m_pia->write_portb(0);
|
||||
m_pia->cb1_w(0);
|
||||
m_pia->ca2_w(0);
|
||||
m_pia->cb2_w(0);
|
||||
|
||||
// Note UNIBUG has a smarter boot loader in ROM and will toggle the
|
||||
// density on failure so this is not necessary for UniFLEX.
|
||||
if ((m_system_type == FLEX_DMAF2 ||
|
||||
@ -810,7 +979,12 @@ void swtpc09_state::machine_start()
|
||||
m_fdc_side = 0;
|
||||
|
||||
// Start with the IRQ disabled?
|
||||
m_fdc_dma_address_reg = 0x10;
|
||||
m_dmaf2_interrupt_enable = 0;
|
||||
|
||||
m_dmaf_high_address[0] = 0;
|
||||
m_dmaf_high_address[1] = 0;
|
||||
m_dmaf_high_address[2] = 0;
|
||||
m_dmaf_high_address[3] = 0;
|
||||
|
||||
m_floppy_motor_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(swtpc09_state::floppy_motor_callback),this));
|
||||
m_floppy_motor_on = 0;
|
||||
@ -845,6 +1019,7 @@ void swtpc09_state::init_swtpc09u()
|
||||
|
||||
void swtpc09_state::init_swtpc09d3()
|
||||
{
|
||||
m_via_ca1_input = 0;
|
||||
m_system_type = UNIFLEX_DMAF3;
|
||||
// UniFLEX numbers sectors from 1.
|
||||
m_hdc->set_sector_base(1);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user