mirror of
https://github.com/holub/mame
synced 2025-04-16 13:34:55 +03:00
New skeleton: dvk_kcgd (colour graphics display controller for DVK series)
This commit is contained in:
Sergey Svishchev
parent
ae053d119a
commit
28287d2970
@ -1443,6 +1443,7 @@ files {
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MAME_DIR .. "src/mess/drivers/bk.c",
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MAME_DIR .. "src/mess/machine/bk.c",
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MAME_DIR .. "src/mess/video/bk.c",
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MAME_DIR .. "src/mess/drivers/dvk_kcgd.c",
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MAME_DIR .. "src/mess/drivers/dvk_ksm.c",
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MAME_DIR .. "src/mess/machine/ms7004.c",
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MAME_DIR .. "src/mess/drivers/mk85.c",
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@ -2652,6 +2652,7 @@ itt3030
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vax785
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ms0515
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ie15
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dvk_kcgd
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dvk_ksm
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dvk_ksm01
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asmapro
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384
src/mess/drivers/dvk_kcgd.c
Normal file
384
src/mess/drivers/dvk_kcgd.c
Normal file
@ -0,0 +1,384 @@
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/***************************************************************************
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KCGD (Kontroller Cvetnogo Graficheskogo Displeya = Colour Graphics
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Display Controller), a replacement for KSM (dvk_ksm.c) in later
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models of DVK desktops.
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MPI (Q-Bus clone) board. Interfaces with MS7004 (DEC LK201 workalike)
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keyboard, mouse, and monochrome or color CRT.
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To do:
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- K1801VM2 CPU core (interrupts and EVNT pin, full EIS set, other insns)
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- Everything else :-)
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****************************************************************************/
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#include "emu.h"
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#include "bus/rs232/rs232.h"
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#include "cpu/t11/t11.h"
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#include "machine/clock.h"
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#include "machine/ms7004.h"
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#define KCGD_TOTAL_HORZ 1000 // XXX verify
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#define KCGD_DISP_HORZ 800
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#define KCGD_HORZ_START 200 // XXX verify
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#define KCGD_TOTAL_VERT 600 // XXX verify
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#define KCGD_DISP_VERT 480
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#define KCGD_VERT_START 100 // XXX verify
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#define KCGD_STATUS_PAGE 0
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#define KCGD_STATUS_INTERLACE 1
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#define KCGD_STATUS_TIMER_INT 5
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#define KCGD_STATUS_MODE_INT 6
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#define KCGD_STATUS_MODE_LAST 7
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#define KCGD_STATUS_TIMER_VAL 15
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#define KCGD_PAGE_0 015574
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#define KCGD_PAGE_1 005574
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#define VERBOSE_DBG 1 /* general debug messages */
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#define DBG_LOG(N,M,A) \
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do { \
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if(VERBOSE_DBG>=N) \
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{ \
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if( M ) \
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logerror("%11.6f at %s: %-24s",machine().time().as_double(),machine().describe_context(),(char*)M ); \
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logerror A; \
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} \
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} while (0)
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class kcgd_state : public driver_device
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{
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public:
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kcgd_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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// m_ms7004(*this, "ms7004"),
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m_palette(*this, "palette"),
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m_screen(*this, "screen")
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{ }
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virtual void machine_reset();
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virtual void video_start();
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UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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TIMER_DEVICE_CALLBACK_MEMBER(scanline_callback);
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DECLARE_PALETTE_INIT(kcgd);
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enum
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{
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TIMER_ID_VSYNC_ON,
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TIMER_ID_VSYNC_OFF,
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TIMER_ID_500HZ
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};
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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DECLARE_WRITE_LINE_MEMBER(write_keyboard_clock);
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DECLARE_WRITE_LINE_MEMBER(write_line_clock);
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DECLARE_READ16_MEMBER(vram_addr_r);
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DECLARE_READ16_MEMBER(vram_data_r);
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DECLARE_READ16_MEMBER(vram_mmap_r);
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DECLARE_WRITE16_MEMBER(vram_addr_w);
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DECLARE_WRITE16_MEMBER(vram_data_w);
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DECLARE_WRITE16_MEMBER(vram_mmap_w);
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DECLARE_READ16_MEMBER(status_r);
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DECLARE_WRITE16_MEMBER(status_w);
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DECLARE_READ8_MEMBER(palette_index_r);
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DECLARE_READ8_MEMBER(palette_data_r);
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DECLARE_WRITE8_MEMBER(palette_index_w);
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DECLARE_WRITE8_MEMBER(palette_data_w);
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emu_timer *m_vsync_on_timer;
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emu_timer *m_vsync_off_timer;
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emu_timer *m_500hz_timer;
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private:
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void draw_scanline(UINT16 *p, UINT16 offset);
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rectangle m_tmpclip;
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bitmap_ind16 m_tmpbmp;
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struct {
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UINT16 status; // 167770
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UINT8 control; // 167772
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int palette_index, vram_addr;
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UINT8 palette[16];
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} m_video;
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UINT32 *m_videoram;
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protected:
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required_device<cpu_device> m_maincpu;
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// required_device<ms7004_device> m_ms7004;
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required_device<palette_device> m_palette;
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required_device<screen_device> m_screen;
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};
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static ADDRESS_MAP_START( kcgd_mem, AS_PROGRAM, 16, kcgd_state )
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE (0000000, 0077777) AM_READWRITE(vram_mmap_r, vram_mmap_w)
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AM_RANGE (0100000, 0157777) AM_ROM
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AM_RANGE (0160000, 0160001) AM_MIRROR(03774) AM_READWRITE(vram_addr_r, vram_addr_w)
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AM_RANGE (0160002, 0160003) AM_MIRROR(03774) AM_READWRITE(vram_data_r, vram_data_w)
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AM_RANGE (0167770, 0167771) AM_READWRITE(status_r, status_w)
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AM_RANGE (0167772, 0167773) AM_READWRITE8(palette_index_r, palette_index_w, 0x00ff) // reads always return 0
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AM_RANGE (0167772, 0167773) AM_READWRITE8(palette_data_r, palette_data_w, 0xff00)
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// AM_RANGE (0176560, 0176567) AM_RAM // USART2 -- host
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// AM_RANGE (0177560, 0177567) AM_RAM // USART3 -- keyboard
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ADDRESS_MAP_END
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void kcgd_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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switch (id)
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{
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/*
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case TIMER_ID_VSYNC_ON:
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m_maincpu->set_input_line(INPUT_LINE_EVNT, ASSERT_LINE);
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break;
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case TIMER_ID_VSYNC_OFF:
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m_maincpu->set_input_line(INPUT_LINE_EVNT, CLEAR_LINE);
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break;
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*/
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case TIMER_ID_500HZ:
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m_video.status ^= (1 << KCGD_STATUS_TIMER_VAL);
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break;
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}
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}
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void kcgd_state::machine_reset()
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{
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memset(&m_video, 0, sizeof(m_video));
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}
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void kcgd_state::video_start()
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{
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// screen_device *screen = machine().device<screen_device>("screen");
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// 64 kwords, word size is 17 bits
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m_videoram = auto_alloc_array(machine(), UINT32, 65536);
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m_tmpclip = rectangle(0, KCGD_DISP_HORZ-1, 0, KCGD_DISP_VERT-1);
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m_tmpbmp.allocate(KCGD_DISP_HORZ, KCGD_DISP_VERT);
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/*
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m_vsync_on_timer = timer_alloc(TIMER_ID_VSYNC_ON);
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m_vsync_on_timer->adjust(screen->time_until_pos(0, 0), 0, screen->frame_period());
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m_vsync_off_timer = timer_alloc(TIMER_ID_VSYNC_OFF);
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m_vsync_off_timer->adjust(screen->time_until_pos(16, 0), 0, screen->frame_period());
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*/
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m_500hz_timer = timer_alloc(TIMER_ID_500HZ);
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m_500hz_timer->adjust(attotime::from_hz(500), 0, attotime::from_hz(500));
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}
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PALETTE_INIT_MEMBER(kcgd_state, kcgd)
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{
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for (int i = 0; i < 16; i++)
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{
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palette.set_pen_color(i, i?i:255, i?i:255, i?i:255);
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}
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}
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/*
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VRAM is 128K and is word-addressable, so address fits into 16 bits.
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Low 32K of VRAM are not used to store pixel data -- XXX.
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*/
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WRITE16_MEMBER(kcgd_state::vram_addr_w)
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{
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DBG_LOG(3,"VRAM WA", ("%06o\n", data));
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m_video.vram_addr = data;
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}
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READ16_MEMBER(kcgd_state::vram_addr_r)
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{
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DBG_LOG(3,"VRAM RA", ("\n"));
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return m_video.vram_addr;
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}
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WRITE16_MEMBER(kcgd_state::vram_data_w)
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{
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DBG_LOG(1,"VRAM W2", ("%06o <- %04XH\n", m_video.vram_addr, data));
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m_videoram[m_video.vram_addr] = data | (BIT(m_video.control, 7) << 16);
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}
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READ16_MEMBER(kcgd_state::vram_data_r)
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{
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DBG_LOG(2,"VRAM R2", ("%06o\n", m_video.vram_addr));
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m_video.status = (m_video.status & 0xff7f) | (BIT(m_videoram[m_video.vram_addr], 16) << 7);
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return (UINT16) (m_videoram[m_video.vram_addr] & 0xffff);
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}
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WRITE16_MEMBER(kcgd_state::vram_mmap_w)
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{
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DBG_LOG(3,"VRAM W1", ("%06o <- %04XH\n", offset, data));
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m_videoram[offset] = data | (BIT(m_video.control, 7) << 16);
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}
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READ16_MEMBER(kcgd_state::vram_mmap_r)
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{
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DBG_LOG(3,"VRAM R1", ("%06o\n", offset));
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return (UINT16) (m_videoram[offset] & 0xffff);
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}
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WRITE16_MEMBER(kcgd_state::status_w)
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{
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DBG_LOG(1,"Status W", ("data %04XH (useful %02XH)\n", data, data & 0x63));
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// bits 7 and 15 are read-only
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m_video.status = (m_video.status & 0x8080) | (data & 0x7f7f);
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}
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READ16_MEMBER(kcgd_state::status_r)
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{
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UINT16 data = m_video.status ^ (BIT(m_video.control, 6) << 7);
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DBG_LOG(1,"Status R", ("data %04X index %d\n", data, m_video.palette_index));
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return data;
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}
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WRITE8_MEMBER(kcgd_state::palette_index_w)
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{
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m_video.control = data;
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m_video.palette_index = ((data >> 2) & 15);
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DBG_LOG(1,"Palette index, Control W", ("data %02XH index %d\n", data, m_video.palette_index));
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}
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WRITE8_MEMBER(kcgd_state::palette_data_w)
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{
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DBG_LOG(1,"Palette data W", ("data %02XH index %d\n", data, m_video.palette_index));
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m_video.palette[m_video.palette_index] = data;
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m_palette->set_pen_color(m_video.palette_index,
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85*(data & 3), 85*((data >> 2) & 3), 85*((data >> 4) & 3));
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}
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READ8_MEMBER(kcgd_state::palette_index_r)
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{
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return 0;
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}
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READ8_MEMBER(kcgd_state::palette_data_r)
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{
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DBG_LOG(1,"Palette data R", ("index %d\n", m_video.palette_index));
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return m_video.palette[m_video.palette_index];
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}
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/*
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Raster sizes are:
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- 800(400)x480 in hires(lores) 60 Hz interlaced mode
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- 800(400)x240 in hires(lores) 30 Hz progressive mode
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Video memory is 17 bits wide (bit 16 indicates hi/lo res mode for each word,
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host writes it separately (via bit 7 in 167772).
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*/
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void kcgd_state::draw_scanline(UINT16 *p, UINT16 offset)
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{
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int i;
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for ( i = 0; i < 100; i++ )
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{
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UINT32 data = m_videoram[ offset++ ];
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if (BIT(data, 16)) {
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*p = ( data >> 12) & 0x0F; p++;
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*p = ( data >> 12) & 0x0F; p++;
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*p = ( data >> 8 ) & 0x0F; p++;
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*p = ( data >> 8 ) & 0x0F; p++;
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*p = ( data >> 4 ) & 0x0F; p++;
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*p = ( data >> 4 ) & 0x0F; p++;
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*p = data & 0x0F; p++;
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*p = data & 0x0F; p++;
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} else {
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*p = 5*(( data >> 14) & 0x03); p++;
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*p = 5*(( data >> 12) & 0x03); p++;
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*p = 5*(( data >> 10) & 0x03); p++;
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*p = 5*(( data >> 8 ) & 0x03); p++;
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*p = 5*(( data >> 6 ) & 0x03); p++;
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*p = 5*(( data >> 4 ) & 0x03); p++;
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*p = 5*(( data >> 2 ) & 0x03); p++;
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*p = 5*( data & 0x03); p++;
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}
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}
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}
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TIMER_DEVICE_CALLBACK_MEMBER(kcgd_state::scanline_callback)
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{
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UINT16 y = m_screen->vpos(), offset;
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if (y < KCGD_VERT_START) return;
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y -= KCGD_VERT_START;
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if (y >= KCGD_DISP_VERT) return;
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offset = BIT(m_video.status, KCGD_STATUS_PAGE) ? (KCGD_PAGE_1 >> 1) : (KCGD_PAGE_0 >> 1);
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DBG_LOG(2,"scanline_cb", ("frame %d y %.3d page %d offset %04X *offset %04X\n",
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m_screen->frame_number(), BIT(m_video.status, KCGD_STATUS_PAGE),
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y, offset + y, m_videoram[offset + y]));
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draw_scanline(&m_tmpbmp.pix16(y), m_videoram[offset + (KCGD_DISP_VERT-1) - y]);
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}
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UINT32 kcgd_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
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{
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copybitmap(bitmap, m_tmpbmp, 0, 0, KCGD_HORZ_START, KCGD_VERT_START, cliprect);
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return 0;
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}
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/* F4 Character Displayer */
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static const gfx_layout kcgd_charlayout =
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{
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8, 10, /* 8x10 pixels */
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256, /* 256 characters */
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1, /* 1 bits per pixel */
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{ 0 }, /* no bitplanes */
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/* x offsets */
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{ 0, 1, 2, 3, 4, 5, 6, 7 },
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/* y offsets */
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{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8, 9*8 },
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8*10 /* every char takes 10 bytes */
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};
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static GFXDECODE_START( kcgd )
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GFXDECODE_ENTRY("maincpu", 0112236, kcgd_charlayout, 0, 1)
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GFXDECODE_END
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static MACHINE_CONFIG_START( kcgd, kcgd_state )
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MCFG_CPU_ADD("maincpu", K1801VM2, XTAL_30_8MHz/4)
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MCFG_CPU_PROGRAM_MAP(kcgd_mem)
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MCFG_T11_INITIAL_MODE(0100000)
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MCFG_TIMER_DRIVER_ADD_PERIODIC("scantimer", kcgd_state, scanline_callback, attotime::from_hz(50*28*11)) // XXX verify
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MCFG_TIMER_START_DELAY(attotime::from_hz(XTAL_30_8MHz/KCGD_HORZ_START))
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_UPDATE_DRIVER(kcgd_state, screen_update)
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MCFG_SCREEN_RAW_PARAMS(XTAL_30_8MHz, KCGD_TOTAL_HORZ, KCGD_HORZ_START,
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KCGD_HORZ_START+KCGD_DISP_HORZ, KCGD_TOTAL_VERT, KCGD_VERT_START,
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KCGD_VERT_START+KCGD_DISP_VERT);
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MCFG_SCREEN_PALETTE("palette")
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MCFG_PALETTE_ADD("palette", 16)
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MCFG_PALETTE_INIT_OWNER(kcgd_state, kcgd)
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MCFG_GFXDECODE_ADD("gfxdecode", "palette", kcgd)
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#if 0
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MCFG_DEVICE_ADD("ms7004", MS7004, 0)
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MCFG_MS7004_TX_HANDLER(DEVWRITELINE("i8251kbd", i8251_device, write_rxd))
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MCFG_DEVICE_ADD("keyboard_clock", CLOCK, 4800*16)
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MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(kcgd_state, write_keyboard_clock))
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#endif
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MACHINE_CONFIG_END
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ROM_START( dvk_kcgd )
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ROM_REGION16_BE(0x100000,"maincpu", ROMREGION_ERASE00)
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ROM_DEFAULT_BIOS("181")
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ROM_SYSTEM_BIOS(0, "181", "mask 181")
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ROMX_LOAD("kr1801re2-181.bin", 0100000, 020000, CRC(acac124f) SHA1(412c3eb71bece6f791fc5a9d707cf4692fd0b45b), ROM_BIOS(1))
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ROM_SYSTEM_BIOS(1, "182", "mask 182")
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ROMX_LOAD("kr1801re2-182.bin", 0100000, 020000, CRC(3ca2921a) SHA1(389b30c40ed7e41dae71d58c7bff630359a48153), ROM_BIOS(2))
|
||||
ROM_END
|
||||
|
||||
/* Driver */
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
|
||||
COMP( 1987, dvk_kcgd, 0, 0, kcgd, 0, driver_device, 0, "USSR", "DVK KCGD", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
|
||||
Loading…
Reference in New Issue
Block a user