From 2894c038d87b4bc0bee7e39a44e7921e1c669411 Mon Sep 17 00:00:00 2001 From: Olivier Galibert Date: Thu, 3 Jan 2019 18:22:15 +0100 Subject: [PATCH] wd33x9c: Checkpoint commit for co-debugging --- src/devices/machine/nscsi_bus.h | 6 +- src/devices/machine/nscsi_cd.cpp | 10 +- src/devices/machine/nscsi_hd.cpp | 16 +- src/devices/machine/nscsi_hd.h | 3 +- src/devices/machine/wd33c9x.cpp | 1034 +++++++++++++++--------------- src/devices/machine/wd33c9x.h | 3 +- src/emu/dislot.h | 1 + src/mame/drivers/cps3.cpp | 81 ++- 8 files changed, 577 insertions(+), 577 deletions(-) diff --git a/src/devices/machine/nscsi_bus.h b/src/devices/machine/nscsi_bus.h index 82640ae5287..0eadd51de7f 100644 --- a/src/devices/machine/nscsi_bus.h +++ b/src/devices/machine/nscsi_bus.h @@ -18,7 +18,7 @@ class nscsi_device; class nscsi_bus_device : public device_t { public: - nscsi_bus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + nscsi_bus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); void ctrl_w(int refid, uint32_t lines, uint32_t mask); void data_w(int refid, uint32_t lines); @@ -49,7 +49,7 @@ private: }; class nscsi_connector: public device_t, - public device_slot_interface + public device_slot_interface { public: template @@ -61,7 +61,7 @@ public: set_default_option(dflt); set_fixed(fixed); } - nscsi_connector(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + nscsi_connector(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0); virtual ~nscsi_connector(); nscsi_device *get_device(); diff --git a/src/devices/machine/nscsi_cd.cpp b/src/devices/machine/nscsi_cd.cpp index fc1898eecd5..2d45481f740 100644 --- a/src/devices/machine/nscsi_cd.cpp +++ b/src/devices/machine/nscsi_cd.cpp @@ -3,7 +3,7 @@ #include "emu.h" #include "machine/nscsi_cd.h" -#define VERBOSE 0 +#define VERBOSE 1 #include "logmacro.h" DEFINE_DEVICE_TYPE(NSCSI_CDROM, nscsi_cdrom_device, "scsi_cdrom", "SCSI CD-ROM") @@ -76,10 +76,10 @@ void nscsi_cdrom_device::device_reset() cur_sector = -1; } -MACHINE_CONFIG_START(nscsi_cdrom_device::device_add_mconfig) - MCFG_CDROM_ADD("image") - MCFG_CDROM_INTERFACE("cdrom") -MACHINE_CONFIG_END +void nscsi_cdrom_device::device_add_mconfig(machine_config &config) +{ + CDROM(config, image).set_interface("cdrom"); +} void nscsi_cdrom_device::set_block_size(u32 block_size) { diff --git a/src/devices/machine/nscsi_hd.cpp b/src/devices/machine/nscsi_hd.cpp index 1136e76ce9f..b623d105da3 100644 --- a/src/devices/machine/nscsi_hd.cpp +++ b/src/devices/machine/nscsi_hd.cpp @@ -20,7 +20,7 @@ nscsi_harddisk_device::nscsi_harddisk_device(const machine_config &mconfig, cons } nscsi_harddisk_device::nscsi_harddisk_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : - nscsi_full_device(mconfig, type, tag, owner, clock), harddisk(nullptr), lba(0), cur_lba(0), blocks(0), bytes_per_sector(0) + nscsi_full_device(mconfig, type, tag, owner, clock), image(*this, "image"), harddisk(nullptr), lba(0), cur_lba(0), blocks(0), bytes_per_sector(0) { } @@ -37,8 +37,7 @@ void nscsi_harddisk_device::device_start() void nscsi_harddisk_device::device_reset() { nscsi_full_device::device_reset(); - harddisk_image_device *hd = subdevice("image"); - harddisk = hd->get_hard_disk_file(); + harddisk = image->get_hard_disk_file(); if(!harddisk) { scsi_id = -1; bytes_per_sector = 0; @@ -46,18 +45,17 @@ void nscsi_harddisk_device::device_reset() const hard_disk_info *hdinfo = hard_disk_get_info(harddisk); bytes_per_sector = hdinfo->sectorbytes; - chd_file *chd = hd->get_chd_file(); + chd_file *chd = image->get_chd_file(); if(chd != nullptr) chd->read_metadata(HARD_DISK_IDENT_METADATA_TAG, 0, m_inquiry_data); } cur_lba = -1; } -MACHINE_CONFIG_START(nscsi_harddisk_device::device_add_mconfig) - MCFG_HARDDISK_ADD("image") - MCFG_HARDDISK_INTERFACE("scsi_hdd") -MACHINE_CONFIG_END - +void nscsi_harddisk_device::device_add_mconfig(machine_config &config) +{ + HARDDISK(config, image).set_interface("scsi_hdd"); +} uint8_t nscsi_harddisk_device::scsi_get_data(int id, int pos) { diff --git a/src/devices/machine/nscsi_hd.h b/src/devices/machine/nscsi_hd.h index 19dfe55c0e5..5ddbf3e8519 100644 --- a/src/devices/machine/nscsi_hd.h +++ b/src/devices/machine/nscsi_hd.h @@ -6,7 +6,7 @@ #pragma once #include "machine/nscsi_bus.h" -#include "harddisk.h" +#include "imagedev/harddriv.h" class nscsi_harddisk_device : public nscsi_full_device { @@ -24,6 +24,7 @@ protected: virtual uint8_t scsi_get_data(int id, int pos) override; virtual void scsi_put_data(int buf, int offset, uint8_t data) override; + required_device image; uint8_t block[512]; hard_disk_file *harddisk; int lba, cur_lba, blocks; diff --git a/src/devices/machine/wd33c9x.cpp b/src/devices/machine/wd33c9x.cpp index a15bc3d4acf..387c4824578 100644 --- a/src/devices/machine/wd33c9x.cpp +++ b/src/devices/machine/wd33c9x.cpp @@ -29,8 +29,7 @@ #define LOG_REGS (LOG_READS | LOG_WRITES) #define LOG_ALL (LOG_REGS | LOG_COMMANDS | LOG_ERRORS | LOG_MISC | LOG_LINES | LOG_STATE | LOG_STEP) -#define VERBOSE (LOG_COMMANDS | LOG_ERRORS | LOG_STATE) -#define LOG_OUTPUT_FUNC printf +#define VERBOSE (LOG_COMMANDS | LOG_ERRORS | LOG_STATE | LOG_REGS | LOG_STEP) #include "logmacro.h" enum register_addresses_e : uint8_t { @@ -279,6 +278,27 @@ enum : uint16_t { INIT_CPT_RECV_BYTE_NACK }; +const char *const wd33c9x_base_device::state_names[] = { + "-", + "IDLE", + "FINISHED", + "DISC_SEL_ARBITRATION", + "INIT_MSG_WAIT_REQ", + "INIT_XFR", + "INIT_XFR_SEND_PAD_WAIT_REQ", + "INIT_XFR_SEND_PAD", + "INIT_XFR_RECV_PAD_WAIT_REQ", + "INIT_XFR_RECV_PAD", + "INIT_XFR_RECV_BYTE_ACK", + "INIT_XFR_RECV_BYTE_NACK", + "INIT_XFR_FUNCTION_COMPLETE", + "INIT_XFR_BUS_COMPLETE", + "INIT_XFR_WAIT_REQ", + "INIT_CPT_RECV_BYTE_ACK", + "INIT_CPT_RECV_WAIT_REQ", + "INIT_CPT_RECV_BYTE_NACK", +}; + enum : uint16_t { // Arbitration ARB_WAIT_BUS_FREE = 1, @@ -299,6 +319,24 @@ enum : uint16_t { RECV_WAIT_REQ_0 }; +const char *const wd33c9x_base_device::substate_names[] = { + "-", + "ARB_WAIT_BUS_FREE", + "ARB_CHECK_FREE", + "ARB_EXAMINE_BUS", + "ARB_ASSERT_SEL", + "ARB_SET_DEST", + "ARB_RELEASE_BUSY", + "ARB_TIMEOUT_BUSY", + "ARB_TIMEOUT_ABORT", + "ARB_DESKEW_WAIT", + "SEND_WAIT_SETTLE", + "SEND_WAIT_REQ_0", + "RECV_WAIT_REQ_1", + "RECV_WAIT_SETTLE", + "RECV_WAIT_REQ_0", +}; + enum : uint16_t { STATE_MASK = 0x00ff, SUB_SHIFT = 8, @@ -327,7 +365,6 @@ wd33c9x_base_device::wd33c9x_base_device(const machine_config &mconfig, device_t , m_scsi_state{ IDLE } , m_mode{ MODE_D } , m_xfr_phase{ 0 } - , m_step_count{ 0 } , m_transfer_count{ 0 } , m_data_fifo{ 0 } , m_data_fifo_pos{ 0 } @@ -358,7 +395,6 @@ void wd33c9x_base_device::device_start() save_item(NAME(m_mode)); save_item(NAME(m_scsi_state)); save_item(NAME(m_xfr_phase)); - save_item(NAME(m_step_count)); save_item(NAME(m_transfer_count)); save_item(NAME(m_data_fifo)); save_item(NAME(m_data_fifo_pos)); @@ -387,7 +423,6 @@ void wd33c9x_base_device::device_reset() set_scsi_state(IDLE); m_mode = MODE_D; m_xfr_phase = 0; - m_step_count = 0; m_transfer_count = 0; data_fifo_reset(); irq_fifo_reset(); @@ -462,7 +497,7 @@ READ8_MEMBER(wd33c9x_base_device::indir_r) case 1: return indir_reg_r(space, 0, mem_mask); default: - LOGMASKED(LOG_READS | LOG_ERRORS, "%s: Read from invalid offset %d\n", shortname(), offset); + LOGMASKED(LOG_READS | LOG_ERRORS, "Read from invalid offset %d\n", offset); break; } return 0; @@ -475,6 +510,7 @@ READ8_MEMBER(wd33c9x_base_device::indir_r) WRITE8_MEMBER(wd33c9x_base_device::indir_w) { + logerror("REG %d %02x\n", offset, data); switch (offset) { case 0: indir_addr_w(space, 0, data, mem_mask); @@ -483,7 +519,7 @@ WRITE8_MEMBER(wd33c9x_base_device::indir_w) indir_reg_w(space, 0, data, mem_mask); break; default: - LOGMASKED(LOG_WRITES | LOG_ERRORS, "%s: Write to invalid offset %d (data=%02x)\n", shortname(), offset, data); + LOGMASKED(LOG_WRITES | LOG_ERRORS, "Write to invalid offset %d (data=%02x)\n", offset, data); break; } } @@ -498,7 +534,6 @@ READ8_MEMBER(wd33c9x_base_device::indir_addr_r) if (offset != 0) { fatalerror("%s: Read from invalid address offset %d\n", shortname(), offset); } - step(false); return m_regs[AUXILIARY_STATUS]; } @@ -540,6 +575,7 @@ READ8_MEMBER(wd33c9x_base_device::indir_reg_r) fatalerror("%s: The host should never access the data register without DBR set.\n", shortname()); } ret = data_fifo_pop(); + logerror("data = %02x\n", ret); m_regs[AUXILIARY_STATUS] &= ~AUXILIARY_STATUS_DBR; break; @@ -556,6 +592,8 @@ READ8_MEMBER(wd33c9x_base_device::indir_reg_r) update_irq(); } + logerror("reg %02x = %02x\n", m_addr, ret); + // No address increment on accesses to Command, Data, and Auxiliary Status Registers if (m_addr != COMMAND && m_addr != AUXILIARY_STATUS) { m_addr = (m_addr + 1) & REGS_MASK; @@ -585,7 +623,7 @@ WRITE8_MEMBER(wd33c9x_base_device::indir_reg_w) case INVALID_1D: case INVALID_1E: case AUXILIARY_STATUS: - LOGMASKED(LOG_WRITES | LOG_ERRORS, "%s: Write to read-only register address %d (data=%02x)\n", shortname(), m_addr, data); + LOGMASKED(LOG_WRITES | LOG_ERRORS, "Write to read-only register address %d (data=%02x)\n", m_addr, data); break; case COMMAND: { @@ -637,7 +675,7 @@ WRITE8_MEMBER(wd33c9x_base_device::indir_reg_w) WRITE_LINE_MEMBER(wd33c9x_base_device::reset_w) { if (state) { - LOGMASKED(LOG_LINES, "%s: Reset via MR line\n", shortname()); + LOGMASKED(LOG_LINES, "Reset via MR line\n"); device_reset(); } } @@ -695,7 +733,7 @@ void wd33c9x_base_device::start_command() switch (cc) { case COMMAND_CC_RESET: - LOGMASKED(LOG_COMMANDS, "%s: Reset Command\n", shortname()); + LOGMASKED(LOG_COMMANDS, "Reset Command\n"); scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL); m_regs[OWN_ID] = m_command_length; @@ -709,17 +747,18 @@ void wd33c9x_base_device::start_command() set_scsi_state(FINISHED); irq_fifo_push((m_regs[OWN_ID] & OWN_ID_EAF) ? SCSI_STATUS_RESET_EAF : SCSI_STATUS_RESET); scsi_id = (m_regs[OWN_ID] & OWN_ID_SCSI_ID); + step(false); break; case COMMAND_CC_ABORT: - LOGMASKED(LOG_COMMANDS, "%s: Abort Command\n", shortname()); + LOGMASKED(LOG_COMMANDS, "Abort Command\n"); set_scsi_state(FINISHED); // FIXME irq_fifo_push((m_regs[OWN_ID] & OWN_ID_EAF) ? SCSI_STATUS_RESET_EAF : SCSI_STATUS_RESET); break; case COMMAND_CC_ASSERT_ATN: - LOGMASKED(LOG_COMMANDS, "%s: Assert ATN Command\n", shortname()); + LOGMASKED(LOG_COMMANDS, "Assert ATN Command\n"); if (m_mode != MODE_I) { fatalerror("%s: ASSERT_ATN command only valid in the Initiator state.", shortname()); } @@ -727,7 +766,7 @@ void wd33c9x_base_device::start_command() return; case COMMAND_CC_NEGATE_ACK: - LOGMASKED(LOG_COMMANDS, "%s: Negate ACK Command\n", shortname()); + LOGMASKED(LOG_COMMANDS, "Negate ACK Command\n"); // FIXME - This is causing problems, so ignore for now. //if (m_mode != MODE_I) { // fatalerror("NEGATE_ACK command only valid in the Initiator state."); @@ -736,7 +775,7 @@ void wd33c9x_base_device::start_command() return; case COMMAND_CC_DISCONNECT: - LOGMASKED(LOG_COMMANDS, "%s: Disconnect Command\n", shortname()); + LOGMASKED(LOG_COMMANDS, "Disconnect Command\n"); scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL); m_mode = MODE_D; @@ -746,16 +785,17 @@ void wd33c9x_base_device::start_command() case COMMAND_CC_SELECT: case COMMAND_CC_SELECT_ATN: - LOGMASKED(LOG_COMMANDS, "%s: %s Command\n", shortname(), select_strings[cc - COMMAND_CC_SELECT_ATN]); + LOGMASKED(LOG_COMMANDS, "%s Command\n", select_strings[cc - COMMAND_CC_SELECT_ATN]); if (m_mode != MODE_D) { fatalerror("Select commands only valid in the Disconnected state."); } set_scsi_state((ARB_WAIT_BUS_FREE << SUB_SHIFT) | DISC_SEL_ARBITRATION); + step(false); break; case COMMAND_CC_SELECT_TRANSFER: case COMMAND_CC_SELECT_ATN_TRANSFER: - LOGMASKED(LOG_COMMANDS, "%s: %s Command\n", shortname(), select_strings[cc - COMMAND_CC_SELECT_ATN]); + LOGMASKED(LOG_COMMANDS, "%s Command\n", select_strings[cc - COMMAND_CC_SELECT_ATN]); if (m_mode == MODE_D) { set_scsi_state((ARB_WAIT_BUS_FREE << SUB_SHIFT) | DISC_SEL_ARBITRATION); m_regs[COMMAND_PHASE] = COMMAND_PHASE_ZERO; @@ -768,10 +808,11 @@ void wd33c9x_base_device::start_command() } set_command_length(cc); load_transfer_count(); + step(false); break; case COMMAND_CC_TRANSFER_INFO: - LOGMASKED(LOG_COMMANDS, "%s: Transfer Info Command\n", shortname()); + LOGMASKED(LOG_COMMANDS, "Transfer Info Command\n"); if (m_mode != MODE_I) { fatalerror("%s: TRANSFER_INFO command only valid in the Initiator state.", shortname()); } @@ -787,8 +828,6 @@ void wd33c9x_base_device::start_command() fatalerror("%s: Unimplemented command: 0x%02x", shortname(), cc); break; } - - delay(1); } @@ -810,563 +849,524 @@ static const char * phase_strings[8] = { void wd33c9x_base_device::step(bool timeout) { - if (++m_step_count > 1) { - return; - } - const uint8_t cc = (m_regs[COMMAND] & COMMAND_CC); const bool sat = (cc == COMMAND_CC_SELECT_TRANSFER || cc == COMMAND_CC_SELECT_ATN_TRANSFER); - uint32_t cycles = 0; - do { - const uint32_t ctrl = scsi_bus->ctrl_r(); - const uint32_t data = scsi_bus->data_r(); + const uint32_t ctrl = scsi_bus->ctrl_r(); + const uint32_t data = scsi_bus->data_r(); - m_step_count = 1; + LOGMASKED(LOG_STEP, + "%s: step - PHASE:%s BSY:%x SEL:%x REQ:%x ACK:%x ATN:%x RST:%x DATA:%02x (%s.%s) %s\n", + shortname(), + phase_strings[ctrl & S_PHASE_MASK], + (ctrl & S_BSY) ? 1 : 0, + (ctrl & S_SEL) ? 1 : 0, + (ctrl & S_REQ) ? 1 : 0, + (ctrl & S_ACK) ? 1 : 0, + (ctrl & S_ATN) ? 1 : 0, + (ctrl & S_RST) ? 1 : 0, + data, + state_names[m_scsi_state & STATE_MASK], substate_names[m_scsi_state >> SUB_SHIFT], + (timeout) ? "timeout" : "change" + ); - LOGMASKED(LOG_STEP, - "%s: step - PHASE:%s BSY:%x SEL:%x REQ:%x ACK:%x ATN:%x RST:%x DATA:%x (%d.%d) %s\n", - shortname(), - phase_strings[ctrl & S_PHASE_MASK], - (ctrl & S_BSY) ? 1 : 0, - (ctrl & S_SEL) ? 1 : 0, - (ctrl & S_REQ) ? 1 : 0, - (ctrl & S_ACK) ? 1 : 0, - (ctrl & S_ATN) ? 1 : 0, - (ctrl & S_RST) ? 1 : 0, - data, - m_scsi_state & STATE_MASK, m_scsi_state >> SUB_SHIFT, - (timeout) ? "timeout" : "change" - ); - - if (m_mode == MODE_I) { - if (ctrl & S_BSY) { - if (ctrl & S_REQ) { - uint8_t xfr_phase = (ctrl & S_PHASE_MASK); - switch (m_scsi_state) { - case DISC_SEL_ARBITRATION: - m_xfr_phase = xfr_phase; - break; - - case INIT_XFR_WAIT_REQ: - break; - - default: - if (m_xfr_phase != xfr_phase) { - fatalerror("%s: Unexpected phase change during state.\n", shortname()); - } - break; + if (m_mode == MODE_I) { + if (ctrl & S_BSY) { + if (ctrl & S_REQ) { + uint8_t xfr_phase = (ctrl & S_PHASE_MASK); + switch (m_scsi_state) { + case DISC_SEL_ARBITRATION: + m_xfr_phase = xfr_phase; + break; + + case INIT_XFR_WAIT_REQ: + break; + + default: + if (m_xfr_phase != xfr_phase) { + fatalerror("%s: Unexpected phase change during state.\n", shortname()); } + break; + } + } + } else { + LOGMASKED(LOG_STATE, "Target disconnected\n"); + if (sat) { + switch (m_regs[COMMAND_PHASE]) { + case COMMAND_PHASE_DISCONNECT_MESSAGE: + set_scsi_state(FINISHED); + m_regs[COMMAND_PHASE] = COMMAND_PHASE_DISCONNECTED; + break; + + case COMMAND_PHASE_COMMAND_COMPLETE: + if (m_regs[CONTROL] & CONTROL_EDI) { + set_scsi_state(FINISHED); + irq_fifo_push(SCSI_STATUS_SELECT_TRANSFER_SUCCESS); + } + break; + + default: + fatalerror("%s: Unhandled command phase during Select-and-Transfer disconnect.\n", shortname()); + break; } } else { - LOGMASKED(LOG_STATE, "%s: Target disconnected\n", shortname()); - if (sat) { - switch (m_regs[COMMAND_PHASE]) { - case COMMAND_PHASE_DISCONNECT_MESSAGE: - set_scsi_state(FINISHED); - m_regs[COMMAND_PHASE] = COMMAND_PHASE_DISCONNECTED; - break; - - case COMMAND_PHASE_COMMAND_COMPLETE: - if (m_regs[CONTROL] & CONTROL_EDI) { - set_scsi_state(FINISHED); - irq_fifo_push(SCSI_STATUS_SELECT_TRANSFER_SUCCESS); - } - break; - - default: - fatalerror("%s: Unhandled command phase during Select-and-Transfer disconnect.\n", shortname()); - break; - } - } - else { - set_scsi_state(FINISHED); - irq_fifo_push(SCSI_STATUS_DISCONNECT); - } - m_mode = MODE_D; - scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); - scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL); - continue; + set_scsi_state(FINISHED); + irq_fifo_push(SCSI_STATUS_DISCONNECT); } + m_mode = MODE_D; + scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); + scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL); } + } - switch (m_scsi_state & SUB_MASK ? m_scsi_state & SUB_MASK : m_scsi_state & STATE_MASK) { - case IDLE: + switch (m_scsi_state & SUB_MASK ? m_scsi_state & SUB_MASK : m_scsi_state & STATE_MASK) { + case IDLE: + break; + + case FINISHED: + set_scsi_state(IDLE); + m_regs[AUXILIARY_STATUS] &= ~(AUXILIARY_STATUS_CIP | AUXILIARY_STATUS_BSY); + update_irq(); + break; + + case ARB_WAIT_BUS_FREE << SUB_SHIFT: + if (!(ctrl & (S_BSY | S_SEL))) { + set_scsi_state_sub(ARB_CHECK_FREE); + delay(1); + } + break; + + case ARB_CHECK_FREE << SUB_SHIFT: + if (ctrl & (S_BSY | S_SEL)) { + set_scsi_state_sub(ARB_CHECK_FREE); break; + } + if (timeout) { + scsi_bus->data_w(scsi_refid, 1 << scsi_id); + scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY); + set_scsi_state_sub(ARB_EXAMINE_BUS); + delay(1); + } + break; - case FINISHED: - set_scsi_state(IDLE); - m_regs[AUXILIARY_STATUS] &= ~(AUXILIARY_STATUS_CIP | AUXILIARY_STATUS_BSY); - update_irq(); - break; - - case ARB_WAIT_BUS_FREE << SUB_SHIFT: - if (timeout) { - if (!(ctrl & (S_BSY | S_SEL))) { + case ARB_EXAMINE_BUS << SUB_SHIFT: + if (timeout) { + if (ctrl & S_SEL) { + scsi_bus->ctrl_w(scsi_refid, 0, S_BSY); + scsi_bus->data_w(scsi_refid, 0); + set_scsi_state_sub(ARB_WAIT_BUS_FREE); + } else { + int win; + for (win = 7; win >=0 && !(data & (1 << win)); win--); + if (win == scsi_id) { + scsi_bus->ctrl_w(scsi_refid, S_SEL, S_SEL); + set_scsi_state_sub(ARB_ASSERT_SEL); + delay(1); + } else { + scsi_bus->data_w(scsi_refid, 0); + scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); set_scsi_state_sub(ARB_CHECK_FREE); } - cycles = 1; } - break; + } + break; - case ARB_CHECK_FREE << SUB_SHIFT: - if (timeout) { - uint8_t next_state; - if (ctrl & (S_BSY | S_SEL)) { - next_state = ARB_WAIT_BUS_FREE; - cycles = 1; - } - else { - scsi_bus->data_w(scsi_refid, 1 << scsi_id); - scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY); - next_state = ARB_EXAMINE_BUS; - cycles = 1; - } - set_scsi_state_sub(next_state); - } - break; + case ARB_ASSERT_SEL << SUB_SHIFT: + if (timeout) { + scsi_bus->data_w(scsi_refid, (1 << scsi_id) | (1 << (m_regs[DESTINATION_ID] & DESTINATION_ID_DI))); + set_scsi_state_sub(ARB_SET_DEST); + delay(1); + } + break; - case ARB_EXAMINE_BUS << SUB_SHIFT: - if (timeout) { - if (ctrl & S_SEL) { - scsi_bus->ctrl_w(scsi_refid, 0, S_BSY); - scsi_bus->data_w(scsi_refid, 0); - set_scsi_state_sub(ARB_WAIT_BUS_FREE); - } - else { - int win; - for (win = 7; win >=0 && !(data & (1 << win)); win--) {}; - if (win == scsi_id) { - scsi_bus->ctrl_w(scsi_refid, S_SEL, S_SEL); - set_scsi_state_sub(ARB_ASSERT_SEL); - } - else { - scsi_bus->data_w(scsi_refid, 0); - scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); - } - } - cycles = 1; - } - break; + case ARB_SET_DEST << SUB_SHIFT: + if (timeout) { + scsi_bus->ctrl_w(scsi_refid, (cc == COMMAND_CC_SELECT_ATN || cc == COMMAND_CC_SELECT_ATN_TRANSFER) ? S_ATN : 0, S_ATN | S_BSY); + set_scsi_state_sub(ARB_RELEASE_BUSY); + delay(1); + } + break; - case ARB_ASSERT_SEL << SUB_SHIFT: - if (timeout) { - scsi_bus->data_w(scsi_refid, (1 << scsi_id) | (1 << (m_regs[DESTINATION_ID] & DESTINATION_ID_DI))); - set_scsi_state_sub(ARB_SET_DEST); - cycles = 1; - } - break; - - case ARB_SET_DEST << SUB_SHIFT: - if (timeout) { - scsi_bus->ctrl_w(scsi_refid, (cc == COMMAND_CC_SELECT_ATN || cc == COMMAND_CC_SELECT_ATN_TRANSFER) ? S_ATN : 0, S_ATN | S_BSY); - set_scsi_state_sub(ARB_RELEASE_BUSY); - cycles = 1; - } - break; - - case ARB_RELEASE_BUSY << SUB_SHIFT: - if (timeout) { - if (ctrl & S_BSY) { - set_scsi_state_sub(ARB_DESKEW_WAIT); - if (cc == COMMAND_CC_RESELECT) { - scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY); - } - cycles = 1; - } - else { - set_scsi_state_sub(ARB_TIMEOUT_BUSY); - cycles = 1; - } - } - break; - - case ARB_DESKEW_WAIT << SUB_SHIFT: - if (timeout) { - scsi_bus->data_w(scsi_refid, 0); - scsi_bus->ctrl_w(scsi_refid, 0, S_SEL); - m_mode = (cc == COMMAND_CC_RESELECT) ? MODE_T : MODE_I; - set_scsi_state_sub(0); - ++m_step_count; - } - break; - - case ARB_TIMEOUT_BUSY << SUB_SHIFT: - if (timeout) { - scsi_bus->data_w(scsi_refid, 0); - set_scsi_state_sub(ARB_TIMEOUT_ABORT); - cycles = 1000; - } - else if (ctrl & S_BSY) { + case ARB_RELEASE_BUSY << SUB_SHIFT: + if (timeout) { + if (ctrl & S_BSY) { set_scsi_state_sub(ARB_DESKEW_WAIT); if (cc == COMMAND_CC_RESELECT) { scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY); } - cycles = 1; + delay(1); + } else { + set_scsi_state_sub(ARB_TIMEOUT_BUSY); + delay(1); // Should be the select timeout... } - break; + } + break; - case ARB_TIMEOUT_ABORT << SUB_SHIFT: - if (timeout) { - if (ctrl & S_BSY) { - set_scsi_state_sub(ARB_DESKEW_WAIT); - if (cc == COMMAND_CC_RESELECT) { - scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY); - } - cycles = 1; + case ARB_DESKEW_WAIT << SUB_SHIFT: + if (timeout) { + scsi_bus->data_w(scsi_refid, 0); + scsi_bus->ctrl_w(scsi_refid, 0, S_SEL); + m_mode = (cc == COMMAND_CC_RESELECT) ? MODE_T : MODE_I; + set_scsi_state_sub(0); + step(true); + } + break; + + case ARB_TIMEOUT_BUSY << SUB_SHIFT: + if (timeout) { + scsi_bus->data_w(scsi_refid, 0); + set_scsi_state_sub(ARB_TIMEOUT_ABORT); + delay(1000); + } else if (ctrl & S_BSY) { + set_scsi_state_sub(ARB_DESKEW_WAIT); + if (cc == COMMAND_CC_RESELECT) { + scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY); + } + delay(1); + } + break; + + case ARB_TIMEOUT_ABORT << SUB_SHIFT: + if (timeout) { + if (ctrl & S_BSY) { + set_scsi_state_sub(ARB_DESKEW_WAIT); + if (cc == COMMAND_CC_RESELECT) { + scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY); } - else { - scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); - scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL); - m_regs[AUXILIARY_STATUS] &= ~(AUXILIARY_STATUS_CIP | AUXILIARY_STATUS_BSY); - m_mode = MODE_D; - set_scsi_state(IDLE); - irq_fifo_push(SCSI_STATUS_SELECTION_TIMEOUT); - update_irq(); + delay(1); + } else { + scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); + scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL); + m_regs[AUXILIARY_STATUS] &= ~(AUXILIARY_STATUS_CIP | AUXILIARY_STATUS_BSY); + m_mode = MODE_D; + set_scsi_state(IDLE); + irq_fifo_push(SCSI_STATUS_SELECTION_TIMEOUT); + update_irq(); + } + } + break; + + case SEND_WAIT_SETTLE << SUB_SHIFT: + if (timeout) { + set_scsi_state_sub(SEND_WAIT_REQ_0); + step(false); + } + break; + + case SEND_WAIT_REQ_0 << SUB_SHIFT: + if (!(ctrl & S_REQ)) { + set_scsi_state_sub(0); + scsi_bus->data_w(scsi_refid, 0); + scsi_bus->ctrl_w(scsi_refid, 0, S_ACK); + if (sat) { + switch (m_xfr_phase) { + case S_PHASE_COMMAND: + ++m_regs[COMMAND_PHASE]; + break; } } - break; + step(false); + } + break; - case SEND_WAIT_SETTLE << SUB_SHIFT: - if (timeout) { - set_scsi_state_sub(SEND_WAIT_REQ_0); - ++m_step_count; - } - break; + case RECV_WAIT_REQ_1 << SUB_SHIFT: + if (ctrl & S_REQ) { + set_scsi_state_sub(RECV_WAIT_SETTLE); + delay(1); + } + break; - case SEND_WAIT_REQ_0 << SUB_SHIFT: - if (!(ctrl & S_REQ)) { - set_scsi_state_sub(0); - scsi_bus->data_w(scsi_refid, 0); - scsi_bus->ctrl_w(scsi_refid, 0, S_ACK); - if (sat) { - switch (m_xfr_phase) { - case S_PHASE_COMMAND: - ++m_regs[COMMAND_PHASE]; - break; - } - } - ++m_step_count; - } - break; - - case RECV_WAIT_REQ_1 << SUB_SHIFT: - if (ctrl & S_REQ) { - set_scsi_state_sub(RECV_WAIT_SETTLE); - cycles = 1; - } - break; - - case RECV_WAIT_SETTLE << SUB_SHIFT: - if (timeout) { - if (sat) { - switch (m_xfr_phase) { - case S_PHASE_DATA_IN: - data_fifo_push(data); - if ((m_regs[CONTROL] & CONTROL_DM) != CONTROL_DM_POLLED) { - set_drq(); - } - else { - decrement_transfer_count(); - m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; - } - break; - - case S_PHASE_STATUS: - m_regs[TARGET_LUN] = data; - m_regs[COMMAND_PHASE] = COMMAND_PHASE_STATUS_RECEIVED; - break; - - case S_PHASE_MSG_IN: - data_fifo_push(data); - break; - - default: - fatalerror("%s: Unexpected phase in RECV_WAIT_SETTLE.\n", shortname()); - break; - } - } - else { + case RECV_WAIT_SETTLE << SUB_SHIFT: + if (timeout) { + if (sat) { + switch (m_xfr_phase) { + case S_PHASE_DATA_IN: data_fifo_push(data); - if (m_xfr_phase == S_PHASE_DATA_IN && (m_regs[CONTROL] & CONTROL_DM) != CONTROL_DM_POLLED) { + if ((m_regs[CONTROL] & CONTROL_DM) != CONTROL_DM_POLLED) { set_drq(); - } - else { + } else { decrement_transfer_count(); m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; } - } - set_scsi_state_sub(RECV_WAIT_REQ_0); - scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK); - ++m_step_count; - } - break; - - case RECV_WAIT_REQ_0 << SUB_SHIFT: - if (!(ctrl & S_REQ)) { - set_scsi_state_sub(0); - ++m_step_count; - } - break; - - case DISC_SEL_ARBITRATION: - scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ); - if (cc == COMMAND_CC_SELECT || cc == COMMAND_CC_SELECT_ATN) { - set_scsi_state(FINISHED); - irq_fifo_push(SCSI_STATUS_SELECT_SUCCESS); - if (ctrl & S_REQ) { - irq_fifo_push(SCSI_STATUS_REQ | m_xfr_phase); - } - } - else { - set_scsi_state(INIT_XFR); - m_regs[COMMAND_PHASE] = COMMAND_PHASE_SELECTED; - } - ++m_step_count; - break; - - case INIT_XFR: - if (ctrl & S_REQ) { - switch (m_xfr_phase) { - case S_PHASE_DATA_OUT: - if ((m_regs[CONTROL] & CONTROL_DM) != CONTROL_DM_POLLED) { - while (!data_fifo_full() && m_transfer_count > 0) { - set_drq(); - } - } - if (!data_fifo_empty()) { - set_scsi_state(INIT_XFR_WAIT_REQ); - cycles = send_byte(); - } - else if ((m_regs[CONTROL] & CONTROL_DM) == CONTROL_DM_POLLED) { - m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; - } break; - case S_PHASE_COMMAND: - if (!data_fifo_empty()) { - uint32_t mask; - if (sat) { - mask = 0; - } - else { - m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; - mask = (m_transfer_count == 0 && m_data_fifo_size == 1) ? S_ATN : 0; - } - set_scsi_state(INIT_XFR_WAIT_REQ); - cycles = send_byte(0, mask); - } - else if (!sat) { - m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; - } - break; - - case S_PHASE_MSG_OUT: - if (sat) { - data_fifo_push(get_msg_out()); - } - if (!data_fifo_empty()) { - uint32_t mask; - if (sat) { - mask = S_ATN; - } - else { - m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; - mask = (m_transfer_count == 0 && m_data_fifo_size == 1) ? S_ATN : 0; - } - set_scsi_state(INIT_XFR_WAIT_REQ); - cycles = send_byte(0, mask); - } - else if (!sat) { - m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; - } - break; - - case S_PHASE_DATA_IN: case S_PHASE_STATUS: + m_regs[TARGET_LUN] = data; + m_regs[COMMAND_PHASE] = COMMAND_PHASE_STATUS_RECEIVED; + break; + case S_PHASE_MSG_IN: - if (!data_fifo_full()) { - // if it's the last message byte, ACK remains asserted, terminate with function_complete() - //state = (m_xfr_phase == S_PHASE_MSG_IN && (!dma_command || tcounter == 1)) ? INIT_XFR_RECV_BYTE_NACK : INIT_XFR_RECV_BYTE_ACK; - scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ); - set_scsi_state((RECV_WAIT_REQ_1 << SUB_SHIFT) | INIT_XFR_RECV_BYTE_ACK); - if (ctrl & S_REQ) { - ++m_step_count; - } - } + logerror("Got msg %02x\n", data); + data_fifo_push(data); break; default: - fatalerror("%s: Invalid phase during INIT_XFR.\n", shortname()); + fatalerror("%s: Unexpected phase in RECV_WAIT_SETTLE.\n", shortname()); break; } + } else { + data_fifo_push(data); + if (m_xfr_phase == S_PHASE_DATA_IN && (m_regs[CONTROL] & CONTROL_DM) != CONTROL_DM_POLLED) { + set_drq(); + } else { + decrement_transfer_count(); + m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; + } } - break; + set_scsi_state_sub(RECV_WAIT_REQ_0); + scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK); + step(false); + } + break; - case INIT_XFR_WAIT_REQ: + case RECV_WAIT_REQ_0 << SUB_SHIFT: + if (!(ctrl & S_REQ)) { + set_scsi_state_sub(0); + step(false); + } + break; + + case DISC_SEL_ARBITRATION: + scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ); + if (cc == COMMAND_CC_SELECT || cc == COMMAND_CC_SELECT_ATN) { + set_scsi_state(FINISHED); + irq_fifo_push(SCSI_STATUS_SELECT_SUCCESS); if (ctrl & S_REQ) { - uint16_t next_state = m_scsi_state; + irq_fifo_push(SCSI_STATUS_REQ | m_xfr_phase); + } + } else { + set_scsi_state(INIT_XFR); + m_regs[COMMAND_PHASE] = COMMAND_PHASE_SELECTED; + } + step(false); + break; - const uint8_t xfr_phase = (ctrl & S_PHASE_MASK); + case INIT_XFR: + if (ctrl & S_REQ) { + switch (m_xfr_phase) { + case S_PHASE_DATA_OUT: + if ((m_regs[CONTROL] & CONTROL_DM) != CONTROL_DM_POLLED) { + if(!data_fifo_full() && m_transfer_count > 0) + set_drq(); + } + if (!data_fifo_empty()) { + set_scsi_state(INIT_XFR_WAIT_REQ); + delay(send_byte()); + } else if ((m_regs[CONTROL] & CONTROL_DM) == CONTROL_DM_POLLED) { + m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; + } + break; - switch ((m_xfr_phase << 3) | xfr_phase) { - case ((S_PHASE_MSG_OUT << 3) | S_PHASE_MSG_OUT): - case ((S_PHASE_COMMAND << 3) | S_PHASE_COMMAND): - case ((S_PHASE_MSG_IN << 3) | S_PHASE_MSG_IN): - next_state = INIT_XFR; - break; + case S_PHASE_COMMAND: + if (!data_fifo_empty()) { + uint32_t mask; + if (sat) { + mask = 0; + } else { + m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; + mask = (m_transfer_count == 0 && m_data_fifo_size == 1) ? S_ATN : 0; + } + set_scsi_state(INIT_XFR_WAIT_REQ); + delay(send_byte(0, mask)); + } else if (!sat) { + m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; + } + break; - case ((S_PHASE_DATA_IN << 3) | S_PHASE_DATA_IN): - case ((S_PHASE_DATA_OUT << 3) | S_PHASE_DATA_OUT): - if (sat || cc == COMMAND_CC_TRANSFER_INFO) { - if (m_transfer_count > 0 || (m_xfr_phase == S_PHASE_DATA_OUT && !data_fifo_empty())) { - next_state = INIT_XFR; + case S_PHASE_MSG_OUT: + if (sat) { + data_fifo_push(get_msg_out()); + } + if (!data_fifo_empty()) { + uint32_t mask; + if (sat) { + mask = S_ATN; + } else { + m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; + mask = (m_transfer_count == 0 && m_data_fifo_size == 1) ? S_ATN : 0; + } + set_scsi_state(INIT_XFR_WAIT_REQ); + delay(send_byte(0, mask)); + } else if (!sat) { + m_regs[AUXILIARY_STATUS] |= AUXILIARY_STATUS_DBR; + } + break; + + case S_PHASE_DATA_IN: + case S_PHASE_STATUS: + case S_PHASE_MSG_IN: + if (!data_fifo_full()) { + // if it's the last message byte, ACK remains asserted, terminate with function_complete() + //state = (m_xfr_phase == S_PHASE_MSG_IN && (!dma_command || tcounter == 1)) ? INIT_XFR_RECV_BYTE_NACK : INIT_XFR_RECV_BYTE_ACK; + scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ); + set_scsi_state((RECV_WAIT_REQ_1 << SUB_SHIFT) | INIT_XFR_RECV_BYTE_ACK); + if (ctrl & S_REQ) + step(false); + } + break; + + default: + fatalerror("%s: Invalid phase during INIT_XFR.\n", shortname()); + break; + } + } + break; + + case INIT_XFR_WAIT_REQ: + if (ctrl & S_REQ) { + uint16_t next_state = m_scsi_state; + + const uint8_t xfr_phase = (ctrl & S_PHASE_MASK); + + switch ((m_xfr_phase << 3) | xfr_phase) { + case ((S_PHASE_MSG_OUT << 3) | S_PHASE_MSG_OUT): + case ((S_PHASE_COMMAND << 3) | S_PHASE_COMMAND): + case ((S_PHASE_MSG_IN << 3) | S_PHASE_MSG_IN): + next_state = INIT_XFR; + break; + + case ((S_PHASE_DATA_IN << 3) | S_PHASE_DATA_IN): + case ((S_PHASE_DATA_OUT << 3) | S_PHASE_DATA_OUT): + if (sat || cc == COMMAND_CC_TRANSFER_INFO) { + if (m_transfer_count > 0 || (m_xfr_phase == S_PHASE_DATA_OUT && !data_fifo_empty())) { + next_state = INIT_XFR; + } + else { + next_state = FINISHED; + uint8_t scsi_status; + if (sat) { + m_regs[COMMAND_PHASE] = COMMAND_PHASE_TRANSFER_COUNT; + scsi_status = SCSI_STATUS_UNEXPECTED_PHASE; } else { - next_state = FINISHED; - uint8_t scsi_status; - if (sat) { - m_regs[COMMAND_PHASE] = COMMAND_PHASE_TRANSFER_COUNT; - scsi_status = SCSI_STATUS_UNEXPECTED_PHASE; - } - else { - scsi_status = SCSI_STATUS_TRANSFER_SUCCESS; - } - irq_fifo_push(scsi_status | m_xfr_phase); + scsi_status = SCSI_STATUS_TRANSFER_SUCCESS; } + irq_fifo_push(scsi_status | m_xfr_phase); } - else { - fatalerror("%s: Unhandled command in data phase.\n", shortname()); + } + else { + fatalerror("%s: Unhandled command in data phase.\n", shortname()); + next_state = FINISHED; + } + break; + + case ((S_PHASE_MSG_OUT << 3) | S_PHASE_COMMAND): + case ((S_PHASE_COMMAND << 3) | S_PHASE_DATA_OUT): + case ((S_PHASE_COMMAND << 3) | S_PHASE_DATA_IN): + case ((S_PHASE_COMMAND << 3) | S_PHASE_STATUS): + case ((S_PHASE_COMMAND << 3) | S_PHASE_MSG_IN): + case ((S_PHASE_DATA_OUT << 3) | S_PHASE_STATUS): + case ((S_PHASE_DATA_IN << 3) | S_PHASE_STATUS): + case ((S_PHASE_STATUS << 3) | S_PHASE_MSG_IN): + if (!(m_xfr_phase & 1) && !data_fifo_empty()) { + fatalerror("%s: Data FIFO is not empty on phase transition.\n", shortname()); + } + + if (sat) { + switch (xfr_phase) { + case S_PHASE_MSG_OUT: + next_state = INIT_XFR; + break; + + case S_PHASE_COMMAND: { + next_state = INIT_XFR; + m_regs[COMMAND_PHASE] = COMMAND_PHASE_CP_BYTES_0; + std::string cmd; + for (uint8_t i = 0; i < m_command_length; ++i) { + const uint8_t command_byte = m_regs[CDB_1 + i]; + cmd += util::string_format(" %02x", command_byte); + data_fifo_push(command_byte); + } + LOGMASKED(LOG_COMMANDS, "Sending command:%s (%d)\n", cmd, m_transfer_count); + break; + } + + case S_PHASE_DATA_OUT: + case S_PHASE_DATA_IN: + next_state = INIT_XFR; + break; + + case S_PHASE_STATUS: + next_state = INIT_XFR; + m_regs[COMMAND_PHASE] = COMMAND_PHASE_RECEIVE_STATUS; + break; + + case S_PHASE_MSG_IN: + next_state = INIT_XFR; + break; + + default: + fatalerror("%s: Unhandled phase in Select-w/Atn-and-Transfer.\n", shortname()); next_state = FINISHED; + break; } + } + else if (cc == COMMAND_CC_TRANSFER_INFO) { + next_state = FINISHED; + irq_fifo_push(SCSI_STATUS_TRANSFER_SUCCESS | xfr_phase); + } + else { + fatalerror("%s: Unhandled command in data phase.\n", shortname()); + next_state = FINISHED; + } + break; + + default: + fatalerror("%s: Unhandled phase transition in INIT_XFR_WAIT_REQ.\n", shortname()); + next_state = FINISHED; + break; + } + + if (next_state != m_scsi_state) { + set_scsi_state(next_state); + m_xfr_phase = xfr_phase; + step(false); + } + } + break; + + case INIT_XFR_RECV_BYTE_ACK: + if (sat && m_xfr_phase == S_PHASE_MSG_IN) { + const uint8_t msg = data_fifo_pop(); + if (m_regs[COMMAND_PHASE] <= COMMAND_PHASE_CP_BYTES_C) { + switch (msg) { + case SM_SAVE_DATA_PTR: + set_scsi_state(FINISHED); + irq_fifo_push(SCSI_STATUS_SAVE_DATA_POINTERS); + m_regs[COMMAND_PHASE] = COMMAND_PHASE_SAVE_DATA_POINTER; break; - case ((S_PHASE_MSG_OUT << 3) | S_PHASE_COMMAND): - case ((S_PHASE_COMMAND << 3) | S_PHASE_DATA_OUT): - case ((S_PHASE_COMMAND << 3) | S_PHASE_DATA_IN): - case ((S_PHASE_COMMAND << 3) | S_PHASE_STATUS): - case ((S_PHASE_COMMAND << 3) | S_PHASE_MSG_IN): - case ((S_PHASE_DATA_OUT << 3) | S_PHASE_STATUS): - case ((S_PHASE_DATA_IN << 3) | S_PHASE_STATUS): - case ((S_PHASE_STATUS << 3) | S_PHASE_MSG_IN): - if (!(m_xfr_phase & 1) && !data_fifo_empty()) { - fatalerror("%s: Data FIFO is not empty on phase transition.\n", shortname()); - } - - if (sat) { - switch (xfr_phase) { - case S_PHASE_MSG_OUT: - next_state = INIT_XFR; - break; - - case S_PHASE_COMMAND: - next_state = INIT_XFR; - m_regs[COMMAND_PHASE] = COMMAND_PHASE_CP_BYTES_0; - LOGMASKED(LOG_COMMANDS, "%s: Sending Command:", shortname()); - for (uint8_t i = 0; i < m_command_length; ++i) { - const uint8_t command_byte = m_regs[CDB_1 + i]; - LOGMASKED(LOG_COMMANDS, " %02x", command_byte); - data_fifo_push(command_byte); - } - LOGMASKED(LOG_COMMANDS, " (%d)\n", m_transfer_count); - break; - - case S_PHASE_DATA_OUT: - case S_PHASE_DATA_IN: - next_state = INIT_XFR; - break; - - case S_PHASE_STATUS: - next_state = INIT_XFR; - m_regs[COMMAND_PHASE] = COMMAND_PHASE_RECEIVE_STATUS; - break; - - case S_PHASE_MSG_IN: - next_state = INIT_XFR; - break; - - default: - fatalerror("%s: Unhandled phase in Select-w/Atn-and-Transfer.\n", shortname()); - next_state = FINISHED; - break; - } - } - else if (cc == COMMAND_CC_TRANSFER_INFO) { - next_state = FINISHED; - irq_fifo_push(SCSI_STATUS_TRANSFER_SUCCESS | xfr_phase); - } - else { - fatalerror("%s: Unhandled command in data phase.\n", shortname()); - next_state = FINISHED; - } + case SM_DISCONNECT: + m_regs[COMMAND_PHASE] = COMMAND_PHASE_DISCONNECT_MESSAGE; break; default: - fatalerror("%s: Unhandled phase transition in INIT_XFR_WAIT_REQ.\n", shortname()); - next_state = FINISHED; + fatalerror("%s: Unhandled MSG_IN.\n", shortname()); break; } - - if (next_state != m_scsi_state) { - set_scsi_state(next_state); - ++m_step_count; - m_xfr_phase = xfr_phase; + } else if (m_regs[COMMAND_PHASE] < COMMAND_PHASE_COMMAND_COMPLETE) { + switch (msg) { + case SM_COMMAND_COMPLETE: + set_scsi_state(FINISHED); + irq_fifo_push(SCSI_STATUS_SELECT_TRANSFER_SUCCESS); + m_regs[COMMAND_PHASE] = COMMAND_PHASE_COMMAND_COMPLETE; + break; + default: + fatalerror("%s: Unhandled MSG_IN.\n", shortname()); + break; } } - break; - - case INIT_XFR_RECV_BYTE_ACK: - if (sat && m_xfr_phase == S_PHASE_MSG_IN) { - const uint8_t msg = data_fifo_pop(); - if (m_regs[COMMAND_PHASE] <= COMMAND_PHASE_CP_BYTES_C) { - switch (msg) { - case SM_SAVE_DATA_PTR: - set_scsi_state(FINISHED); - irq_fifo_push(SCSI_STATUS_SAVE_DATA_POINTERS); - m_regs[COMMAND_PHASE] = COMMAND_PHASE_SAVE_DATA_POINTER; - break; - - case SM_DISCONNECT: - m_regs[COMMAND_PHASE] = COMMAND_PHASE_DISCONNECT_MESSAGE; - break; - - default: - fatalerror("%s: Unhandled MSG_IN.\n", shortname()); - break; - } - } - else if (m_regs[COMMAND_PHASE] < COMMAND_PHASE_COMMAND_COMPLETE) { - switch (msg) { - case SM_COMMAND_COMPLETE: - set_scsi_state(FINISHED); - irq_fifo_push(SCSI_STATUS_SELECT_TRANSFER_SUCCESS); - m_regs[COMMAND_PHASE] = COMMAND_PHASE_COMMAND_COMPLETE; - break; - default: - fatalerror("%s: Unhandled MSG_IN.\n", shortname()); - break; - } - } - } - else { - set_scsi_state(INIT_XFR_WAIT_REQ); - } - scsi_bus->ctrl_w(scsi_refid, 0, S_ACK); - ++m_step_count; - break; - - default: - fatalerror("%s: Unhandled state in step.\n", shortname()); - break; + } else { + set_scsi_state(INIT_XFR_WAIT_REQ); } + scsi_bus->ctrl_w(scsi_refid, 0, S_ACK); + step(false); + break; - timeout = false; - - } while (--m_step_count); - - if (cycles) { - delay(cycles); + default: + fatalerror("%s: Unhandled state in step.\n", shortname()); + break; } } @@ -1390,7 +1390,7 @@ void wd33c9x_base_device::load_transfer_count() m_transfer_count = 1; } } - LOGMASKED(LOG_COMMANDS, "%s: Transfer Count %d bytes\n", shortname(), m_transfer_count); + LOGMASKED(LOG_COMMANDS, "Transfer Count %d bytes\n", m_transfer_count); } @@ -1499,7 +1499,9 @@ uint32_t wd33c9x_base_device::send_byte(const uint32_t value, const uint32_t mas void wd33c9x_base_device::set_scsi_state(uint16_t state) { - LOGMASKED(LOG_STEP, "%s: SCSI state change: %x to %x\n", shortname(), m_scsi_state, state); + LOGMASKED(LOG_STEP, "SCSI state change: %s.%s to %s.%s\n", + state_names[m_scsi_state & STATE_MASK], substate_names[m_scsi_state >> SUB_SHIFT], + state_names[state & STATE_MASK], substate_names[state >> SUB_SHIFT]); m_scsi_state = state; } @@ -1588,7 +1590,7 @@ void wd33c9x_base_device::update_irq() { if (m_regs[AUXILIARY_STATUS] & AUXILIARY_STATUS_INT) { m_regs[AUXILIARY_STATUS] &= ~AUXILIARY_STATUS_INT; - LOGMASKED(LOG_LINES, "%s: Clearing IRQ\n", shortname()); + LOGMASKED(LOG_LINES, "Clearing IRQ\n"); m_irq_cb(CLEAR_LINE); } if (!irq_fifo_empty()) { @@ -1612,7 +1614,7 @@ void wd33c9x_base_device::update_irq() } } - LOGMASKED(LOG_LINES, "%s: Asserting IRQ - SCSI Status (%02x)\n", shortname(), m_regs[SCSI_STATUS]); + LOGMASKED(LOG_LINES, "Asserting IRQ - SCSI Status (%02x)\n", m_regs[SCSI_STATUS]); m_irq_cb(ASSERT_LINE); } } @@ -1625,7 +1627,7 @@ void wd33c9x_base_device::update_irq() void wd33c9x_base_device::set_drq() { if (!m_drq_state) { - LOGMASKED(LOG_LINES, "%s: Asserting DRQ\n", shortname()); + LOGMASKED(LOG_LINES, "Asserting DRQ\n"); m_drq_state = true; m_drq_cb(ASSERT_LINE); } @@ -1639,7 +1641,7 @@ void wd33c9x_base_device::set_drq() void wd33c9x_base_device::clear_drq() { if (m_drq_state) { - LOGMASKED(LOG_LINES, "%s: Clearing DRQ\n", shortname()); + LOGMASKED(LOG_LINES, "Clearing DRQ\n"); m_drq_state = false; m_drq_cb(CLEAR_LINE); } @@ -1695,7 +1697,7 @@ bool wd33c9x_base_device::set_command_length(const uint8_t cc) } ret = true; } - LOGMASKED(LOG_COMMANDS, "%s: SCSI Command Length %d bytes\n", shortname(), m_command_length); + LOGMASKED(LOG_COMMANDS, "SCSI Command Length %d bytes\n", m_command_length); return ret; } diff --git a/src/devices/machine/wd33c9x.h b/src/devices/machine/wd33c9x.h index d5f3b5a5da4..bda117dbdc5 100644 --- a/src/devices/machine/wd33c9x.h +++ b/src/devices/machine/wd33c9x.h @@ -48,6 +48,8 @@ protected: virtual void scsi_ctrl_changed() override; private: + static const char *const state_names[]; + static const char *const substate_names[]; static constexpr uint8_t NUM_REGS = 0x20; static constexpr uint8_t REGS_MASK = NUM_REGS - 1; uint8_t m_addr; @@ -62,7 +64,6 @@ private: uint16_t m_scsi_state; uint8_t m_mode; uint8_t m_xfr_phase; - uint8_t m_step_count; void load_transfer_count(); bool decrement_transfer_count(); diff --git a/src/emu/dislot.h b/src/emu/dislot.h index 154e7452b10..3154a056f35 100644 --- a/src/emu/dislot.h +++ b/src/emu/dislot.h @@ -133,6 +133,7 @@ public: device_t *get_card_device() const { return m_card_device; } void set_card_device(device_t *dev) { m_card_device = dev; } const char *slot_name() const { return device().tag() + 1; } + slot_option &option_set(const char *tag, const device_type &devtype) { m_default_option = tag; m_fixed = true; return option_add_internal(tag, devtype); } protected: void set_default_clock(u32 clock) { m_default_clock = clock; } diff --git a/src/mame/drivers/cps3.cpp b/src/mame/drivers/cps3.cpp index 10f9558b8e2..e2e7105dd79 100644 --- a/src/mame/drivers/cps3.cpp +++ b/src/mame/drivers/cps3.cpp @@ -464,9 +464,8 @@ hardware modification to the security cart..... #include "machine/intelfsh.h" #include "machine/nvram.h" #include "includes/cps3.h" -#include "bus/scsi/scsi.h" -#include "bus/scsi/scsicd.h" -#include "machine/wd33c93.h" +#include "machine/nscsi_cd.h" +#include "machine/wd33c9x.h" #include "screen.h" #include "speaker.h" @@ -2177,7 +2176,7 @@ void cps3_state::cps3_map(address_map &map) map(0x05100000, 0x05100003).w(FUNC(cps3_state::cps3_irq12_ack_w)); map(0x05110000, 0x05110003).w(FUNC(cps3_state::cps3_irq10_ack_w)); - map(0x05140000, 0x05140003).rw("wd33c93", FUNC(wd33c93_device::read), FUNC(wd33c93_device::write)).umask32(0x00ff00ff); + map(0x05140000, 0x05140003).rw("scsi:7:wd33c93", FUNC(wd33c93n_device::indir_r), FUNC(wd33c93n_device::indir_w)).umask32(0x00ff00ff); map(0x06000000, 0x067fffff).rw(FUNC(cps3_state::cps3_flash1_r), FUNC(cps3_state::cps3_flash1_w)); /* Flash ROMs simm 1 */ map(0x06800000, 0x06ffffff).rw(FUNC(cps3_state::cps3_flash2_r), FUNC(cps3_state::cps3_flash2_w)); /* Flash ROMs simm 2 */ @@ -2510,11 +2509,9 @@ void cps3_state::cps3(machine_config &config) m_maincpu->set_periodic_int(FUNC(cps3_state::cps3_other_interrupt), attotime::from_hz(80)); /* ?source? */ m_maincpu->set_dma_kludge_callback(FUNC(cps3_state::dma_callback)); - scsi_port_device &scsi(SCSI_PORT(config, "scsi")); - scsi.set_slot_device(1, "cdrom", SCSICD, DEVICE_INPUT_DEFAULTS_NAME(SCSI_ID_1)); - - wd33c93_device& wd33c93(WD33C93(config, "wd33c93")); - wd33c93.set_scsi_port("scsi"); + NSCSI_BUS(config, "scsi"); + NSCSI_CONNECTOR(config, "scsi:1").option_set("cdrom", NSCSI_CDROM); + NSCSI_CONNECTOR(config, "scsi:7").option_set("wd33c93", WD33C93A).clock(10'000'000); /* video hardware */ screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); @@ -2613,7 +2610,7 @@ ROM_START( redearth ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "redearth_euro.29f400.u2", 0x000000, 0x080000, CRC(02e0f336) SHA1(acc37e830dfeb9674f5a0fb24f4cc23217ae4ff5) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-wzd-5", 0, BAD_DUMP SHA1(e5676752b08283dc4a98c3d7b759e8aa6dcd0679) ) ROM_END @@ -2621,7 +2618,7 @@ ROM_START( redearthr1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "redearth_euro.29f400.u2", 0x000000, 0x080000, CRC(02e0f336) SHA1(acc37e830dfeb9674f5a0fb24f4cc23217ae4ff5) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-wzd-3", 0, SHA1(a6ff67093db6bc80ee5fc46e4300e0177b213a52) ) ROM_END @@ -2629,7 +2626,7 @@ ROM_START( warzard ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "warzard_japan.29f400.u2", 0x000000, 0x080000, CRC(f8e2f0c6) SHA1(93d6a986f44c211fff014e55681eca4d2a2774d6) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-wzd-5", 0, BAD_DUMP SHA1(e5676752b08283dc4a98c3d7b759e8aa6dcd0679) ) ROM_END @@ -2637,7 +2634,7 @@ ROM_START( warzardr1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "warzard_japan.29f400.u2", 0x000000, 0x080000, CRC(f8e2f0c6) SHA1(93d6a986f44c211fff014e55681eca4d2a2774d6) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-wzd-3", 0, SHA1(a6ff67093db6bc80ee5fc46e4300e0177b213a52) ) ROM_END @@ -2646,7 +2643,7 @@ ROM_START( sfiii ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii_euro.29f400.u2", 0x000000, 0x080000, CRC(27699ddc) SHA1(d8b525cd27e584560b129598df31fd2c5b2a682a) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-sf3-3", 0, BAD_DUMP SHA1(606e62cc5f46275e366e7dbb412dbaeb7e54cd0c) ) ROM_END @@ -2654,7 +2651,7 @@ ROM_START( sfiiiu ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii_usa_region_b1.29f400.u2", 0x000000, 0x080000, CRC(fb172a8e) SHA1(48ebf59910f246835f7dc0c588da30f7a908072f) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-sf3-3", 0, BAD_DUMP SHA1(606e62cc5f46275e366e7dbb412dbaeb7e54cd0c) ) ROM_END @@ -2662,7 +2659,7 @@ ROM_START( sfiiia ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii_asia_region_bd.29f400.u2", 0x000000, 0x080000, CRC(cbd28de7) SHA1(9c15ecb73b9587d20850e62e8683930a45caa01b) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-sf3-3", 0, BAD_DUMP SHA1(606e62cc5f46275e366e7dbb412dbaeb7e54cd0c) ) ROM_END @@ -2670,7 +2667,7 @@ ROM_START( sfiiij ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii_japan.29f400.u2", 0x000000, 0x080000, CRC(74205250) SHA1(c3e83ace7121d32da729162662ec6b5285a31211) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-sf3-3", 0, BAD_DUMP SHA1(606e62cc5f46275e366e7dbb412dbaeb7e54cd0c) ) ROM_END @@ -2678,7 +2675,7 @@ ROM_START( sfiiih ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii_hispanic.29f400.u2", 0x000000, 0x080000, CRC(d2b3cd48) SHA1(00ebb270c24a66515c97e35331de54ff5358000e) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-sf3-3", 0, BAD_DUMP SHA1(606e62cc5f46275e366e7dbb412dbaeb7e54cd0c) ) ROM_END @@ -2687,7 +2684,7 @@ ROM_START( sfiii2 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii2_usa.29f400.u2", 0x000000, 0x080000, CRC(75dd72e0) SHA1(5a12d6ea6734df5de00ecee6f9ef470749d2f242) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-3ga000", 0, BAD_DUMP SHA1(4e162885b0b3265a56e0265037bcf247e820f027) ) ROM_END @@ -2695,7 +2692,7 @@ ROM_START( sfiii2j ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii2_japan.29f400.u2", 0x000000, 0x080000, CRC(faea0a3e) SHA1(a03cd63bcf52e4d57f7a598c8bc8e243694624ec) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-3ga000", 0, BAD_DUMP SHA1(4e162885b0b3265a56e0265037bcf247e820f027) ) ROM_END @@ -2704,7 +2701,7 @@ ROM_START( jojo ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojo_usa.29f400.u2", 0x000000, 0x080000, CRC(8d40f7be) SHA1(2a4bd83db2f959c33b071e517941aa55a0f919c0) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjk-3", 0, SHA1(dc6e74b5e02e13f62cb8c4e234dd6061501e49c1) ) ROM_END @@ -2712,7 +2709,7 @@ ROM_START( jojor1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojo_usa.29f400.u2", 0x000000, 0x080000, CRC(8d40f7be) SHA1(2a4bd83db2f959c33b071e517941aa55a0f919c0) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjk-2", 0, BAD_DUMP SHA1(0f5c09171409213e191a607ee89ca3a91fe9c96a) ) ROM_END @@ -2720,7 +2717,7 @@ ROM_START( jojor2 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojo_usa.29f400.u2", 0x000000, 0x080000, CRC(8d40f7be) SHA1(2a4bd83db2f959c33b071e517941aa55a0f919c0) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjk000", 0, BAD_DUMP SHA1(09869f6d8c032b527e02d815749dc8fab1289e86) ) ROM_END @@ -2728,7 +2725,7 @@ ROM_START( jojoj ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojo_japan.29f400.u2", 0x000000, 0x080000, CRC(02778f60) SHA1(a167f9ebe030592a0cdb0c6a3c75835c6a43be4c) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjk-3", 0, SHA1(dc6e74b5e02e13f62cb8c4e234dd6061501e49c1) ) ROM_END @@ -2736,7 +2733,7 @@ ROM_START( jojojr1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojo_japan.29f400.u2", 0x000000, 0x080000, CRC(02778f60) SHA1(a167f9ebe030592a0cdb0c6a3c75835c6a43be4c) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjk-2", 0, BAD_DUMP SHA1(0f5c09171409213e191a607ee89ca3a91fe9c96a) ) ROM_END @@ -2744,7 +2741,7 @@ ROM_START( jojojr2 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojo_japan.29f400.u2", 0x000000, 0x080000, CRC(02778f60) SHA1(a167f9ebe030592a0cdb0c6a3c75835c6a43be4c) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjk000", 0, BAD_DUMP SHA1(09869f6d8c032b527e02d815749dc8fab1289e86) ) ROM_END @@ -2753,7 +2750,7 @@ ROM_START( sfiii3 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii3_euro.29f400.u2", 0x000000, 0x080000, CRC(30bbf293) SHA1(f094c2eeaf4f6709060197aca371a4532346bf78) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-33s-2", 0, BAD_DUMP SHA1(41b0e246db91cbfc3f8f0f62d981734feb4b4ab5) ) ROM_END @@ -2761,7 +2758,7 @@ ROM_START( sfiii3r1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii3_euro.29f400.u2", 0x000000, 0x080000, CRC(30bbf293) SHA1(f094c2eeaf4f6709060197aca371a4532346bf78) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-33s-1", 0, BAD_DUMP SHA1(2f4a9006a31903114f9f9dc09465ae253e565c51) ) ROM_END @@ -2769,7 +2766,7 @@ ROM_START( sfiii3u ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii3_usa.29f400.u2", 0x000000, 0x080000, CRC(ecc545c1) SHA1(e39083820aae914fd8b80c9765129bedb745ceba) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-33s-2", 0, BAD_DUMP SHA1(41b0e246db91cbfc3f8f0f62d981734feb4b4ab5) ) ROM_END @@ -2777,7 +2774,7 @@ ROM_START( sfiii3ur1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii3_usa.29f400.u2", 0x000000, 0x080000, CRC(ecc545c1) SHA1(e39083820aae914fd8b80c9765129bedb745ceba) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-33s-1", 0, BAD_DUMP SHA1(2f4a9006a31903114f9f9dc09465ae253e565c51) ) ROM_END @@ -2785,7 +2782,7 @@ ROM_START( sfiii3j ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii3_japan.29f400.u2", 0x000000, 0x080000, CRC(63f23d1f) SHA1(58559403c325454f8c8d3eb0f569a531aa22db26) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-33s-2", 0, BAD_DUMP SHA1(41b0e246db91cbfc3f8f0f62d981734feb4b4ab5) ) ROM_END @@ -2793,7 +2790,7 @@ ROM_START( sfiii3jr1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "sfiii3_japan.29f400.u2", 0x000000, 0x080000, CRC(63f23d1f) SHA1(58559403c325454f8c8d3eb0f569a531aa22db26) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-33s-1", 0, BAD_DUMP SHA1(2f4a9006a31903114f9f9dc09465ae253e565c51) ) ROM_END @@ -2802,7 +2799,7 @@ ROM_START( jojoba ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojoba_japan.29f400.u2", 0x000000, 0x080000, CRC(3085478c) SHA1(055eab1fc42816f370a44b17fd7e87ffcb10e8b7) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjm-1", 0, SHA1(8628d3fa555fbd5f4121082e925c1834b76c5e65) ) ROM_END @@ -2810,7 +2807,7 @@ ROM_START( jojobar1 ) ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "jojoba_japan.29f400.u2", 0x000000, 0x080000, CRC(3085478c) SHA1(055eab1fc42816f370a44b17fd7e87ffcb10e8b7) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "cap-jjm-0", 0, BAD_DUMP SHA1(0678a0baeb853dcff1d230c14f0873cc9f143d7b) ) ROM_END @@ -3671,7 +3668,7 @@ ROM_START( cps3boot ) // for cart with standard SH2 ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_hd6417095_sh2.u2", 0x000000, 0x080000, CRC(cb9bd5b0) SHA1(ea7ecb3deb69f5307a62d8f0d7d8e68d49013d07)) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "unicd-cps3_for_standard_sh2_v4", 0, SHA1(099c52bd38753f0f4876243e7aa87ca482a2dcb7) ) ROM_END @@ -3679,7 +3676,7 @@ ROM_START( cps3booto ) // for cart with standard SH2 ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_hd6417095_sh2.u2", 0x000000, 0x080000, CRC(cb9bd5b0) SHA1(ea7ecb3deb69f5307a62d8f0d7d8e68d49013d07)) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "no-battery_multi-game_bootleg_cd_for_hd6417095_sh2", 0, SHA1(6057cc3ec7991c0c00a7ab9da6ac2f92c9fb1aed) ) ROM_END @@ -3687,7 +3684,7 @@ ROM_START( cps3booto2 ) // for cart with standard SH2 ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_hd6417095_sh2.u2", 0x000000, 0x080000, CRC(cb9bd5b0) SHA1(ea7ecb3deb69f5307a62d8f0d7d8e68d49013d07)) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "no-battery_multi-game_bootleg_cd_for_hd6417095_sh2_older", 0, SHA1(123f2fcb0f3dd3d6b859e82a51d0127e46763776) ) ROM_END @@ -3695,7 +3692,7 @@ ROM_START( cps3bs32 ) // for cart with standard SH2 ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_hd6417095_sh2.u2", 0x000000, 0x080000, CRC(cb9bd5b0) SHA1(ea7ecb3deb69f5307a62d8f0d7d8e68d49013d07)) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "sfiii_2nd_impact_converted_for_standard_sh2_v3", 0, SHA1(8f180d159e88042a1e819cefd39eef67f5e86e3d) ) ROM_END @@ -3703,7 +3700,7 @@ ROM_START( cps3bs32a ) // for cart with standard SH2 ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_hd6417095_sh2.u2", 0x000000, 0x080000, CRC(cb9bd5b0) SHA1(ea7ecb3deb69f5307a62d8f0d7d8e68d49013d07)) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "sfiii_2nd_impact_converted_for_standard_sh2_older", 0, SHA1(8a8e4138c3bf12435933ab9d9ace510513200843) ) // v1 or v2? ROM_END @@ -3711,7 +3708,7 @@ ROM_START( cps3boota ) // for cart with dead custom SH2 (or 2nd Impact CPU which ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_dead_security_cart.u2", 0x000000, 0x080000, CRC(0fd56fb3) SHA1(5a8bffc07eb7da73cf4bca6718df72e471296bfd) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "unicd-cps3_for_custom_sh2_v5", 0, SHA1(50a5b2845d3dd3de3bce15c4f1b58500db80cabe) ) ROM_END @@ -3719,7 +3716,7 @@ ROM_START( cps3bootao ) // for cart with dead custom SH2 (or 2nd Impact CPU whic ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_dead_security_cart.u2", 0x000000, 0x080000, CRC(0fd56fb3) SHA1(5a8bffc07eb7da73cf4bca6718df72e471296bfd) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "no-battery_multi-game_bootleg_cd_for_dead_security_cart", 0, SHA1(1ede2f1ba197ee787208358a13eae7185a5ae3b2) ) ROM_END @@ -3728,7 +3725,7 @@ ROM_START( cps3bootao2 ) // for cart with dead custom SH2 (or 2nd Impact CPU whi ROM_REGION32_BE( 0x080000, "bios", 0 ) /* bios region */ ROM_LOAD( "no-battery_bios_29f400_for_dead_security_cart.u2", 0x000000, 0x080000, CRC(0fd56fb3) SHA1(5a8bffc07eb7da73cf4bca6718df72e471296bfd) ) - DISK_REGION( "scsi:" SCSI_PORT_DEVICE1 ":cdrom" ) + DISK_REGION( "scsi:1:cdrom" ) DISK_IMAGE_READONLY( "no-battery_multi-game_bootleg_cd_for_dead_security_cart_older", 0, SHA1(4b0b673b45dac94da018576c0a7f8644653fc564) ) ROM_END