Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-07 17:27:06 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

Cleanups and version bump.

Browse Source
This commit is contained in:
Aaron Giles 2009-12-31 22:03:37 +00:00
parent 367c1d7524
commit 289a309cd3
44 changed files with 2159 additions and 2159 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/emu/cpu/drcbex86.c
View File

@ -2897,7 +2897,7 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN
{ {
emit_link skip1, skip2; emit_link skip1, skip2;
int tempreg = REG_EAX; int tempreg = REG_EAX;
// emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx // emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx
emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param
emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20
emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1
@ -2922,7 +2922,7 @@ static void emit_rol_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN
emit_shld_r32_r32_cl(dst, reglo, reghi); // shld reglo,reghi,cl emit_shld_r32_r32_cl(dst, reglo, reghi); // shld reglo,reghi,cl
if (saveflags) emit_pushf(dst); // pushf if (saveflags) emit_pushf(dst); // pushf
emit_shld_r32_r32_cl(dst, reghi, tempreg); // shld reghi,ebx,cl emit_shld_r32_r32_cl(dst, reghi, tempreg); // shld reghi,ebx,cl
// emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8] // emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8]
} }
if (saveflags) if (saveflags)
emit_combine_z_flags(dst); emit_combine_z_flags(dst);
@ -2972,7 +2972,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN
{ {
emit_link skip1, skip2; emit_link skip1, skip2;
int tempreg = REG_EAX; int tempreg = REG_EAX;
// emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx // emit_mov_m32_r32(dst, MBD(REG_ESP, -8), tempreg); // mov [esp-8],ebx
emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param emit_mov_r32_p32(drcbe, dst, REG_ECX, param); // mov ecx,param
emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20 emit_test_r32_imm(dst, REG_ECX, 0x20); // test ecx,0x20
emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1 emit_jcc_short_link(dst, COND_Z, &skip1); // jz skip1
@ -2997,7 +2997,7 @@ static void emit_ror_r64_p64(drcbe_state *drcbe, x86code **dst, UINT8 reglo, UIN
emit_shrd_r32_r32_cl(dst, reglo, reghi); // shrd reglo,reghi,cl emit_shrd_r32_r32_cl(dst, reglo, reghi); // shrd reglo,reghi,cl
if (saveflags) emit_pushf(dst); // pushf if (saveflags) emit_pushf(dst); // pushf
emit_shrd_r32_r32_cl(dst, reghi, tempreg); // shrd reghi,ebx,cl emit_shrd_r32_r32_cl(dst, reghi, tempreg); // shrd reghi,ebx,cl
// emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8] // emit_mov_r32_m32(dst, tempreg, MBD(REG_ESP, saveflags ? -4 : -8)); // mov ebx,[esp-8]
} }
if (saveflags) if (saveflags)
emit_combine_z_flags(dst); emit_combine_z_flags(dst);

6
src/emu/cpu/rsp/rsp.h
View File

@ -113,10 +113,10 @@ void rspdrc_add_dmem(const device_config *device, void *base);
#define FSREG ((op >> 11) & 31) #define FSREG ((op >> 11) & 31)
#define FDREG ((op >> 6) & 31) #define FDREG ((op >> 6) & 31)
#define IS_SINGLE(o) (((o) & (1 << 21)) == 0) #define IS_SINGLE(o) (((o) & (1 << 21)) == 0)
#define IS_DOUBLE(o) (((o) & (1 << 21)) != 0) #define IS_DOUBLE(o) (((o) & (1 << 21)) != 0)
#define IS_FLOAT(o) (((o) & (1 << 23)) == 0) #define IS_FLOAT(o) (((o) & (1 << 23)) == 0)
#define IS_INTEGRAL(o) (((o) & (1 << 23)) != 0) #define IS_INTEGRAL(o) (((o) & (1 << 23)) != 0)
#define SIMMVAL ((INT16)op) #define SIMMVAL ((INT16)op)
#define UIMMVAL ((UINT16)op) #define UIMMVAL ((UINT16)op)

3564
src/emu/cpu/rsp/rspdrc.c
View File

File diff suppressed because it is too large Load Diff

2
src/mame/drivers/darius.c
View File

@ -810,7 +810,7 @@ static const ym2203_interface ym2203_interface_2 =
static const pc080sn_interface darius_pc080sn_intf = static const pc080sn_interface darius_pc080sn_intf =
{ {
1, /* gfxnum */ 1, /* gfxnum */
-16, 8, 0, 1 /* x_offset, y_offset, y_invert, dblwidth */ -16, 8, 0, 1 /* x_offset, y_offset, y_invert, dblwidth */
}; };
static MACHINE_DRIVER_START( darius ) static MACHINE_DRIVER_START( darius )

8
src/mame/drivers/deco32.c
View File

@ -774,14 +774,14 @@ static ADDRESS_MAP_START( dragngun_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x138000, 0x138003) AM_NOP /* Palette dma complete in bit 0x8? ack? return 0 else tight loop */ AM_RANGE(0x138000, 0x138003) AM_NOP /* Palette dma complete in bit 0x8? ack? return 0 else tight loop */
AM_RANGE(0x138008, 0x13800b) AM_WRITE(deco32_palette_dma_w) AM_RANGE(0x138008, 0x13800b) AM_WRITE(deco32_palette_dma_w)
// AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control) // AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control)
AM_RANGE(0x180000, 0x18001f) AM_RAM AM_BASE(&deco32_pf12_control) AM_RANGE(0x180000, 0x18001f) AM_RAM AM_BASE(&deco32_pf12_control)
AM_RANGE(0x190000, 0x191fff) AM_RAM_WRITE(deco32_pf1_data_w) AM_BASE(&deco32_pf1_data) AM_RANGE(0x190000, 0x191fff) AM_RAM_WRITE(deco32_pf1_data_w) AM_BASE(&deco32_pf1_data)
AM_RANGE(0x194000, 0x195fff) AM_RAM_WRITE(deco32_pf2_data_w) AM_BASE(&deco32_pf2_data) AM_RANGE(0x194000, 0x195fff) AM_RAM_WRITE(deco32_pf2_data_w) AM_BASE(&deco32_pf2_data)
AM_RANGE(0x1a0000, 0x1a0fff) AM_RAM AM_BASE(&deco32_pf1_rowscroll) AM_RANGE(0x1a0000, 0x1a0fff) AM_RAM AM_BASE(&deco32_pf1_rowscroll)
AM_RANGE(0x1a4000, 0x1a4fff) AM_RAM AM_BASE(&deco32_pf2_rowscroll) AM_RANGE(0x1a4000, 0x1a4fff) AM_RAM AM_BASE(&deco32_pf2_rowscroll)
// AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control) // AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control)
AM_RANGE(0x1c0000, 0x1c001f) AM_RAM AM_BASE(&deco32_pf34_control) AM_RANGE(0x1c0000, 0x1c001f) AM_RAM AM_BASE(&deco32_pf34_control)
AM_RANGE(0x1d0000, 0x1d1fff) AM_RAM_WRITE(deco32_pf3_data_w) AM_BASE(&deco32_pf3_data) AM_RANGE(0x1d0000, 0x1d1fff) AM_RAM_WRITE(deco32_pf3_data_w) AM_BASE(&deco32_pf3_data)
AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_data_w) AM_BASE(&deco32_pf4_data) AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_data_w) AM_BASE(&deco32_pf4_data)
@ -827,14 +827,14 @@ static ADDRESS_MAP_START( lockload_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x170000, 0x170007) AM_READ(lockload_gun_mirror_r) /* Not on Dragongun */ AM_RANGE(0x170000, 0x170007) AM_READ(lockload_gun_mirror_r) /* Not on Dragongun */
AM_RANGE(0x178008, 0x17800f) AM_WRITENOP /* Gun read ACK's */ AM_RANGE(0x178008, 0x17800f) AM_WRITENOP /* Gun read ACK's */
// AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control) // AM_RANGE(0x180000, 0x18001f) AM_RAM_WRITE(deco32_pf12_control_w) AM_BASE(&deco32_pf12_control)
AM_RANGE(0x180000, 0x18001f) AM_RAM AM_BASE(&deco32_pf12_control) AM_RANGE(0x180000, 0x18001f) AM_RAM AM_BASE(&deco32_pf12_control)
AM_RANGE(0x190000, 0x191fff) AM_RAM_WRITE(deco32_pf1_data_w) AM_BASE(&deco32_pf1_data) AM_RANGE(0x190000, 0x191fff) AM_RAM_WRITE(deco32_pf1_data_w) AM_BASE(&deco32_pf1_data)
AM_RANGE(0x194000, 0x195fff) AM_RAM_WRITE(deco32_pf2_data_w) AM_BASE(&deco32_pf2_data) AM_RANGE(0x194000, 0x195fff) AM_RAM_WRITE(deco32_pf2_data_w) AM_BASE(&deco32_pf2_data)
AM_RANGE(0x1a0000, 0x1a0fff) AM_RAM AM_BASE(&deco32_pf1_rowscroll) AM_RANGE(0x1a0000, 0x1a0fff) AM_RAM AM_BASE(&deco32_pf1_rowscroll)
AM_RANGE(0x1a4000, 0x1a4fff) AM_RAM AM_BASE(&deco32_pf2_rowscroll) AM_RANGE(0x1a4000, 0x1a4fff) AM_RAM AM_BASE(&deco32_pf2_rowscroll)
// AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control) // AM_RANGE(0x1c0000, 0x1c001f) AM_RAM_WRITE(deco32_pf34_control_w) AM_BASE(&deco32_pf34_control)
AM_RANGE(0x1c0000, 0x1c001f) AM_RAM AM_BASE(&deco32_pf34_control) AM_RANGE(0x1c0000, 0x1c001f) AM_RAM AM_BASE(&deco32_pf34_control)
AM_RANGE(0x1d0000, 0x1d1fff) AM_RAM_WRITE(deco32_pf3_data_w) AM_BASE(&deco32_pf3_data) AM_RANGE(0x1d0000, 0x1d1fff) AM_RAM_WRITE(deco32_pf3_data_w) AM_BASE(&deco32_pf3_data)
AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_data_w) AM_BASE(&deco32_pf4_data) AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_data_w) AM_BASE(&deco32_pf4_data)

2
src/mame/drivers/galastrm.c
View File

@ -310,7 +310,7 @@ static const tc0100scn_interface galastrm_tc0100scn_intf =
static const tc0480scp_interface galastrm_tc0480scp_intf = static const tc0480scp_interface galastrm_tc0480scp_intf =
{ {
1, 3, /* gfxnum, txnum */ 1, 3, /* gfxnum, txnum */
0, /* pixels */ 0, /* pixels */
-40, -3, /* x_offset, y_offset */ -40, -3, /* x_offset, y_offset */
0, 0, /* text_xoff, text_yoff */ 0, 0, /* text_xoff, text_yoff */
0, 0, /* flip_xoff, flip_yoff */ 0, 0, /* flip_xoff, flip_yoff */

2
src/mame/drivers/groundfx.c
View File

@ -354,7 +354,7 @@ static const tc0100scn_interface groundfx_tc0100scn_intf =
static const tc0480scp_interface groundfx_tc0480scp_intf = static const tc0480scp_interface groundfx_tc0480scp_intf =
{ {
1, 4, /* gfxnum, txnum */ 1, 4, /* gfxnum, txnum */
0, /* pixels */ 0, /* pixels */
0x24, 0, /* x_offset, y_offset */ 0x24, 0, /* x_offset, y_offset */
-1, 0, /* text_xoff, text_yoff */ -1, 0, /* text_xoff, text_yoff */
0, 0, /* flip_xoff, flip_yoff */ 0, 0, /* flip_xoff, flip_yoff */

2
src/mame/drivers/gunbustr.c
View File

@ -317,7 +317,7 @@ static const eeprom_interface gunbustr_eeprom_interface =
static const tc0480scp_interface gunbustr_tc0480scp_intf = static const tc0480scp_interface gunbustr_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
0, /* pixels */ 0, /* pixels */
0x20, 0x07, /* x_offset, y_offset */ 0x20, 0x07, /* x_offset, y_offset */
-1, -1, /* text_xoff, text_yoff */ -1, -1, /* text_xoff, text_yoff */
-1, 0, /* flip_xoff, flip_yoff */ -1, 0, /* flip_xoff, flip_yoff */

2
src/mame/drivers/opwolf.c
View File

@ -711,7 +711,7 @@ static const msm5205_interface msm5205_config =
static const pc080sn_interface opwolf_pc080sn_intf = static const pc080sn_interface opwolf_pc080sn_intf =
{ {
1, /* gfxnum */ 1, /* gfxnum */
0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */
}; };
static const pc090oj_interface opwolf_pc090oj_intf = static const pc090oj_interface opwolf_pc090oj_intf =

4
src/mame/drivers/rainbow.c
View File

@ -650,13 +650,13 @@ static const ym2151_interface ym2151_config =
static const pc080sn_interface rainbow_pc080sn_intf = static const pc080sn_interface rainbow_pc080sn_intf =
{ {
1, /* gfxnum */ 1, /* gfxnum */
0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */
}; };
static const pc080sn_interface jumping_pc080sn_intf = static const pc080sn_interface jumping_pc080sn_intf =
{ {
1, /* gfxnum */ 1, /* gfxnum */
0, 0, 1, 0 /* x_offset, y_offset, y_invert, dblwidth */ 0, 0, 1, 0 /* x_offset, y_offset, y_invert, dblwidth */
}; };
static const pc090oj_interface rainbow_pc090oj_intf = static const pc090oj_interface rainbow_pc090oj_intf =

2
src/mame/drivers/rastan.c
View File

@ -383,7 +383,7 @@ static MACHINE_RESET( rastan )
static const pc080sn_interface rastan_pc080sn_intf = static const pc080sn_interface rastan_pc080sn_intf =
{ {
0, /* gfxnum */ 0, /* gfxnum */
0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ 0, 0, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */
}; };
static const pc090oj_interface rastan_pc090oj_intf = static const pc090oj_interface rastan_pc090oj_intf =

2
src/mame/drivers/slapshot.c
View File

@ -498,7 +498,7 @@ static const ym2610_interface ym2610_config =
static const tc0480scp_interface slapshot_tc0480scp_intf = static const tc0480scp_interface slapshot_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
3, /* pixels */ 3, /* pixels */
30, 9, /* x_offset, y_offset */ 30, 9, /* x_offset, y_offset */
-1, 1, /* text_xoff, text_yoff */ -1, 1, /* text_xoff, text_yoff */
0, 2, /* flip_xoff, flip_yoff */ 0, 2, /* flip_xoff, flip_yoff */

2
src/mame/drivers/superchs.c
View File

@ -363,7 +363,7 @@ static const eeprom_interface superchs_eeprom_interface =
static const tc0480scp_interface superchs_tc0480scp_intf = static const tc0480scp_interface superchs_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
0, /* pixels */ 0, /* pixels */
0x20, 0x08, /* x_offset, y_offset */ 0x20, 0x08, /* x_offset, y_offset */
-1, 0, /* text_xoff, text_yoff */ -1, 0, /* text_xoff, text_yoff */
0, 0, /* flip_xoff, flip_yoff */ 0, 0, /* flip_xoff, flip_yoff */

10
src/mame/drivers/taito_f2.c
View File

@ -3265,7 +3265,7 @@ static const tc0100scn_interface thundfox_tc0100scn_intf_2 =
static const tc0480scp_interface footchmp_tc0480scp_intf = static const tc0480scp_interface footchmp_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
3, /* pixels */ 3, /* pixels */
0x1d, 0x08, /* x_offset, y_offset */ 0x1d, 0x08, /* x_offset, y_offset */
-1, 0, /* text_xoff, text_yoff */ -1, 0, /* text_xoff, text_yoff */
-1, 0, /* flip_xoff, flip_yoff */ -1, 0, /* flip_xoff, flip_yoff */
@ -3275,7 +3275,7 @@ static const tc0480scp_interface footchmp_tc0480scp_intf =
static const tc0480scp_interface hthero_tc0480scp_intf = static const tc0480scp_interface hthero_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
3, /* pixels */ 3, /* pixels */
0x33, -0x04, /* x_offset, y_offset */ 0x33, -0x04, /* x_offset, y_offset */
-1, 0, /* text_xoff, text_yoff */ -1, 0, /* text_xoff, text_yoff */
-1, 0, /* flip_xoff, flip_yoff */ -1, 0, /* flip_xoff, flip_yoff */
@ -3285,7 +3285,7 @@ static const tc0480scp_interface hthero_tc0480scp_intf =
static const tc0480scp_interface deadconx_tc0480scp_intf = static const tc0480scp_interface deadconx_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
3, /* pixels */ 3, /* pixels */
0x1e, 0x08, /* x_offset, y_offset */ 0x1e, 0x08, /* x_offset, y_offset */
-1, 0, /* text_xoff, text_yoff */ -1, 0, /* text_xoff, text_yoff */
-1, 0, /* flip_xoff, flip_yoff */ -1, 0, /* flip_xoff, flip_yoff */
@ -3295,7 +3295,7 @@ static const tc0480scp_interface deadconx_tc0480scp_intf =
static const tc0480scp_interface deadconxj_tc0480scp_intf = static const tc0480scp_interface deadconxj_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
3, /* pixels */ 3, /* pixels */
0x34, -0x05, /* x_offset, y_offset */ 0x34, -0x05, /* x_offset, y_offset */
-1, 0, /* text_xoff, text_yoff */ -1, 0, /* text_xoff, text_yoff */
-1, 0, /* flip_xoff, flip_yoff */ -1, 0, /* flip_xoff, flip_yoff */
@ -3305,7 +3305,7 @@ static const tc0480scp_interface deadconxj_tc0480scp_intf =
static const tc0480scp_interface metalb_tc0480scp_intf = static const tc0480scp_interface metalb_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
3, /* pixels */ 3, /* pixels */
0x32, -0x04, /* x_offset, y_offset */ 0x32, -0x04, /* x_offset, y_offset */
1, 0, /* text_xoff, text_yoff */ 1, 0, /* text_xoff, text_yoff */
-1, 0, /* flip_xoff, flip_yoff */ -1, 0, /* flip_xoff, flip_yoff */

2
src/mame/drivers/taito_z.c
View File

@ -2902,7 +2902,7 @@ static const tc0100scn_interface spacegun_tc0100scn_intf =
static const tc0480scp_interface taitoz_tc0480scp_intf = static const tc0480scp_interface taitoz_tc0480scp_intf =
{ {
1, 2, /* gfxnum, txnum */ 1, 2, /* gfxnum, txnum */
0, /* pixels */ 0, /* pixels */
0x21, 0x08, /* x_offset, y_offset */ 0x21, 0x08, /* x_offset, y_offset */
4, 0, /* text_xoff, text_yoff */ 4, 0, /* text_xoff, text_yoff */
0, 0, /* flip_xoff, flip_yoff */ 0, 0, /* flip_xoff, flip_yoff */

2
src/mame/drivers/topspeed.c
View File

@ -673,7 +673,7 @@ static MACHINE_RESET( topspeed )
static const pc080sn_interface topspeed_pc080sn_intf = static const pc080sn_interface topspeed_pc080sn_intf =
{ {
1, /* gfxnum */ 1, /* gfxnum */
0, 8, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */ 0, 8, 0, 0 /* x_offset, y_offset, y_invert, dblwidth */
}; };
static const tc0220ioc_interface topspeed_io_intf = static const tc0220ioc_interface topspeed_io_intf =

2
src/mame/drivers/undrfire.c
View File

@ -712,7 +712,7 @@ static const tc0100scn_interface undrfire_tc0100scn_intf =
static const tc0480scp_interface undrfire_tc0480scp_intf = static const tc0480scp_interface undrfire_tc0480scp_intf =
{ {
1, 4, /* gfxnum, txnum */ 1, 4, /* gfxnum, txnum */
0, /* pixels */ 0, /* pixels */
0x24, 0, /* x_offset, y_offset */ 0x24, 0, /* x_offset, y_offset */
-1, 0, /* text_xoff, text_yoff */ -1, 0, /* text_xoff, text_yoff */
0, 0, /* flip_xoff, flip_yoff */ 0, 0, /* flip_xoff, flip_yoff */

2
src/mame/machine/snes.c
View File

@ -178,7 +178,7 @@ static TIMER_CALLBACK( snes_scanline_tick )
timer_adjust_oneshot(snes_hirq_timer, video_screen_get_time_until_pos(machine->primary_screen, snes_ppu.beam.current_vert, pixel*snes_htmult), 0); timer_adjust_oneshot(snes_hirq_timer, video_screen_get_time_until_pos(machine->primary_screen, snes_ppu.beam.current_vert, pixel*snes_htmult), 0);
} }
} }
} }
/* Start of VBlank */ /* Start of VBlank */
if( snes_ppu.beam.current_vert == snes_ppu.beam.last_visible_line ) if( snes_ppu.beam.current_vert == snes_ppu.beam.last_visible_line )

2
src/mame/machine/tait8741.c
View File

@ -604,7 +604,7 @@ static INT8 cyclemb_8741_r(const address_space *space,int num,int offset)
if(cyclemb_mcu.rst) if(cyclemb_mcu.rst)
{ {
/* FIXME: mame rands are supposedly parity checks or signals that the i8741 sends to the main z80 for telling him what kind of input /* FIXME: mame rands are supposedly parity checks or signals that the i8741 sends to the main z80 for telling him what kind of input
this specific packet contains. DSW3 surely contains something else too... */ this specific packet contains. DSW3 surely contains something else too... */
/* FIXME: remove cpu_get_pc hack */ /* FIXME: remove cpu_get_pc hack */
switch(cpu_get_pc(space->cpu)) switch(cpu_get_pc(space->cpu))
{ {

20
src/mame/video/hng64.c
View File

@ -2103,7 +2103,7 @@ void recoverPolygonBlock(running_machine* machine, const UINT16* packet, struct
// 24 word chunk, 3 vertices, per-vertex UVs // 24 word chunk, 3 vertices, per-vertex UVs
case 0x04: // 0000 0100 case 0x04: // 0000 0100
case 0x0e: // 0000 1110 case 0x0e: // 0000 1110
case 0x24: // 0010 0100 - TODO: I'm missing a lot of geo in the driving game intros case 0x24: // 0010 0100 - TODO: I'm missing a lot of geo in the driving game intros
case 0x2e: // 0010 1110 case 0x2e: // 0010 1110
for (m = 0; m < 3; m++) for (m = 0; m < 3; m++)
{ {
@ -2182,7 +2182,7 @@ void recoverPolygonBlock(running_machine* machine, const UINT16* packet, struct
// 12 word chunk, 1 vertex, per-vertex UVs // 12 word chunk, 1 vertex, per-vertex UVs
case 0x86: // 1000 0110 case 0x86: // 1000 0110
case 0x96: // 1001 0110 case 0x96: // 1001 0110
case 0xb6: // 1011 0110 - TODO: I'm missing a lot of geo in the driving game intros. case 0xb6: // 1011 0110 - TODO: I'm missing a lot of geo in the driving game intros.
case 0xc6: // 1100 0110 case 0xc6: // 1100 0110
case 0xd6: // 1101 0110 case 0xd6: // 1101 0110
// Copy over the proper vertices from the previous triangle... // Copy over the proper vertices from the previous triangle...
@ -2220,14 +2220,14 @@ void recoverPolygonBlock(running_machine* machine, const UINT16* packet, struct
// TODO: I'm not reading 3 necessary words here (maybe face normal) !!! // TODO: I'm not reading 3 necessary words here (maybe face normal) !!!
/* DEBUG /* DEBUG
printf("0x?6 : %08x (%d/%d)\n", address[k]*3*2, l, size[k]-1); printf("0x?6 : %08x (%d/%d)\n", address[k]*3*2, l, size[k]-1);
for (m = 0; m < 13; m++) for (m = 0; m < 13; m++)
printf("%04x ", threeDPointer[m]); printf("%04x ", threeDPointer[m]);
printf("\n"); printf("\n");
for (m = 0; m < 13; m++) for (m = 0; m < 13; m++)
printf("%3.4f ", uToF(threeDPointer[m])); printf("%3.4f ", uToF(threeDPointer[m]));
printf("\n\n"); printf("\n\n");
*/ */
chunkLength = 12; chunkLength = 12;
break; break;

106
src/mame/video/n64.c
View File

@ -10,7 +10,7 @@
#include "driver.h" #include "driver.h"
#include "includes/n64.h" #include "includes/n64.h"
#define LOG_RDP_EXECUTION 0 #define LOG_RDP_EXECUTION 0
static FILE *rdp_exec; static FILE *rdp_exec;
@ -1703,26 +1703,26 @@ INLINE void video_max(UINT32* Pixels, UINT8* max, UINT32* enb)
/* /*
INLINE void video_max(UINT32* Pixels, UINT8* max, UINT32* enb) INLINE void video_max(UINT32* Pixels, UINT8* max, UINT32* enb)
{ {
int i; int i;
int pos = 0; int pos = 0;
*enb = 0; *enb = 0;
for(i = 0; i < 7; i++) for(i = 0; i < 7; i++)
{ {
if (Pixels[i] > Pixels[pos]) if (Pixels[i] > Pixels[pos])
{ {
*enb += (1 << i); *enb += (1 << i);
pos = i; pos = i;
} }
else if (Pixels[i] < Pixels[pos]) else if (Pixels[i] < Pixels[pos])
{ {
*enb += (1 << i); *enb += (1 << i);
} }
else else
{ {
pos = i; pos = i;
} }
} }
*max = Pixels[pos]; *max = Pixels[pos];
} }
*/ */
@ -2519,7 +2519,7 @@ static void render_spans_32(int start, int end, TILE* tex_tile, int shade, int t
{ {
COLOR_COMBINER2_C0(c1); COLOR_COMBINER2_C0(c1);
COLOR_COMBINER2_C1(c2); COLOR_COMBINER2_C1(c2);
} }
if ((zbuffer || other_modes.z_source_sel) && other_modes.z_compare_en) if ((zbuffer || other_modes.z_source_sel) && other_modes.z_compare_en)
{ {
@ -3588,7 +3588,7 @@ static RDP_COMMAND( rdp_set_other_modes )
int index; int index;
other_modes.cycle_type = (w1 >> 20) & 0x3; other_modes.cycle_type = (w1 >> 20) & 0x3;
other_modes.persp_tex_en = (w1 & 0x80000) ? 1 : 0; other_modes.persp_tex_en = (w1 & 0x80000) ? 1 : 0;
other_modes.detail_tex_en = (w1 & 0x40000) ? 1 : 0; other_modes.detail_tex_en = (w1 & 0x40000) ? 1 : 0;
other_modes.sharpen_tex_en = (w1 & 0x20000) ? 1 : 0; other_modes.sharpen_tex_en = (w1 & 0x20000) ? 1 : 0;
other_modes.tex_lod_en = (w1 & 0x10000) ? 1 : 0; other_modes.tex_lod_en = (w1 & 0x10000) ? 1 : 0;
@ -4092,19 +4092,19 @@ static RDP_COMMAND( rdp_set_combine )
SET_SUB_ALPHA_INPUT(&combiner_alphaadd[1], combine.add_a1); SET_SUB_ALPHA_INPUT(&combiner_alphaadd[1], combine.add_a1);
/* /*
if(combiner_rgbsub_a_r[1] == &noise_color.i.r) if(combiner_rgbsub_a_r[1] == &noise_color.i.r)
{ {
COLOR_COMBINER1 = COLOR_COMBINER1_NOISE; COLOR_COMBINER1 = COLOR_COMBINER1_NOISE;
COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NOISE; COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NOISE;
COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NOISE; COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NOISE;
} }
else else
{ {
COLOR_COMBINER1 = COLOR_COMBINER1_NNOISE; COLOR_COMBINER1 = COLOR_COMBINER1_NNOISE;
COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NNOISE; COLOR_COMBINER2_C0 = COLOR_COMBINER2_C0_NNOISE;
COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NNOISE; COLOR_COMBINER2_C1 = COLOR_COMBINER2_C1_NNOISE;
} }
*/ */
} }
static RDP_COMMAND( rdp_set_texture_image ) static RDP_COMMAND( rdp_set_texture_image )
@ -4122,7 +4122,7 @@ static RDP_COMMAND( rdp_set_mask_image )
static RDP_COMMAND( rdp_set_color_image ) static RDP_COMMAND( rdp_set_color_image )
{ {
fb_format = (w1 >> 21) & 0x7; fb_format = (w1 >> 21) & 0x7;
fb_size = (w1 >> 19) & 0x3; fb_size = (w1 >> 19) & 0x3;
fb_width = (w1 & 0x3ff) + 1; fb_width = (w1 & 0x3ff) + 1;
fb_address = w2 & 0x01ffffff; fb_address = w2 & 0x01ffffff;
@ -4238,23 +4238,23 @@ void rdp_process_list(running_machine *machine)
//*out = cc_lut2[(cc_lut1[(*A << 16) | (*B << 8) | *C] << 8) | *D]; //*out = cc_lut2[(cc_lut1[(*A << 16) | (*B << 8) | *C] << 8) | *D];
/* /*
The slow, branchy version The slow, branchy version
INT32 color = (((*A-*B)* *C) + (*D << 8) + 0x80); INT32 color = (((*A-*B)* *C) + (*D << 8) + 0x80);
color >>= 8; color >>= 8;
if (color > 255) if (color > 255)
{ {
*out = 255; *out = 255;
} }
else if (color < 0) else if (color < 0)
{ {
*out = 0; *out = 0;
} }
else else
{ {
*out = (UINT8)color; *out = (UINT8)color;
} }
*/ */
//} //}
INLINE void BLENDER_EQUATION0_FORCE(INT32* r, INT32* g, INT32* b, int bsel_special) INLINE void BLENDER_EQUATION0_FORCE(INT32* r, INT32* g, INT32* b, int bsel_special)

48
src/mame/video/rdpblend.h
View File

@ -113,47 +113,47 @@ INLINE int BLENDER2_16_NIMR_NZC_AC_ND_NFORCE(UINT16 *fb, UINT8* hb, COLOR c1, CO
static int (*rdp_blender1_16_dith_func[32])(UINT16 *, UINT8 *, COLOR, int) = static int (*rdp_blender1_16_dith_func[32])(UINT16 *, UINT8 *, COLOR, int) =
{ {
BLENDER1_16_NIMR_NZC_NDITH_NAC_NFORCE, BLENDER1_16_NIMR_NZC_NDITH_AC_NFORCE, BLENDER1_16_NIMR_NZC_DITH_NAC_NFORCE, BLENDER1_16_NIMR_NZC_DITH_AC_NFORCE, BLENDER1_16_NIMR_NZC_NDITH_NAC_NFORCE, BLENDER1_16_NIMR_NZC_NDITH_AC_NFORCE, BLENDER1_16_NIMR_NZC_DITH_NAC_NFORCE, BLENDER1_16_NIMR_NZC_DITH_AC_NFORCE,
BLENDER1_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_AC_NFORCE, BLENDER1_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_NIMR_ZC_DITH_AC_NFORCE,
BLENDER1_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_DITH_AC_NFORCE, BLENDER1_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_NZC_DITH_AC_NFORCE,
BLENDER1_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_DITH_AC_NFORCE, BLENDER1_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER1_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER1_16_IMR_ZC_DITH_AC_NFORCE,
BLENDER1_16_NIMR_NZC_NDITH_NAC_FORCE, BLENDER1_16_NIMR_NZC_NDITH_AC_FORCE, BLENDER1_16_NIMR_NZC_DITH_NAC_FORCE, BLENDER1_16_NIMR_NZC_DITH_AC_FORCE, BLENDER1_16_NIMR_NZC_NDITH_NAC_FORCE, BLENDER1_16_NIMR_NZC_NDITH_AC_FORCE, BLENDER1_16_NIMR_NZC_DITH_NAC_FORCE, BLENDER1_16_NIMR_NZC_DITH_AC_FORCE,
BLENDER1_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_DITH_AC_FORCE, BLENDER1_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER1_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER1_16_NIMR_ZC_DITH_AC_FORCE,
BLENDER1_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_NZC_NDITH_AC_FORCE, BLENDER1_16_IMR_NZC_DITH_NAC_FORCE, BLENDER1_16_IMR_NZC_DITH_AC_FORCE, BLENDER1_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_NZC_NDITH_AC_FORCE, BLENDER1_16_IMR_NZC_DITH_NAC_FORCE, BLENDER1_16_IMR_NZC_DITH_AC_FORCE,
BLENDER1_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_ZC_NDITH_AC_FORCE, BLENDER1_16_IMR_ZC_DITH_NAC_FORCE, BLENDER1_16_IMR_ZC_DITH_AC_FORCE, BLENDER1_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER1_16_IMR_ZC_NDITH_AC_FORCE, BLENDER1_16_IMR_ZC_DITH_NAC_FORCE, BLENDER1_16_IMR_ZC_DITH_AC_FORCE,
}; };
static int (*rdp_blender2_16_dith_func[32])(UINT16 *, UINT8 *, COLOR, COLOR, int) = static int (*rdp_blender2_16_dith_func[32])(UINT16 *, UINT8 *, COLOR, COLOR, int) =
{ {
BLENDER2_16_NIMR_NZC_NDITH_NAC_NFORCE, BLENDER2_16_NIMR_NZC_NDITH_AC_NFORCE, BLENDER2_16_NIMR_NZC_DITH_NAC_NFORCE, BLENDER2_16_NIMR_NZC_DITH_AC_NFORCE, BLENDER2_16_NIMR_NZC_NDITH_NAC_NFORCE, BLENDER2_16_NIMR_NZC_NDITH_AC_NFORCE, BLENDER2_16_NIMR_NZC_DITH_NAC_NFORCE, BLENDER2_16_NIMR_NZC_DITH_AC_NFORCE,
BLENDER2_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_AC_NFORCE, BLENDER2_16_NIMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_NIMR_ZC_DITH_AC_NFORCE,
BLENDER2_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_DITH_AC_NFORCE, BLENDER2_16_IMR_NZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_NZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_NZC_DITH_AC_NFORCE,
BLENDER2_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_DITH_AC_NFORCE, BLENDER2_16_IMR_ZC_NDITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_NDITH_AC_NFORCE, BLENDER2_16_IMR_ZC_DITH_NAC_NFORCE, BLENDER2_16_IMR_ZC_DITH_AC_NFORCE,
BLENDER2_16_NIMR_NZC_NDITH_NAC_FORCE, BLENDER2_16_NIMR_NZC_NDITH_AC_FORCE, BLENDER2_16_NIMR_NZC_DITH_NAC_FORCE, BLENDER2_16_NIMR_NZC_DITH_AC_FORCE, BLENDER2_16_NIMR_NZC_NDITH_NAC_FORCE, BLENDER2_16_NIMR_NZC_NDITH_AC_FORCE, BLENDER2_16_NIMR_NZC_DITH_NAC_FORCE, BLENDER2_16_NIMR_NZC_DITH_AC_FORCE,
BLENDER2_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_DITH_AC_FORCE, BLENDER2_16_NIMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_NDITH_AC_FORCE, BLENDER2_16_NIMR_ZC_DITH_NAC_FORCE, BLENDER2_16_NIMR_ZC_DITH_AC_FORCE,
BLENDER2_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_NZC_NDITH_AC_FORCE, BLENDER2_16_IMR_NZC_DITH_NAC_FORCE, BLENDER2_16_IMR_NZC_DITH_AC_FORCE, BLENDER2_16_IMR_NZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_NZC_NDITH_AC_FORCE, BLENDER2_16_IMR_NZC_DITH_NAC_FORCE, BLENDER2_16_IMR_NZC_DITH_AC_FORCE,
BLENDER2_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_ZC_NDITH_AC_FORCE, BLENDER2_16_IMR_ZC_DITH_NAC_FORCE, BLENDER2_16_IMR_ZC_DITH_AC_FORCE, BLENDER2_16_IMR_ZC_NDITH_NAC_FORCE, BLENDER2_16_IMR_ZC_NDITH_AC_FORCE, BLENDER2_16_IMR_ZC_DITH_NAC_FORCE, BLENDER2_16_IMR_ZC_DITH_AC_FORCE,
}; };
static int (*rdp_blender1_16_ndith_func[16])(UINT16 *, UINT8 *, COLOR) = static int (*rdp_blender1_16_ndith_func[16])(UINT16 *, UINT8 *, COLOR) =
{ {
BLENDER1_16_NIMR_NZC_NAC_ND_NFORCE, BLENDER1_16_NIMR_NZC_AC_ND_NFORCE, BLENDER1_16_NIMR_NZC_NAC_ND_NFORCE, BLENDER1_16_NIMR_NZC_AC_ND_NFORCE,
BLENDER1_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER1_16_NIMR_ZC_AC_ND_NFORCE, BLENDER1_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER1_16_NIMR_ZC_AC_ND_NFORCE,
BLENDER1_16_IMR_NZC_NAC_ND_NFORCE, BLENDER1_16_IMR_NZC_AC_ND_NFORCE, BLENDER1_16_IMR_NZC_NAC_ND_NFORCE, BLENDER1_16_IMR_NZC_AC_ND_NFORCE,
BLENDER1_16_IMR_ZC_NAC_ND_NFORCE, BLENDER1_16_IMR_ZC_AC_ND_NFORCE, BLENDER1_16_IMR_ZC_NAC_ND_NFORCE, BLENDER1_16_IMR_ZC_AC_ND_NFORCE,
BLENDER1_16_NIMR_NZC_NAC_ND_FORCE, BLENDER1_16_NIMR_NZC_AC_ND_FORCE, BLENDER1_16_NIMR_NZC_NAC_ND_FORCE, BLENDER1_16_NIMR_NZC_AC_ND_FORCE,
BLENDER1_16_NIMR_ZC_NAC_ND_FORCE, BLENDER1_16_NIMR_ZC_AC_ND_FORCE, BLENDER1_16_NIMR_ZC_NAC_ND_FORCE, BLENDER1_16_NIMR_ZC_AC_ND_FORCE,
BLENDER1_16_IMR_NZC_NAC_ND_FORCE, BLENDER1_16_IMR_NZC_AC_ND_FORCE, BLENDER1_16_IMR_NZC_NAC_ND_FORCE, BLENDER1_16_IMR_NZC_AC_ND_FORCE,
BLENDER1_16_IMR_ZC_NAC_ND_FORCE, BLENDER1_16_IMR_ZC_AC_ND_FORCE, BLENDER1_16_IMR_ZC_NAC_ND_FORCE, BLENDER1_16_IMR_ZC_AC_ND_FORCE,
}; };
static int (*rdp_blender2_16_ndith_func[16])(UINT16 *, UINT8 *, COLOR, COLOR) = static int (*rdp_blender2_16_ndith_func[16])(UINT16 *, UINT8 *, COLOR, COLOR) =
{ {
BLENDER2_16_NIMR_NZC_NAC_ND_NFORCE, BLENDER2_16_NIMR_NZC_AC_ND_NFORCE, BLENDER2_16_NIMR_NZC_NAC_ND_NFORCE, BLENDER2_16_NIMR_NZC_AC_ND_NFORCE,
BLENDER2_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER2_16_NIMR_ZC_AC_ND_NFORCE, BLENDER2_16_NIMR_ZC_NAC_ND_NFORCE, BLENDER2_16_NIMR_ZC_AC_ND_NFORCE,
BLENDER2_16_IMR_NZC_NAC_ND_NFORCE, BLENDER2_16_IMR_NZC_AC_ND_NFORCE, BLENDER2_16_IMR_NZC_NAC_ND_NFORCE, BLENDER2_16_IMR_NZC_AC_ND_NFORCE,
BLENDER2_16_IMR_ZC_NAC_ND_NFORCE, BLENDER2_16_IMR_ZC_AC_ND_NFORCE, BLENDER2_16_IMR_ZC_NAC_ND_NFORCE, BLENDER2_16_IMR_ZC_AC_ND_NFORCE,
BLENDER2_16_NIMR_NZC_NAC_ND_FORCE, BLENDER2_16_NIMR_NZC_AC_ND_FORCE, BLENDER2_16_NIMR_NZC_NAC_ND_FORCE, BLENDER2_16_NIMR_NZC_AC_ND_FORCE,
BLENDER2_16_NIMR_ZC_NAC_ND_FORCE, BLENDER2_16_NIMR_ZC_AC_ND_FORCE, BLENDER2_16_NIMR_ZC_NAC_ND_FORCE, BLENDER2_16_NIMR_ZC_AC_ND_FORCE,
BLENDER2_16_IMR_NZC_NAC_ND_FORCE, BLENDER2_16_IMR_NZC_AC_ND_FORCE, BLENDER2_16_IMR_NZC_NAC_ND_FORCE, BLENDER2_16_IMR_NZC_AC_ND_FORCE,
BLENDER2_16_IMR_ZC_NAC_ND_FORCE, BLENDER2_16_IMR_ZC_AC_ND_FORCE, BLENDER2_16_IMR_ZC_NAC_ND_FORCE, BLENDER2_16_IMR_ZC_AC_ND_FORCE,
}; };

60
src/mame/video/rdpcc.c
View File

@ -1,14 +1,14 @@
/* /*
#if defined(NOISE) #if defined(NOISE)
#define COLOR_COMBINER1_NOISE(color) #define COLOR_COMBINER1_NOISE(color)
noise_color.i.r = rdp_rand(); noise_color.i.r = rdp_rand();
noise_color.i.g = rdp_rand(); noise_color.i.g = rdp_rand();
noise_color.i.b = rdp_rand(); noise_color.i.b = rdp_rand();
color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]);
color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]); color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]);
color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]); color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]);
color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]); color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]);
alpha_cvg_get(&color.i.a); alpha_cvg_get(&color.i.a);
#else*/ #else*/
#define COLOR_COMBINER1(color) \ #define COLOR_COMBINER1(color) \
color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); \ color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); \
@ -20,15 +20,15 @@
/* /*
#if defined(NOISE) #if defined(NOISE)
#define COLOR_COMBINER2_C0_NOISE(color) #define COLOR_COMBINER2_C0_NOISE(color)
noise_color.i.r = rdp_rand(); noise_color.i.r = rdp_rand();
noise_color.i.g = rdp_rand(); noise_color.i.g = rdp_rand();
noise_color.i.b = rdp_rand(); noise_color.i.b = rdp_rand();
color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[0],*combiner_rgbsub_b_r[0],*combiner_rgbmul_r[0],*combiner_rgbadd_r[0]); color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[0],*combiner_rgbsub_b_r[0],*combiner_rgbmul_r[0],*combiner_rgbadd_r[0]);
color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[0],*combiner_rgbsub_b_g[0],*combiner_rgbmul_g[0],*combiner_rgbadd_g[0]); color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[0],*combiner_rgbsub_b_g[0],*combiner_rgbmul_g[0],*combiner_rgbadd_g[0]);
color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[0],*combiner_rgbsub_b_b[0],*combiner_rgbmul_b[0],*combiner_rgbadd_b[0]); color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[0],*combiner_rgbsub_b_b[0],*combiner_rgbmul_b[0],*combiner_rgbadd_b[0]);
color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[0],*combiner_alphasub_b[0],*combiner_alphamul[0],*combiner_alphaadd[0]); color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[0],*combiner_alphasub_b[0],*combiner_alphamul[0],*combiner_alphaadd[0]);
combined_color.c = color.c; combined_color.c = color.c;
#else*/ #else*/
#define COLOR_COMBINER2_C0(color) \ #define COLOR_COMBINER2_C0(color) \
color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[0],*combiner_rgbsub_b_r[0],*combiner_rgbmul_r[0],*combiner_rgbadd_r[0]); \ color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[0],*combiner_rgbsub_b_r[0],*combiner_rgbmul_r[0],*combiner_rgbadd_r[0]); \
@ -40,18 +40,18 @@
/*#if defined(NOISE) /*#if defined(NOISE)
#define COLOR_COMBINER2_C1_NOISE(color) #define COLOR_COMBINER2_C1_NOISE(color)
color.c = texel0_color.c; color.c = texel0_color.c;
texel0_color.c = texel1_color.c; texel0_color.c = texel1_color.c;
texel1_color.c = color.c; texel1_color.c = color.c;
noise_color.i.r = rdp_rand(); noise_color.i.r = rdp_rand();
noise_color.i.g = rdp_rand(); noise_color.i.g = rdp_rand();
noise_color.i.b = rdp_rand(); noise_color.i.b = rdp_rand();
color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]); color.i.r = COMBINER_EQUATION(*combiner_rgbsub_a_r[1],*combiner_rgbsub_b_r[1],*combiner_rgbmul_r[1],*combiner_rgbadd_r[1]);
color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]); color.i.g = COMBINER_EQUATION(*combiner_rgbsub_a_g[1],*combiner_rgbsub_b_g[1],*combiner_rgbmul_g[1],*combiner_rgbadd_g[1]);
color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]); color.i.b = COMBINER_EQUATION(*combiner_rgbsub_a_b[1],*combiner_rgbsub_b_b[1],*combiner_rgbmul_b[1],*combiner_rgbadd_b[1]);
color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]); color.i.a = COMBINER_EQUATION(*combiner_alphasub_a[1],*combiner_alphasub_b[1],*combiner_alphamul[1],*combiner_alphaadd[1]);
alpha_cvg_get(&color.i.a); alpha_cvg_get(&color.i.a);
#else*/ #else*/
#define COLOR_COMBINER2_C1(color) \ #define COLOR_COMBINER2_C1(color) \
color.c = texel0_color.c; \ color.c = texel0_color.c; \

6
src/mame/video/rdpclamp.h
View File

@ -19,18 +19,18 @@ INLINE void CLAMP_QUICK_C(INT32* S, INT32* T, INT32 maxs, INT32 maxt, int num);
static void (*rdp_clamp_func[8])(INT32*, INT32*, INT32*, INT32*, INT32, INT32, TILE*) = static void (*rdp_clamp_func[8])(INT32*, INT32*, INT32*, INT32*, INT32, INT32, TILE*) =
{ {
CLAMP_NC_NDOS_NDOT, CLAMP_NC_NDOS_DOT, CLAMP_NC_DOS_NDOT, CLAMP_NC_DOS_DOT, CLAMP_NC_NDOS_NDOT, CLAMP_NC_NDOS_DOT, CLAMP_NC_DOS_NDOT, CLAMP_NC_DOS_DOT,
CLAMP_C, CLAMP_C, CLAMP_C, CLAMP_C, CLAMP_C, CLAMP_C, CLAMP_C, CLAMP_C,
}; };
static void (*rdp_clamp_light_func[8])(INT32*, INT32*, INT32, INT32, TILE*) = static void (*rdp_clamp_light_func[8])(INT32*, INT32*, INT32, INT32, TILE*) =
{ {
CLAMP_LIGHT_NC_NDOS_NDOT, CLAMP_LIGHT_NC_NDOS_DOT, CLAMP_LIGHT_NC_DOS_NDOT, CLAMP_LIGHT_NC_DOS_DOT, CLAMP_LIGHT_NC_NDOS_NDOT, CLAMP_LIGHT_NC_NDOS_DOT, CLAMP_LIGHT_NC_DOS_NDOT, CLAMP_LIGHT_NC_DOS_DOT,
CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C, CLAMP_LIGHT_C,
}; };
static void (*rdp_clamp_quick_func[8])(INT32*, INT32*, INT32, INT32, int) = static void (*rdp_clamp_quick_func[8])(INT32*, INT32*, INT32, INT32, int) =
{ {
CLAMP_QUICK_NC_NDOS_NDOT, CLAMP_QUICK_NC_NDOS_DOT, CLAMP_QUICK_NC_DOS_NDOT, CLAMP_QUICK_NC_DOS_DOT, CLAMP_QUICK_NC_NDOS_NDOT, CLAMP_QUICK_NC_NDOS_DOT, CLAMP_QUICK_NC_DOS_NDOT, CLAMP_QUICK_NC_DOS_DOT,
CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C, CLAMP_QUICK_C,
}; };

40
src/mame/video/rdpfetch.h
View File

@ -41,41 +41,41 @@ static UINT32 (*rdp_fetch_texel_func[128])(UINT32, UINT32) =
{ {
// 4-bit accessors // 4-bit accessors
FETCH_TEXEL_RGBA4_TLUT_NEN, FETCH_TEXEL_RGBA4_TLUT_NEN, FETCH_TEXEL_RGBA4_TLUT_EN0, FETCH_TEXEL_RGBA4_TLUT_EN1, FETCH_TEXEL_RGBA4_TLUT_NEN, FETCH_TEXEL_RGBA4_TLUT_NEN, FETCH_TEXEL_RGBA4_TLUT_EN0, FETCH_TEXEL_RGBA4_TLUT_EN1,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_EN0, FETCH_TEXEL_CI4_TLUT_EN1, FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_NEN, FETCH_TEXEL_CI4_TLUT_EN0, FETCH_TEXEL_CI4_TLUT_EN1,
FETCH_TEXEL_IA4_TLUT_NEN, FETCH_TEXEL_IA4_TLUT_NEN, FETCH_TEXEL_IA4_TLUT_EN0, FETCH_TEXEL_IA4_TLUT_EN1, FETCH_TEXEL_IA4_TLUT_NEN, FETCH_TEXEL_IA4_TLUT_NEN, FETCH_TEXEL_IA4_TLUT_EN0, FETCH_TEXEL_IA4_TLUT_EN1,
FETCH_TEXEL_I4_TLUT_NEN, FETCH_TEXEL_I4_TLUT_NEN, FETCH_TEXEL_I4_TLUT_EN0, FETCH_TEXEL_I4_TLUT_EN1, FETCH_TEXEL_I4_TLUT_NEN, FETCH_TEXEL_I4_TLUT_NEN, FETCH_TEXEL_I4_TLUT_EN0, FETCH_TEXEL_I4_TLUT_EN1,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
// 8-bit accessors // 8-bit accessors
FETCH_TEXEL_RGBA8_TLUT_NEN, FETCH_TEXEL_RGBA8_TLUT_NEN, FETCH_TEXEL_RGBA8_TLUT_EN0, FETCH_TEXEL_RGBA8_TLUT_EN1, FETCH_TEXEL_RGBA8_TLUT_NEN, FETCH_TEXEL_RGBA8_TLUT_NEN, FETCH_TEXEL_RGBA8_TLUT_EN0, FETCH_TEXEL_RGBA8_TLUT_EN1,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_EN0, FETCH_TEXEL_CI8_TLUT_EN1, FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_NEN, FETCH_TEXEL_CI8_TLUT_EN0, FETCH_TEXEL_CI8_TLUT_EN1,
FETCH_TEXEL_IA8_TLUT_NEN, FETCH_TEXEL_IA8_TLUT_NEN, FETCH_TEXEL_IA8_TLUT_EN0, FETCH_TEXEL_IA8_TLUT_EN1, FETCH_TEXEL_IA8_TLUT_NEN, FETCH_TEXEL_IA8_TLUT_NEN, FETCH_TEXEL_IA8_TLUT_EN0, FETCH_TEXEL_IA8_TLUT_EN1,
FETCH_TEXEL_I8_TLUT_NEN, FETCH_TEXEL_I8_TLUT_NEN, FETCH_TEXEL_I8_TLUT_EN0, FETCH_TEXEL_I8_TLUT_EN1, FETCH_TEXEL_I8_TLUT_NEN, FETCH_TEXEL_I8_TLUT_NEN, FETCH_TEXEL_I8_TLUT_EN0, FETCH_TEXEL_I8_TLUT_EN1,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
// 16-bit accessors // 16-bit accessors
FETCH_TEXEL_RGBA16_TLUT_NEN,FETCH_TEXEL_RGBA16_TLUT_NEN,FETCH_TEXEL_RGBA16_TLUT_EN0,FETCH_TEXEL_RGBA16_TLUT_EN1, FETCH_TEXEL_RGBA16_TLUT_NEN,FETCH_TEXEL_RGBA16_TLUT_NEN,FETCH_TEXEL_RGBA16_TLUT_EN0,FETCH_TEXEL_RGBA16_TLUT_EN1,
FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16, FETCH_TEXEL_YUV16,
FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_EN0, FETCH_TEXEL_CI16_TLUT_EN1, FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_NEN, FETCH_TEXEL_CI16_TLUT_EN0, FETCH_TEXEL_CI16_TLUT_EN1,
FETCH_TEXEL_IA16_TLUT_NEN, FETCH_TEXEL_IA16_TLUT_NEN, FETCH_TEXEL_IA16_TLUT_EN0, FETCH_TEXEL_IA16_TLUT_EN1, FETCH_TEXEL_IA16_TLUT_NEN, FETCH_TEXEL_IA16_TLUT_NEN, FETCH_TEXEL_IA16_TLUT_EN0, FETCH_TEXEL_IA16_TLUT_EN1,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
// 32-bit accessors // 32-bit accessors
FETCH_TEXEL_RGBA32_TLUT_NEN,FETCH_TEXEL_RGBA32_TLUT_NEN,FETCH_TEXEL_RGBA32_TLUT_EN0,FETCH_TEXEL_RGBA32_TLUT_EN1, FETCH_TEXEL_RGBA32_TLUT_NEN,FETCH_TEXEL_RGBA32_TLUT_NEN,FETCH_TEXEL_RGBA32_TLUT_EN0,FETCH_TEXEL_RGBA32_TLUT_EN1,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID, FETCH_TEXEL_INVALID,
}; };

4
src/mame/video/rdpfrect.h
View File

@ -11,6 +11,6 @@ static void (*rdp_fill_rectangle_16bit_func[16])(RECTANGLE *) =
{ {
fill_rectangle_16bit_c1_dm, fill_rectangle_16bit_c1_db, fill_rectangle_16bit_c1_dn, fill_rectangle_16bit_c1_dn, fill_rectangle_16bit_c1_dm, fill_rectangle_16bit_c1_db, fill_rectangle_16bit_c1_dn, fill_rectangle_16bit_c1_dn,
fill_rectangle_16bit_c2_dm, fill_rectangle_16bit_c2_db, fill_rectangle_16bit_c2_dn, fill_rectangle_16bit_c2_dn, fill_rectangle_16bit_c2_dm, fill_rectangle_16bit_c2_db, fill_rectangle_16bit_c2_dn, fill_rectangle_16bit_c2_dn,
fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc, fill_rectangle_16bit_cc,
fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf, fill_rectangle_16bit_cf,
}; };

330
src/mame/video/rdpspn16.h
View File

@ -396,275 +396,275 @@ static void render_spans_16_c2_s_t_z_f_zc_zu_dn(int start, int end, TILE* tex_ti
static void (*rdp_render_spans_16_func[512])(int, int, TILE*) = static void (*rdp_render_spans_16_func[512])(int, int, TILE*) =
{ {
render_spans_16_c1_ns_nt_nz_nf_nzc_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_dm, render_spans_16_c1_ns_nt_nz_nf_nzc_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_dm,
render_spans_16_c1_ns_nt_z_nf_nzc_dm, render_spans_16_c2_ns_nt_z_nf_nzc_dm, render_spans_16_c1_ns_nt_z_nf_nzc_dm, render_spans_16_c2_ns_nt_z_nf_nzc_dm,
render_spans_16_c1_ns_t_nz_nf_nzc_dm, render_spans_16_c2_ns_t_nz_nf_nzc_dm, render_spans_16_c1_ns_t_nz_nf_nzc_dm, render_spans_16_c2_ns_t_nz_nf_nzc_dm,
render_spans_16_c1_ns_t_z_nf_nzc_dm, render_spans_16_c2_ns_t_z_nf_nzc_dm, render_spans_16_c1_ns_t_z_nf_nzc_dm, render_spans_16_c2_ns_t_z_nf_nzc_dm,
render_spans_16_c1_s_nt_nz_nf_nzc_dm, render_spans_16_c2_s_nt_nz_nf_nzc_dm, render_spans_16_c1_s_nt_nz_nf_nzc_dm, render_spans_16_c2_s_nt_nz_nf_nzc_dm,
render_spans_16_c1_s_nt_z_nf_nzc_dm, render_spans_16_c2_s_nt_z_nf_nzc_dm, render_spans_16_c1_s_nt_z_nf_nzc_dm, render_spans_16_c2_s_nt_z_nf_nzc_dm,
render_spans_16_c1_s_t_nz_nf_nzc_dm, render_spans_16_c2_s_t_nz_nf_nzc_dm, render_spans_16_c1_s_t_nz_nf_nzc_dm, render_spans_16_c2_s_t_nz_nf_nzc_dm,
render_spans_16_c1_s_t_z_nf_nzc_dm, render_spans_16_c2_s_t_z_nf_nzc_dm, render_spans_16_c1_s_t_z_nf_nzc_dm, render_spans_16_c2_s_t_z_nf_nzc_dm,
render_spans_16_c1_ns_nt_nz_f_nzc_dm, render_spans_16_c2_ns_nt_nz_f_nzc_dm, render_spans_16_c1_ns_nt_nz_f_nzc_dm, render_spans_16_c2_ns_nt_nz_f_nzc_dm,
render_spans_16_c1_ns_nt_z_f_nzc_dm, render_spans_16_c2_ns_nt_z_f_nzc_dm, render_spans_16_c1_ns_nt_z_f_nzc_dm, render_spans_16_c2_ns_nt_z_f_nzc_dm,
render_spans_16_c1_ns_t_nz_f_nzc_dm, render_spans_16_c2_ns_t_nz_f_nzc_dm, render_spans_16_c1_ns_t_nz_f_nzc_dm, render_spans_16_c2_ns_t_nz_f_nzc_dm,
render_spans_16_c1_ns_t_z_f_nzc_dm, render_spans_16_c2_ns_t_z_f_nzc_dm, render_spans_16_c1_ns_t_z_f_nzc_dm, render_spans_16_c2_ns_t_z_f_nzc_dm,
render_spans_16_c1_s_nt_nz_f_nzc_dm, render_spans_16_c2_s_nt_nz_f_nzc_dm, render_spans_16_c1_s_nt_nz_f_nzc_dm, render_spans_16_c2_s_nt_nz_f_nzc_dm,
render_spans_16_c1_s_nt_z_f_nzc_dm, render_spans_16_c2_s_nt_z_f_nzc_dm, render_spans_16_c1_s_nt_z_f_nzc_dm, render_spans_16_c2_s_nt_z_f_nzc_dm,
render_spans_16_c1_s_t_nz_f_nzc_dm, render_spans_16_c2_s_t_nz_f_nzc_dm, render_spans_16_c1_s_t_nz_f_nzc_dm, render_spans_16_c2_s_t_nz_f_nzc_dm,
render_spans_16_c1_s_t_z_f_nzc_dm, render_spans_16_c2_s_t_z_f_nzc_dm, render_spans_16_c1_s_t_z_f_nzc_dm, render_spans_16_c2_s_t_z_f_nzc_dm,
render_spans_16_c1_ns_nt_nz_nf_zc_dm, render_spans_16_c2_ns_nt_nz_nf_zc_dm, render_spans_16_c1_ns_nt_nz_nf_zc_dm, render_spans_16_c2_ns_nt_nz_nf_zc_dm,
render_spans_16_c1_ns_nt_z_nf_zc_dm, render_spans_16_c2_ns_nt_z_nf_zc_dm, render_spans_16_c1_ns_nt_z_nf_zc_dm, render_spans_16_c2_ns_nt_z_nf_zc_dm,
render_spans_16_c1_ns_t_nz_nf_zc_dm, render_spans_16_c2_ns_t_nz_nf_zc_dm, render_spans_16_c1_ns_t_nz_nf_zc_dm, render_spans_16_c2_ns_t_nz_nf_zc_dm,
render_spans_16_c1_ns_t_z_nf_zc_dm, render_spans_16_c2_ns_t_z_nf_zc_dm, render_spans_16_c1_ns_t_z_nf_zc_dm, render_spans_16_c2_ns_t_z_nf_zc_dm,
render_spans_16_c1_s_nt_nz_nf_zc_dm, render_spans_16_c2_s_nt_nz_nf_zc_dm, render_spans_16_c1_s_nt_nz_nf_zc_dm, render_spans_16_c2_s_nt_nz_nf_zc_dm,
render_spans_16_c1_s_nt_z_nf_zc_dm, render_spans_16_c2_s_nt_z_nf_zc_dm, render_spans_16_c1_s_nt_z_nf_zc_dm, render_spans_16_c2_s_nt_z_nf_zc_dm,
render_spans_16_c1_s_t_nz_nf_zc_dm, render_spans_16_c2_s_t_nz_nf_zc_dm, render_spans_16_c1_s_t_nz_nf_zc_dm, render_spans_16_c2_s_t_nz_nf_zc_dm,
render_spans_16_c1_s_t_z_nf_zc_dm, render_spans_16_c2_s_t_z_nf_zc_dm, render_spans_16_c1_s_t_z_nf_zc_dm, render_spans_16_c2_s_t_z_nf_zc_dm,
render_spans_16_c1_ns_nt_nz_f_zc_dm, render_spans_16_c2_ns_nt_nz_f_zc_dm, render_spans_16_c1_ns_nt_nz_f_zc_dm, render_spans_16_c2_ns_nt_nz_f_zc_dm,
render_spans_16_c1_ns_nt_z_f_zc_dm, render_spans_16_c2_ns_nt_z_f_zc_dm, render_spans_16_c1_ns_nt_z_f_zc_dm, render_spans_16_c2_ns_nt_z_f_zc_dm,
render_spans_16_c1_ns_t_nz_f_zc_dm, render_spans_16_c2_ns_t_nz_f_zc_dm, render_spans_16_c1_ns_t_nz_f_zc_dm, render_spans_16_c2_ns_t_nz_f_zc_dm,
render_spans_16_c1_ns_t_z_f_zc_dm, render_spans_16_c2_ns_t_z_f_zc_dm, render_spans_16_c1_ns_t_z_f_zc_dm, render_spans_16_c2_ns_t_z_f_zc_dm,
render_spans_16_c1_s_nt_nz_f_zc_dm, render_spans_16_c2_s_nt_nz_f_zc_dm, render_spans_16_c1_s_nt_nz_f_zc_dm, render_spans_16_c2_s_nt_nz_f_zc_dm,
render_spans_16_c1_s_nt_z_f_zc_dm, render_spans_16_c2_s_nt_z_f_zc_dm, render_spans_16_c1_s_nt_z_f_zc_dm, render_spans_16_c2_s_nt_z_f_zc_dm,
render_spans_16_c1_s_t_nz_f_zc_dm, render_spans_16_c2_s_t_nz_f_zc_dm, render_spans_16_c1_s_t_nz_f_zc_dm, render_spans_16_c2_s_t_nz_f_zc_dm,
render_spans_16_c1_s_t_z_f_zc_dm, render_spans_16_c2_s_t_z_f_zc_dm, render_spans_16_c1_s_t_z_f_zc_dm, render_spans_16_c2_s_t_z_f_zc_dm,
render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dm, render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dm,
render_spans_16_c1_ns_nt_z_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dm, render_spans_16_c1_ns_nt_z_nf_nzc_zu_dm, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dm,
render_spans_16_c1_ns_t_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dm, render_spans_16_c1_ns_t_nz_nf_nzc_zu_dm, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dm,
render_spans_16_c1_ns_t_z_nf_nzc_zu_dm, render_spans_16_c2_ns_t_z_nf_nzc_zu_dm, render_spans_16_c1_ns_t_z_nf_nzc_zu_dm, render_spans_16_c2_ns_t_z_nf_nzc_zu_dm,
render_spans_16_c1_s_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dm, render_spans_16_c1_s_nt_nz_nf_nzc_zu_dm, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dm,
render_spans_16_c1_s_nt_z_nf_nzc_zu_dm, render_spans_16_c2_s_nt_z_nf_nzc_zu_dm, render_spans_16_c1_s_nt_z_nf_nzc_zu_dm, render_spans_16_c2_s_nt_z_nf_nzc_zu_dm,
render_spans_16_c1_s_t_nz_nf_nzc_zu_dm, render_spans_16_c2_s_t_nz_nf_nzc_zu_dm, render_spans_16_c1_s_t_nz_nf_nzc_zu_dm, render_spans_16_c2_s_t_nz_nf_nzc_zu_dm,
render_spans_16_c1_s_t_z_nf_nzc_zu_dm, render_spans_16_c2_s_t_z_nf_nzc_zu_dm, render_spans_16_c1_s_t_z_nf_nzc_zu_dm, render_spans_16_c2_s_t_z_nf_nzc_zu_dm,
render_spans_16_c1_ns_nt_nz_f_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dm, render_spans_16_c1_ns_nt_nz_f_nzc_zu_dm, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dm,
render_spans_16_c1_ns_nt_z_f_nzc_zu_dm, render_spans_16_c2_ns_nt_z_f_nzc_zu_dm, render_spans_16_c1_ns_nt_z_f_nzc_zu_dm, render_spans_16_c2_ns_nt_z_f_nzc_zu_dm,
render_spans_16_c1_ns_t_nz_f_nzc_zu_dm, render_spans_16_c2_ns_t_nz_f_nzc_zu_dm, render_spans_16_c1_ns_t_nz_f_nzc_zu_dm, render_spans_16_c2_ns_t_nz_f_nzc_zu_dm,
render_spans_16_c1_ns_t_z_f_nzc_zu_dm, render_spans_16_c2_ns_t_z_f_nzc_zu_dm, render_spans_16_c1_ns_t_z_f_nzc_zu_dm, render_spans_16_c2_ns_t_z_f_nzc_zu_dm,
render_spans_16_c1_s_nt_nz_f_nzc_zu_dm, render_spans_16_c2_s_nt_nz_f_nzc_zu_dm, render_spans_16_c1_s_nt_nz_f_nzc_zu_dm, render_spans_16_c2_s_nt_nz_f_nzc_zu_dm,
render_spans_16_c1_s_nt_z_f_nzc_zu_dm, render_spans_16_c2_s_nt_z_f_nzc_zu_dm, render_spans_16_c1_s_nt_z_f_nzc_zu_dm, render_spans_16_c2_s_nt_z_f_nzc_zu_dm,
render_spans_16_c1_s_t_nz_f_nzc_zu_dm, render_spans_16_c2_s_t_nz_f_nzc_zu_dm, render_spans_16_c1_s_t_nz_f_nzc_zu_dm, render_spans_16_c2_s_t_nz_f_nzc_zu_dm,
render_spans_16_c1_s_t_z_f_nzc_zu_dm, render_spans_16_c2_s_t_z_f_nzc_zu_dm, render_spans_16_c1_s_t_z_f_nzc_zu_dm, render_spans_16_c2_s_t_z_f_nzc_zu_dm,
render_spans_16_c1_ns_nt_nz_nf_zc_zu_dm, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dm, render_spans_16_c1_ns_nt_nz_nf_zc_zu_dm, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dm,
render_spans_16_c1_ns_nt_z_nf_zc_zu_dm, render_spans_16_c2_ns_nt_z_nf_zc_zu_dm, render_spans_16_c1_ns_nt_z_nf_zc_zu_dm, render_spans_16_c2_ns_nt_z_nf_zc_zu_dm,
render_spans_16_c1_ns_t_nz_nf_zc_zu_dm, render_spans_16_c2_ns_t_nz_nf_zc_zu_dm, render_spans_16_c1_ns_t_nz_nf_zc_zu_dm, render_spans_16_c2_ns_t_nz_nf_zc_zu_dm,
render_spans_16_c1_ns_t_z_nf_zc_zu_dm, render_spans_16_c2_ns_t_z_nf_zc_zu_dm, render_spans_16_c1_ns_t_z_nf_zc_zu_dm, render_spans_16_c2_ns_t_z_nf_zc_zu_dm,
render_spans_16_c1_s_nt_nz_nf_zc_zu_dm, render_spans_16_c2_s_nt_nz_nf_zc_zu_dm, render_spans_16_c1_s_nt_nz_nf_zc_zu_dm, render_spans_16_c2_s_nt_nz_nf_zc_zu_dm,
render_spans_16_c1_s_nt_z_nf_zc_zu_dm, render_spans_16_c2_s_nt_z_nf_zc_zu_dm, render_spans_16_c1_s_nt_z_nf_zc_zu_dm, render_spans_16_c2_s_nt_z_nf_zc_zu_dm,
render_spans_16_c1_s_t_nz_nf_zc_zu_dm, render_spans_16_c2_s_t_nz_nf_zc_zu_dm, render_spans_16_c1_s_t_nz_nf_zc_zu_dm, render_spans_16_c2_s_t_nz_nf_zc_zu_dm,
render_spans_16_c1_s_t_z_nf_zc_zu_dm, render_spans_16_c2_s_t_z_nf_zc_zu_dm, render_spans_16_c1_s_t_z_nf_zc_zu_dm, render_spans_16_c2_s_t_z_nf_zc_zu_dm,
render_spans_16_c1_ns_nt_nz_f_zc_zu_dm, render_spans_16_c2_ns_nt_nz_f_zc_zu_dm, render_spans_16_c1_ns_nt_nz_f_zc_zu_dm, render_spans_16_c2_ns_nt_nz_f_zc_zu_dm,
render_spans_16_c1_ns_nt_z_f_zc_zu_dm, render_spans_16_c2_ns_nt_z_f_zc_zu_dm, render_spans_16_c1_ns_nt_z_f_zc_zu_dm, render_spans_16_c2_ns_nt_z_f_zc_zu_dm,
render_spans_16_c1_ns_t_nz_f_zc_zu_dm, render_spans_16_c2_ns_t_nz_f_zc_zu_dm, render_spans_16_c1_ns_t_nz_f_zc_zu_dm, render_spans_16_c2_ns_t_nz_f_zc_zu_dm,
render_spans_16_c1_ns_t_z_f_zc_zu_dm, render_spans_16_c2_ns_t_z_f_zc_zu_dm, render_spans_16_c1_ns_t_z_f_zc_zu_dm, render_spans_16_c2_ns_t_z_f_zc_zu_dm,
render_spans_16_c1_s_nt_nz_f_zc_zu_dm, render_spans_16_c2_s_nt_nz_f_zc_zu_dm, render_spans_16_c1_s_nt_nz_f_zc_zu_dm, render_spans_16_c2_s_nt_nz_f_zc_zu_dm,
render_spans_16_c1_s_nt_z_f_zc_zu_dm, render_spans_16_c2_s_nt_z_f_zc_zu_dm, render_spans_16_c1_s_nt_z_f_zc_zu_dm, render_spans_16_c2_s_nt_z_f_zc_zu_dm,
render_spans_16_c1_s_t_nz_f_zc_zu_dm, render_spans_16_c2_s_t_nz_f_zc_zu_dm, render_spans_16_c1_s_t_nz_f_zc_zu_dm, render_spans_16_c2_s_t_nz_f_zc_zu_dm,
render_spans_16_c1_s_t_z_f_zc_zu_dm, render_spans_16_c2_s_t_z_f_zc_zu_dm, render_spans_16_c1_s_t_z_f_zc_zu_dm, render_spans_16_c2_s_t_z_f_zc_zu_dm,
render_spans_16_c1_ns_nt_nz_nf_nzc_db, render_spans_16_c2_ns_nt_nz_nf_nzc_db, render_spans_16_c1_ns_nt_nz_nf_nzc_db, render_spans_16_c2_ns_nt_nz_nf_nzc_db,
render_spans_16_c1_ns_nt_z_nf_nzc_db, render_spans_16_c2_ns_nt_z_nf_nzc_db, render_spans_16_c1_ns_nt_z_nf_nzc_db, render_spans_16_c2_ns_nt_z_nf_nzc_db,
render_spans_16_c1_ns_t_nz_nf_nzc_db, render_spans_16_c2_ns_t_nz_nf_nzc_db, render_spans_16_c1_ns_t_nz_nf_nzc_db, render_spans_16_c2_ns_t_nz_nf_nzc_db,
render_spans_16_c1_ns_t_z_nf_nzc_db, render_spans_16_c2_ns_t_z_nf_nzc_db, render_spans_16_c1_ns_t_z_nf_nzc_db, render_spans_16_c2_ns_t_z_nf_nzc_db,
render_spans_16_c1_s_nt_nz_nf_nzc_db, render_spans_16_c2_s_nt_nz_nf_nzc_db, render_spans_16_c1_s_nt_nz_nf_nzc_db, render_spans_16_c2_s_nt_nz_nf_nzc_db,
render_spans_16_c1_s_nt_z_nf_nzc_db, render_spans_16_c2_s_nt_z_nf_nzc_db, render_spans_16_c1_s_nt_z_nf_nzc_db, render_spans_16_c2_s_nt_z_nf_nzc_db,
render_spans_16_c1_s_t_nz_nf_nzc_db, render_spans_16_c2_s_t_nz_nf_nzc_db, render_spans_16_c1_s_t_nz_nf_nzc_db, render_spans_16_c2_s_t_nz_nf_nzc_db,
render_spans_16_c1_s_t_z_nf_nzc_db, render_spans_16_c2_s_t_z_nf_nzc_db, render_spans_16_c1_s_t_z_nf_nzc_db, render_spans_16_c2_s_t_z_nf_nzc_db,
render_spans_16_c1_ns_nt_nz_f_nzc_db, render_spans_16_c2_ns_nt_nz_f_nzc_db, render_spans_16_c1_ns_nt_nz_f_nzc_db, render_spans_16_c2_ns_nt_nz_f_nzc_db,
render_spans_16_c1_ns_nt_z_f_nzc_db, render_spans_16_c2_ns_nt_z_f_nzc_db, render_spans_16_c1_ns_nt_z_f_nzc_db, render_spans_16_c2_ns_nt_z_f_nzc_db,
render_spans_16_c1_ns_t_nz_f_nzc_db, render_spans_16_c2_ns_t_nz_f_nzc_db, render_spans_16_c1_ns_t_nz_f_nzc_db, render_spans_16_c2_ns_t_nz_f_nzc_db,
render_spans_16_c1_ns_t_z_f_nzc_db, render_spans_16_c2_ns_t_z_f_nzc_db, render_spans_16_c1_ns_t_z_f_nzc_db, render_spans_16_c2_ns_t_z_f_nzc_db,
render_spans_16_c1_s_nt_nz_f_nzc_db, render_spans_16_c2_s_nt_nz_f_nzc_db, render_spans_16_c1_s_nt_nz_f_nzc_db, render_spans_16_c2_s_nt_nz_f_nzc_db,
render_spans_16_c1_s_nt_z_f_nzc_db, render_spans_16_c2_s_nt_z_f_nzc_db, render_spans_16_c1_s_nt_z_f_nzc_db, render_spans_16_c2_s_nt_z_f_nzc_db,
render_spans_16_c1_s_t_nz_f_nzc_db, render_spans_16_c2_s_t_nz_f_nzc_db, render_spans_16_c1_s_t_nz_f_nzc_db, render_spans_16_c2_s_t_nz_f_nzc_db,
render_spans_16_c1_s_t_z_f_nzc_db, render_spans_16_c2_s_t_z_f_nzc_db, render_spans_16_c1_s_t_z_f_nzc_db, render_spans_16_c2_s_t_z_f_nzc_db,
render_spans_16_c1_ns_nt_nz_nf_zc_db, render_spans_16_c2_ns_nt_nz_nf_zc_db, render_spans_16_c1_ns_nt_nz_nf_zc_db, render_spans_16_c2_ns_nt_nz_nf_zc_db,
render_spans_16_c1_ns_nt_z_nf_zc_db, render_spans_16_c2_ns_nt_z_nf_zc_db, render_spans_16_c1_ns_nt_z_nf_zc_db, render_spans_16_c2_ns_nt_z_nf_zc_db,
render_spans_16_c1_ns_t_nz_nf_zc_db, render_spans_16_c2_ns_t_nz_nf_zc_db, render_spans_16_c1_ns_t_nz_nf_zc_db, render_spans_16_c2_ns_t_nz_nf_zc_db,
render_spans_16_c1_ns_t_z_nf_zc_db, render_spans_16_c2_ns_t_z_nf_zc_db, render_spans_16_c1_ns_t_z_nf_zc_db, render_spans_16_c2_ns_t_z_nf_zc_db,
render_spans_16_c1_s_nt_nz_nf_zc_db, render_spans_16_c2_s_nt_nz_nf_zc_db, render_spans_16_c1_s_nt_nz_nf_zc_db, render_spans_16_c2_s_nt_nz_nf_zc_db,
render_spans_16_c1_s_nt_z_nf_zc_db, render_spans_16_c2_s_nt_z_nf_zc_db, render_spans_16_c1_s_nt_z_nf_zc_db, render_spans_16_c2_s_nt_z_nf_zc_db,
render_spans_16_c1_s_t_nz_nf_zc_db, render_spans_16_c2_s_t_nz_nf_zc_db, render_spans_16_c1_s_t_nz_nf_zc_db, render_spans_16_c2_s_t_nz_nf_zc_db,
render_spans_16_c1_s_t_z_nf_zc_db, render_spans_16_c2_s_t_z_nf_zc_db, render_spans_16_c1_s_t_z_nf_zc_db, render_spans_16_c2_s_t_z_nf_zc_db,
render_spans_16_c1_ns_nt_nz_f_zc_db, render_spans_16_c2_ns_nt_nz_f_zc_db, render_spans_16_c1_ns_nt_nz_f_zc_db, render_spans_16_c2_ns_nt_nz_f_zc_db,
render_spans_16_c1_ns_nt_z_f_zc_db, render_spans_16_c2_ns_nt_z_f_zc_db, render_spans_16_c1_ns_nt_z_f_zc_db, render_spans_16_c2_ns_nt_z_f_zc_db,
render_spans_16_c1_ns_t_nz_f_zc_db, render_spans_16_c2_ns_t_nz_f_zc_db, render_spans_16_c1_ns_t_nz_f_zc_db, render_spans_16_c2_ns_t_nz_f_zc_db,
render_spans_16_c1_ns_t_z_f_zc_db, render_spans_16_c2_ns_t_z_f_zc_db, render_spans_16_c1_ns_t_z_f_zc_db, render_spans_16_c2_ns_t_z_f_zc_db,
render_spans_16_c1_s_nt_nz_f_zc_db, render_spans_16_c2_s_nt_nz_f_zc_db, render_spans_16_c1_s_nt_nz_f_zc_db, render_spans_16_c2_s_nt_nz_f_zc_db,
render_spans_16_c1_s_nt_z_f_zc_db, render_spans_16_c2_s_nt_z_f_zc_db, render_spans_16_c1_s_nt_z_f_zc_db, render_spans_16_c2_s_nt_z_f_zc_db,
render_spans_16_c1_s_t_nz_f_zc_db, render_spans_16_c2_s_t_nz_f_zc_db, render_spans_16_c1_s_t_nz_f_zc_db, render_spans_16_c2_s_t_nz_f_zc_db,
render_spans_16_c1_s_t_z_f_zc_db, render_spans_16_c2_s_t_z_f_zc_db, render_spans_16_c1_s_t_z_f_zc_db, render_spans_16_c2_s_t_z_f_zc_db,
render_spans_16_c1_ns_nt_nz_nf_nzc_zu_db, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_db, render_spans_16_c1_ns_nt_nz_nf_nzc_zu_db, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_db,
render_spans_16_c1_ns_nt_z_nf_nzc_zu_db, render_spans_16_c2_ns_nt_z_nf_nzc_zu_db, render_spans_16_c1_ns_nt_z_nf_nzc_zu_db, render_spans_16_c2_ns_nt_z_nf_nzc_zu_db,
render_spans_16_c1_ns_t_nz_nf_nzc_zu_db, render_spans_16_c2_ns_t_nz_nf_nzc_zu_db, render_spans_16_c1_ns_t_nz_nf_nzc_zu_db, render_spans_16_c2_ns_t_nz_nf_nzc_zu_db,
render_spans_16_c1_ns_t_z_nf_nzc_zu_db, render_spans_16_c2_ns_t_z_nf_nzc_zu_db, render_spans_16_c1_ns_t_z_nf_nzc_zu_db, render_spans_16_c2_ns_t_z_nf_nzc_zu_db,
render_spans_16_c1_s_nt_nz_nf_nzc_zu_db, render_spans_16_c2_s_nt_nz_nf_nzc_zu_db, render_spans_16_c1_s_nt_nz_nf_nzc_zu_db, render_spans_16_c2_s_nt_nz_nf_nzc_zu_db,
render_spans_16_c1_s_nt_z_nf_nzc_zu_db, render_spans_16_c2_s_nt_z_nf_nzc_zu_db, render_spans_16_c1_s_nt_z_nf_nzc_zu_db, render_spans_16_c2_s_nt_z_nf_nzc_zu_db,
render_spans_16_c1_s_t_nz_nf_nzc_zu_db, render_spans_16_c2_s_t_nz_nf_nzc_zu_db, render_spans_16_c1_s_t_nz_nf_nzc_zu_db, render_spans_16_c2_s_t_nz_nf_nzc_zu_db,
render_spans_16_c1_s_t_z_nf_nzc_zu_db, render_spans_16_c2_s_t_z_nf_nzc_zu_db, render_spans_16_c1_s_t_z_nf_nzc_zu_db, render_spans_16_c2_s_t_z_nf_nzc_zu_db,
render_spans_16_c1_ns_nt_nz_f_nzc_zu_db, render_spans_16_c2_ns_nt_nz_f_nzc_zu_db, render_spans_16_c1_ns_nt_nz_f_nzc_zu_db, render_spans_16_c2_ns_nt_nz_f_nzc_zu_db,
render_spans_16_c1_ns_nt_z_f_nzc_zu_db, render_spans_16_c2_ns_nt_z_f_nzc_zu_db, render_spans_16_c1_ns_nt_z_f_nzc_zu_db, render_spans_16_c2_ns_nt_z_f_nzc_zu_db,
render_spans_16_c1_ns_t_nz_f_nzc_zu_db, render_spans_16_c2_ns_t_nz_f_nzc_zu_db, render_spans_16_c1_ns_t_nz_f_nzc_zu_db, render_spans_16_c2_ns_t_nz_f_nzc_zu_db,
render_spans_16_c1_ns_t_z_f_nzc_zu_db, render_spans_16_c2_ns_t_z_f_nzc_zu_db, render_spans_16_c1_ns_t_z_f_nzc_zu_db, render_spans_16_c2_ns_t_z_f_nzc_zu_db,
render_spans_16_c1_s_nt_nz_f_nzc_zu_db, render_spans_16_c2_s_nt_nz_f_nzc_zu_db, render_spans_16_c1_s_nt_nz_f_nzc_zu_db, render_spans_16_c2_s_nt_nz_f_nzc_zu_db,
render_spans_16_c1_s_nt_z_f_nzc_zu_db, render_spans_16_c2_s_nt_z_f_nzc_zu_db, render_spans_16_c1_s_nt_z_f_nzc_zu_db, render_spans_16_c2_s_nt_z_f_nzc_zu_db,
render_spans_16_c1_s_t_nz_f_nzc_zu_db, render_spans_16_c2_s_t_nz_f_nzc_zu_db, render_spans_16_c1_s_t_nz_f_nzc_zu_db, render_spans_16_c2_s_t_nz_f_nzc_zu_db,
render_spans_16_c1_s_t_z_f_nzc_zu_db, render_spans_16_c2_s_t_z_f_nzc_zu_db, render_spans_16_c1_s_t_z_f_nzc_zu_db, render_spans_16_c2_s_t_z_f_nzc_zu_db,
render_spans_16_c1_ns_nt_nz_nf_zc_zu_db, render_spans_16_c2_ns_nt_nz_nf_zc_zu_db, render_spans_16_c1_ns_nt_nz_nf_zc_zu_db, render_spans_16_c2_ns_nt_nz_nf_zc_zu_db,
render_spans_16_c1_ns_nt_z_nf_zc_zu_db, render_spans_16_c2_ns_nt_z_nf_zc_zu_db, render_spans_16_c1_ns_nt_z_nf_zc_zu_db, render_spans_16_c2_ns_nt_z_nf_zc_zu_db,
render_spans_16_c1_ns_t_nz_nf_zc_zu_db, render_spans_16_c2_ns_t_nz_nf_zc_zu_db, render_spans_16_c1_ns_t_nz_nf_zc_zu_db, render_spans_16_c2_ns_t_nz_nf_zc_zu_db,
render_spans_16_c1_ns_t_z_nf_zc_zu_db, render_spans_16_c2_ns_t_z_nf_zc_zu_db, render_spans_16_c1_ns_t_z_nf_zc_zu_db, render_spans_16_c2_ns_t_z_nf_zc_zu_db,
render_spans_16_c1_s_nt_nz_nf_zc_zu_db, render_spans_16_c2_s_nt_nz_nf_zc_zu_db, render_spans_16_c1_s_nt_nz_nf_zc_zu_db, render_spans_16_c2_s_nt_nz_nf_zc_zu_db,
render_spans_16_c1_s_nt_z_nf_zc_zu_db, render_spans_16_c2_s_nt_z_nf_zc_zu_db, render_spans_16_c1_s_nt_z_nf_zc_zu_db, render_spans_16_c2_s_nt_z_nf_zc_zu_db,
render_spans_16_c1_s_t_nz_nf_zc_zu_db, render_spans_16_c2_s_t_nz_nf_zc_zu_db, render_spans_16_c1_s_t_nz_nf_zc_zu_db, render_spans_16_c2_s_t_nz_nf_zc_zu_db,
render_spans_16_c1_s_t_z_nf_zc_zu_db, render_spans_16_c2_s_t_z_nf_zc_zu_db, render_spans_16_c1_s_t_z_nf_zc_zu_db, render_spans_16_c2_s_t_z_nf_zc_zu_db,
render_spans_16_c1_ns_nt_nz_f_zc_zu_db, render_spans_16_c2_ns_nt_nz_f_zc_zu_db, render_spans_16_c1_ns_nt_nz_f_zc_zu_db, render_spans_16_c2_ns_nt_nz_f_zc_zu_db,
render_spans_16_c1_ns_nt_z_f_zc_zu_db, render_spans_16_c2_ns_nt_z_f_zc_zu_db, render_spans_16_c1_ns_nt_z_f_zc_zu_db, render_spans_16_c2_ns_nt_z_f_zc_zu_db,
render_spans_16_c1_ns_t_nz_f_zc_zu_db, render_spans_16_c2_ns_t_nz_f_zc_zu_db, render_spans_16_c1_ns_t_nz_f_zc_zu_db, render_spans_16_c2_ns_t_nz_f_zc_zu_db,
render_spans_16_c1_ns_t_z_f_zc_zu_db, render_spans_16_c2_ns_t_z_f_zc_zu_db, render_spans_16_c1_ns_t_z_f_zc_zu_db, render_spans_16_c2_ns_t_z_f_zc_zu_db,
render_spans_16_c1_s_nt_nz_f_zc_zu_db, render_spans_16_c2_s_nt_nz_f_zc_zu_db, render_spans_16_c1_s_nt_nz_f_zc_zu_db, render_spans_16_c2_s_nt_nz_f_zc_zu_db,
render_spans_16_c1_s_nt_z_f_zc_zu_db, render_spans_16_c2_s_nt_z_f_zc_zu_db, render_spans_16_c1_s_nt_z_f_zc_zu_db, render_spans_16_c2_s_nt_z_f_zc_zu_db,
render_spans_16_c1_s_t_nz_f_zc_zu_db, render_spans_16_c2_s_t_nz_f_zc_zu_db, render_spans_16_c1_s_t_nz_f_zc_zu_db, render_spans_16_c2_s_t_nz_f_zc_zu_db,
render_spans_16_c1_s_t_z_f_zc_zu_db, render_spans_16_c2_s_t_z_f_zc_zu_db, render_spans_16_c1_s_t_z_f_zc_zu_db, render_spans_16_c2_s_t_z_f_zc_zu_db,
render_spans_16_c1_ns_nt_nz_nf_nzc_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_dn, render_spans_16_c1_ns_nt_nz_nf_nzc_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_dn,
render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn, render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn,
render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn, render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn,
render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn, render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn,
render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn, render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn,
render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn, render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn,
render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn, render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn,
render_spans_16_c1_s_t_z_nf_nzc_dn, render_spans_16_c2_s_t_z_nf_nzc_dn, render_spans_16_c1_s_t_z_nf_nzc_dn, render_spans_16_c2_s_t_z_nf_nzc_dn,
render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn, render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn,
render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn, render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn,
render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn, render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn,
render_spans_16_c1_ns_t_z_f_nzc_dn, render_spans_16_c2_ns_t_z_f_nzc_dn, render_spans_16_c1_ns_t_z_f_nzc_dn, render_spans_16_c2_ns_t_z_f_nzc_dn,
render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn, render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn,
render_spans_16_c1_s_nt_z_f_nzc_dn, render_spans_16_c2_s_nt_z_f_nzc_dn, render_spans_16_c1_s_nt_z_f_nzc_dn, render_spans_16_c2_s_nt_z_f_nzc_dn,
render_spans_16_c1_s_t_nz_f_nzc_dn, render_spans_16_c2_s_t_nz_f_nzc_dn, render_spans_16_c1_s_t_nz_f_nzc_dn, render_spans_16_c2_s_t_nz_f_nzc_dn,
render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn, render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn,
render_spans_16_c1_ns_nt_nz_nf_zc_dn, render_spans_16_c2_ns_nt_nz_nf_zc_dn, render_spans_16_c1_ns_nt_nz_nf_zc_dn, render_spans_16_c2_ns_nt_nz_nf_zc_dn,
render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn, render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn,
render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn, render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn,
render_spans_16_c1_ns_t_z_nf_zc_dn, render_spans_16_c2_ns_t_z_nf_zc_dn, render_spans_16_c1_ns_t_z_nf_zc_dn, render_spans_16_c2_ns_t_z_nf_zc_dn,
render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn, render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn,
render_spans_16_c1_s_nt_z_nf_zc_dn, render_spans_16_c2_s_nt_z_nf_zc_dn, render_spans_16_c1_s_nt_z_nf_zc_dn, render_spans_16_c2_s_nt_z_nf_zc_dn,
render_spans_16_c1_s_t_nz_nf_zc_dn, render_spans_16_c2_s_t_nz_nf_zc_dn, render_spans_16_c1_s_t_nz_nf_zc_dn, render_spans_16_c2_s_t_nz_nf_zc_dn,
render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn, render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn,
render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn, render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn,
render_spans_16_c1_ns_nt_z_f_zc_dn, render_spans_16_c2_ns_nt_z_f_zc_dn, render_spans_16_c1_ns_nt_z_f_zc_dn, render_spans_16_c2_ns_nt_z_f_zc_dn,
render_spans_16_c1_ns_t_nz_f_zc_dn, render_spans_16_c2_ns_t_nz_f_zc_dn, render_spans_16_c1_ns_t_nz_f_zc_dn, render_spans_16_c2_ns_t_nz_f_zc_dn,
render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn, render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn,
render_spans_16_c1_s_nt_nz_f_zc_dn, render_spans_16_c2_s_nt_nz_f_zc_dn, render_spans_16_c1_s_nt_nz_f_zc_dn, render_spans_16_c2_s_nt_nz_f_zc_dn,
render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn, render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn,
render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn, render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn,
render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn, render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn,
render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn,
render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn,
render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn,
render_spans_16_c1_ns_t_z_nf_nzc_zu_dn, render_spans_16_c2_ns_t_z_nf_nzc_zu_dn, render_spans_16_c1_ns_t_z_nf_nzc_zu_dn, render_spans_16_c2_ns_t_z_nf_nzc_zu_dn,
render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn,
render_spans_16_c1_s_nt_z_nf_nzc_zu_dn, render_spans_16_c2_s_nt_z_nf_nzc_zu_dn, render_spans_16_c1_s_nt_z_nf_nzc_zu_dn, render_spans_16_c2_s_nt_z_nf_nzc_zu_dn,
render_spans_16_c1_s_t_nz_nf_nzc_zu_dn, render_spans_16_c2_s_t_nz_nf_nzc_zu_dn, render_spans_16_c1_s_t_nz_nf_nzc_zu_dn, render_spans_16_c2_s_t_nz_nf_nzc_zu_dn,
render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn, render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn,
render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn,
render_spans_16_c1_ns_nt_z_f_nzc_zu_dn, render_spans_16_c2_ns_nt_z_f_nzc_zu_dn, render_spans_16_c1_ns_nt_z_f_nzc_zu_dn, render_spans_16_c2_ns_nt_z_f_nzc_zu_dn,
render_spans_16_c1_ns_t_nz_f_nzc_zu_dn, render_spans_16_c2_ns_t_nz_f_nzc_zu_dn, render_spans_16_c1_ns_t_nz_f_nzc_zu_dn, render_spans_16_c2_ns_t_nz_f_nzc_zu_dn,
render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn, render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn,
render_spans_16_c1_s_nt_nz_f_nzc_zu_dn, render_spans_16_c2_s_nt_nz_f_nzc_zu_dn, render_spans_16_c1_s_nt_nz_f_nzc_zu_dn, render_spans_16_c2_s_nt_nz_f_nzc_zu_dn,
render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn, render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn,
render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn, render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn,
render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn, render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn,
render_spans_16_c1_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c1_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dn,
render_spans_16_c1_ns_nt_z_nf_zc_zu_dn, render_spans_16_c2_ns_nt_z_nf_zc_zu_dn, render_spans_16_c1_ns_nt_z_nf_zc_zu_dn, render_spans_16_c2_ns_nt_z_nf_zc_zu_dn,
render_spans_16_c1_ns_t_nz_nf_zc_zu_dn, render_spans_16_c2_ns_t_nz_nf_zc_zu_dn, render_spans_16_c1_ns_t_nz_nf_zc_zu_dn, render_spans_16_c2_ns_t_nz_nf_zc_zu_dn,
render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn, render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn,
render_spans_16_c1_s_nt_nz_nf_zc_zu_dn, render_spans_16_c2_s_nt_nz_nf_zc_zu_dn, render_spans_16_c1_s_nt_nz_nf_zc_zu_dn, render_spans_16_c2_s_nt_nz_nf_zc_zu_dn,
render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn, render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn,
render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn, render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn,
render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn, render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn,
render_spans_16_c1_ns_nt_nz_f_zc_zu_dn, render_spans_16_c2_ns_nt_nz_f_zc_zu_dn, render_spans_16_c1_ns_nt_nz_f_zc_zu_dn, render_spans_16_c2_ns_nt_nz_f_zc_zu_dn,
render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn, render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn,
render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn, render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn,
render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn, render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn,
render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn, render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn,
render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn, render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn,
render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn, render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn,
render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn, render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn,
render_spans_16_c1_ns_nt_nz_nf_nzc_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_dn, render_spans_16_c1_ns_nt_nz_nf_nzc_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_dn,
render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn, render_spans_16_c1_ns_nt_z_nf_nzc_dn, render_spans_16_c2_ns_nt_z_nf_nzc_dn,
render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn, render_spans_16_c1_ns_t_nz_nf_nzc_dn, render_spans_16_c2_ns_t_nz_nf_nzc_dn,
render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn, render_spans_16_c1_ns_t_z_nf_nzc_dn, render_spans_16_c2_ns_t_z_nf_nzc_dn,
render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn, render_spans_16_c1_s_nt_nz_nf_nzc_dn, render_spans_16_c2_s_nt_nz_nf_nzc_dn,
render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn, render_spans_16_c1_s_nt_z_nf_nzc_dn, render_spans_16_c2_s_nt_z_nf_nzc_dn,
render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn, render_spans_16_c1_s_t_nz_nf_nzc_dn, render_spans_16_c2_s_t_nz_nf_nzc_dn,
render_spans_16_c1_s_t_z_nf_nzc_dn, render_spans_16_c2_s_t_z_nf_nzc_dn, render_spans_16_c1_s_t_z_nf_nzc_dn, render_spans_16_c2_s_t_z_nf_nzc_dn,
render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn, render_spans_16_c1_ns_nt_nz_f_nzc_dn, render_spans_16_c2_ns_nt_nz_f_nzc_dn,
render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn, render_spans_16_c1_ns_nt_z_f_nzc_dn, render_spans_16_c2_ns_nt_z_f_nzc_dn,
render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn, render_spans_16_c1_ns_t_nz_f_nzc_dn, render_spans_16_c2_ns_t_nz_f_nzc_dn,
render_spans_16_c1_ns_t_z_f_nzc_dn, render_spans_16_c2_ns_t_z_f_nzc_dn, render_spans_16_c1_ns_t_z_f_nzc_dn, render_spans_16_c2_ns_t_z_f_nzc_dn,
render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn, render_spans_16_c1_s_nt_nz_f_nzc_dn, render_spans_16_c2_s_nt_nz_f_nzc_dn,
render_spans_16_c1_s_nt_z_f_nzc_dn, render_spans_16_c2_s_nt_z_f_nzc_dn, render_spans_16_c1_s_nt_z_f_nzc_dn, render_spans_16_c2_s_nt_z_f_nzc_dn,
render_spans_16_c1_s_t_nz_f_nzc_dn, render_spans_16_c2_s_t_nz_f_nzc_dn, render_spans_16_c1_s_t_nz_f_nzc_dn, render_spans_16_c2_s_t_nz_f_nzc_dn,
render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn, render_spans_16_c1_s_t_z_f_nzc_dn, render_spans_16_c2_s_t_z_f_nzc_dn,
render_spans_16_c1_ns_nt_nz_nf_zc_dn, render_spans_16_c2_ns_nt_nz_nf_zc_dn, render_spans_16_c1_ns_nt_nz_nf_zc_dn, render_spans_16_c2_ns_nt_nz_nf_zc_dn,
render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn, render_spans_16_c1_ns_nt_z_nf_zc_dn, render_spans_16_c2_ns_nt_z_nf_zc_dn,
render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn, render_spans_16_c1_ns_t_nz_nf_zc_dn, render_spans_16_c2_ns_t_nz_nf_zc_dn,
render_spans_16_c1_ns_t_z_nf_zc_dn, render_spans_16_c2_ns_t_z_nf_zc_dn, render_spans_16_c1_ns_t_z_nf_zc_dn, render_spans_16_c2_ns_t_z_nf_zc_dn,
render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn, render_spans_16_c1_s_nt_nz_nf_zc_dn, render_spans_16_c2_s_nt_nz_nf_zc_dn,
render_spans_16_c1_s_nt_z_nf_zc_dn, render_spans_16_c2_s_nt_z_nf_zc_dn, render_spans_16_c1_s_nt_z_nf_zc_dn, render_spans_16_c2_s_nt_z_nf_zc_dn,
render_spans_16_c1_s_t_nz_nf_zc_dn, render_spans_16_c2_s_t_nz_nf_zc_dn, render_spans_16_c1_s_t_nz_nf_zc_dn, render_spans_16_c2_s_t_nz_nf_zc_dn,
render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn, render_spans_16_c1_s_t_z_nf_zc_dn, render_spans_16_c2_s_t_z_nf_zc_dn,
render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn, render_spans_16_c1_ns_nt_nz_f_zc_dn, render_spans_16_c2_ns_nt_nz_f_zc_dn,
render_spans_16_c1_ns_nt_z_f_zc_dn, render_spans_16_c2_ns_nt_z_f_zc_dn, render_spans_16_c1_ns_nt_z_f_zc_dn, render_spans_16_c2_ns_nt_z_f_zc_dn,
render_spans_16_c1_ns_t_nz_f_zc_dn, render_spans_16_c2_ns_t_nz_f_zc_dn, render_spans_16_c1_ns_t_nz_f_zc_dn, render_spans_16_c2_ns_t_nz_f_zc_dn,
render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn, render_spans_16_c1_ns_t_z_f_zc_dn, render_spans_16_c2_ns_t_z_f_zc_dn,
render_spans_16_c1_s_nt_nz_f_zc_dn, render_spans_16_c2_s_nt_nz_f_zc_dn, render_spans_16_c1_s_nt_nz_f_zc_dn, render_spans_16_c2_s_nt_nz_f_zc_dn,
render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn, render_spans_16_c1_s_nt_z_f_zc_dn, render_spans_16_c2_s_nt_z_f_zc_dn,
render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn, render_spans_16_c1_s_t_nz_f_zc_dn, render_spans_16_c2_s_t_nz_f_zc_dn,
render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn, render_spans_16_c1_s_t_z_f_zc_dn, render_spans_16_c2_s_t_z_f_zc_dn,
render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c1_ns_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_nzc_zu_dn,
render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c1_ns_nt_z_nf_nzc_zu_dn, render_spans_16_c2_ns_nt_z_nf_nzc_zu_dn,
render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c1_ns_t_nz_nf_nzc_zu_dn, render_spans_16_c2_ns_t_nz_nf_nzc_zu_dn,
render_spans_16_c1_ns_t_z_nf_nzc_zu_dn, render_spans_16_c2_ns_t_z_nf_nzc_zu_dn, render_spans_16_c1_ns_t_z_nf_nzc_zu_dn, render_spans_16_c2_ns_t_z_nf_nzc_zu_dn,
render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c1_s_nt_nz_nf_nzc_zu_dn, render_spans_16_c2_s_nt_nz_nf_nzc_zu_dn,
render_spans_16_c1_s_nt_z_nf_nzc_zu_dn, render_spans_16_c2_s_nt_z_nf_nzc_zu_dn, render_spans_16_c1_s_nt_z_nf_nzc_zu_dn, render_spans_16_c2_s_nt_z_nf_nzc_zu_dn,
render_spans_16_c1_s_t_nz_nf_nzc_zu_dn, render_spans_16_c2_s_t_nz_nf_nzc_zu_dn, render_spans_16_c1_s_t_nz_nf_nzc_zu_dn, render_spans_16_c2_s_t_nz_nf_nzc_zu_dn,
render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn, render_spans_16_c1_s_t_z_nf_nzc_zu_dn, render_spans_16_c2_s_t_z_nf_nzc_zu_dn,
render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c1_ns_nt_nz_f_nzc_zu_dn, render_spans_16_c2_ns_nt_nz_f_nzc_zu_dn,
render_spans_16_c1_ns_nt_z_f_nzc_zu_dn, render_spans_16_c2_ns_nt_z_f_nzc_zu_dn, render_spans_16_c1_ns_nt_z_f_nzc_zu_dn, render_spans_16_c2_ns_nt_z_f_nzc_zu_dn,
render_spans_16_c1_ns_t_nz_f_nzc_zu_dn, render_spans_16_c2_ns_t_nz_f_nzc_zu_dn, render_spans_16_c1_ns_t_nz_f_nzc_zu_dn, render_spans_16_c2_ns_t_nz_f_nzc_zu_dn,
render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn, render_spans_16_c1_ns_t_z_f_nzc_zu_dn, render_spans_16_c2_ns_t_z_f_nzc_zu_dn,
render_spans_16_c1_s_nt_nz_f_nzc_zu_dn, render_spans_16_c2_s_nt_nz_f_nzc_zu_dn, render_spans_16_c1_s_nt_nz_f_nzc_zu_dn, render_spans_16_c2_s_nt_nz_f_nzc_zu_dn,
render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn, render_spans_16_c1_s_nt_z_f_nzc_zu_dn, render_spans_16_c2_s_nt_z_f_nzc_zu_dn,
render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn, render_spans_16_c1_s_t_nz_f_nzc_zu_dn, render_spans_16_c2_s_t_nz_f_nzc_zu_dn,
render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn, render_spans_16_c1_s_t_z_f_nzc_zu_dn, render_spans_16_c2_s_t_z_f_nzc_zu_dn,
render_spans_16_c1_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c1_ns_nt_nz_nf_zc_zu_dn, render_spans_16_c2_ns_nt_nz_nf_zc_zu_dn,
render_spans_16_c1_ns_nt_z_nf_zc_zu_dn, render_spans_16_c2_ns_nt_z_nf_zc_zu_dn, render_spans_16_c1_ns_nt_z_nf_zc_zu_dn, render_spans_16_c2_ns_nt_z_nf_zc_zu_dn,
render_spans_16_c1_ns_t_nz_nf_zc_zu_dn, render_spans_16_c2_ns_t_nz_nf_zc_zu_dn, render_spans_16_c1_ns_t_nz_nf_zc_zu_dn, render_spans_16_c2_ns_t_nz_nf_zc_zu_dn,
render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn, render_spans_16_c1_ns_t_z_nf_zc_zu_dn, render_spans_16_c2_ns_t_z_nf_zc_zu_dn,
render_spans_16_c1_s_nt_nz_nf_zc_zu_dn, render_spans_16_c2_s_nt_nz_nf_zc_zu_dn, render_spans_16_c1_s_nt_nz_nf_zc_zu_dn, render_spans_16_c2_s_nt_nz_nf_zc_zu_dn,
render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn, render_spans_16_c1_s_nt_z_nf_zc_zu_dn, render_spans_16_c2_s_nt_z_nf_zc_zu_dn,
render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn, render_spans_16_c1_s_t_nz_nf_zc_zu_dn, render_spans_16_c2_s_t_nz_nf_zc_zu_dn,
render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn, render_spans_16_c1_s_t_z_nf_zc_zu_dn, render_spans_16_c2_s_t_z_nf_zc_zu_dn,
render_spans_16_c1_ns_nt_nz_f_zc_zu_dn, render_spans_16_c2_ns_nt_nz_f_zc_zu_dn, render_spans_16_c1_ns_nt_nz_f_zc_zu_dn, render_spans_16_c2_ns_nt_nz_f_zc_zu_dn,
render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn, render_spans_16_c1_ns_nt_z_f_zc_zu_dn, render_spans_16_c2_ns_nt_z_f_zc_zu_dn,
render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn, render_spans_16_c1_ns_t_nz_f_zc_zu_dn, render_spans_16_c2_ns_t_nz_f_zc_zu_dn,
render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn, render_spans_16_c1_ns_t_z_f_zc_zu_dn, render_spans_16_c2_ns_t_z_f_zc_zu_dn,
render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn, render_spans_16_c1_s_nt_nz_f_zc_zu_dn, render_spans_16_c2_s_nt_nz_f_zc_zu_dn,
render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn, render_spans_16_c1_s_nt_z_f_zc_zu_dn, render_spans_16_c2_s_nt_z_f_zc_zu_dn,
render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn, render_spans_16_c1_s_t_nz_f_zc_zu_dn, render_spans_16_c2_s_t_nz_f_zc_zu_dn,
render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn, render_spans_16_c1_s_t_z_f_zc_zu_dn, render_spans_16_c2_s_t_z_f_zc_zu_dn,
}; };

2
src/mame/video/rdptpipe.c
View File

@ -1,4 +1,4 @@
#define RELATIVE(x, y) (((((x) >> 3) - (y)) << 3) | (x & 7)) #define RELATIVE(x, y) (((((x) >> 3) - (y)) << 3) | (x & 7))
#if defined(COPY) #if defined(COPY)
#define CLAMP(SSS, SST, maxs, maxt) \ #define CLAMP(SSS, SST, maxs, maxt) \

8
src/mame/video/rdpzcomp.h
View File

@ -17,8 +17,8 @@ INLINE UINT32 z_compare_NIMR_NAA_Z3(void* fb, UINT8* hb, UINT16* zb, UINT8* zhb,
static UINT32 (*rdp_z_compare_func[16])(void*, UINT8*, UINT16*, UINT8*, UINT32, UINT16) = static UINT32 (*rdp_z_compare_func[16])(void*, UINT8*, UINT16*, UINT8*, UINT32, UINT16) =
{ {
z_compare_IMR_AA_Z0, z_compare_NIMR_AA_Z0, z_compare_IMR_NAA_Z0, z_compare_NIMR_NAA_Z0, z_compare_IMR_AA_Z0, z_compare_NIMR_AA_Z0, z_compare_IMR_NAA_Z0, z_compare_NIMR_NAA_Z0,
z_compare_IMR_AA_Z1, z_compare_NIMR_AA_Z1, z_compare_IMR_NAA_Z1, z_compare_NIMR_NAA_Z1, z_compare_IMR_AA_Z1, z_compare_NIMR_AA_Z1, z_compare_IMR_NAA_Z1, z_compare_NIMR_NAA_Z1,
z_compare_IMR_AA_Z2, z_compare_NIMR_AA_Z2, z_compare_IMR_NAA_Z2, z_compare_NIMR_NAA_Z2, z_compare_IMR_AA_Z2, z_compare_NIMR_AA_Z2, z_compare_IMR_NAA_Z2, z_compare_NIMR_NAA_Z2,
z_compare_IMR_AA_Z3, z_compare_NIMR_AA_Z3, z_compare_IMR_NAA_Z3, z_compare_NIMR_NAA_Z3 z_compare_IMR_AA_Z3, z_compare_NIMR_AA_Z3, z_compare_IMR_NAA_Z3, z_compare_NIMR_NAA_Z3
}; };

6
src/mame/video/taito_b.c
View File

@ -62,8 +62,8 @@ VIDEO_START( taitob_color_order0 )
/*this is the basic layout used in: Nastar, Ashura Blaster, Hit the Ice, Rambo3, Tetris*/ /*this is the basic layout used in: Nastar, Ashura Blaster, Hit the Ice, Rambo3, Tetris*/
/*Note that in both this and color order 1 /*Note that in both this and color order 1
* pixel_color_base/color_granularity is equal to sprites color base. * pixel_color_base/color_granularity is equal to sprites color base.
* Pure coincidence ?*/ * Pure coincidence ?*/
b_sp_color_base = 0x40 * 16; /*sprites */ b_sp_color_base = 0x40 * 16; /*sprites */
@ -394,7 +394,7 @@ VIDEO_UPDATE( taitob )
VIDEO_EOF( taitob ) VIDEO_EOF( taitob )
{ {
const device_config *tc0180vcu = devtag_get_device(machine, "tc0180vcu"); const device_config *tc0180vcu = devtag_get_device(machine, "tc0180vcu");
UINT8 video_control = tc0180vcu_get_videoctrl(tc0180vcu, 0); UINT8 video_control = tc0180vcu_get_videoctrl(tc0180vcu, 0);
UINT8 framebuffer_page = tc0180vcu_get_fb_page(tc0180vcu, 0); UINT8 framebuffer_page = tc0180vcu_get_fb_page(tc0180vcu, 0);

2
src/version.c
View File

@ -10,4 +10,4 @@
***************************************************************************/ ***************************************************************************/
extern const char build_version[]; extern const char build_version[];
const char build_version[] = "0.135u4 ("__DATE__")"; const char build_version[] = "0.136 ("__DATE__")";