mirror of
https://github.com/holub/mame
synced 2025-07-04 17:38:08 +03:00
-netlist: Various fixes: [Ryan Holtz]
* 7473: Made device only transition on a falling clock. * 74161: Inverted Clear and Clock inputs to match datasheet. * 74260: Fixed number of inputs. * Am2847: Fixed shift register size (was 160 bits, should have been 80 bits) * DM9334: Inverted C and E inputs to match datasheet.
This commit is contained in:
parent
66abfa8e6d
commit
2987115966
@ -1,7 +1,7 @@
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// license:BSD-3-Clause
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// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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// copyright-holders:Ryan Holtz
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/*
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/*
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* nld_74161.c
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* nld_74161.cpp
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*
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*
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*/
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*/
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@ -20,8 +20,8 @@ namespace netlist
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, m_B(*this, "B")
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, m_B(*this, "B")
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, m_C(*this, "C")
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, m_C(*this, "C")
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, m_D(*this, "D")
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, m_D(*this, "D")
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, m_CLEAR(*this, "CLEAR")
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, m_CLRQ(*this, "CLRQ")
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, m_LOAD(*this, "LOAD")
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, m_LOADQ(*this, "LOADQ")
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, m_CLK(*this, "CLK")
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, m_CLK(*this, "CLK")
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, m_ENABLEP(*this, "ENABLEP")
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, m_ENABLEP(*this, "ENABLEP")
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, m_ENABLET(*this, "ENABLET")
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, m_ENABLET(*this, "ENABLET")
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@ -40,8 +40,8 @@ namespace netlist
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logic_input_t m_B;
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logic_input_t m_B;
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logic_input_t m_C;
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logic_input_t m_C;
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logic_input_t m_D;
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logic_input_t m_D;
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logic_input_t m_CLEAR;
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logic_input_t m_CLRQ;
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logic_input_t m_LOAD;
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logic_input_t m_LOADQ;
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logic_input_t m_CLK;
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logic_input_t m_CLK;
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logic_input_t m_ENABLEP;
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logic_input_t m_ENABLEP;
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logic_input_t m_ENABLET;
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logic_input_t m_ENABLET;
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@ -57,7 +57,7 @@ namespace netlist
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{
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{
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NETLIB_CONSTRUCTOR_DERIVED(74161_dip, 74161)
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NETLIB_CONSTRUCTOR_DERIVED(74161_dip, 74161)
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{
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{
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register_subalias("1", m_CLEAR);
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register_subalias("1", m_CLRQ);
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register_subalias("2", m_CLK);
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register_subalias("2", m_CLK);
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register_subalias("3", m_A);
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register_subalias("3", m_A);
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register_subalias("4", m_B);
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register_subalias("4", m_B);
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@ -65,7 +65,7 @@ namespace netlist
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register_subalias("6", m_D);
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register_subalias("6", m_D);
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register_subalias("7", m_ENABLEP);
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register_subalias("7", m_ENABLEP);
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register_subalias("9", m_LOAD);
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register_subalias("9", m_LOADQ);
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register_subalias("10", m_ENABLET);
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register_subalias("10", m_ENABLET);
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register_subalias("11", m_Q[3]);
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register_subalias("11", m_Q[3]);
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register_subalias("12", m_Q[2]);
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register_subalias("12", m_Q[2]);
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@ -94,31 +94,33 @@ namespace netlist
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NETLIB_UPDATE(74161)
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NETLIB_UPDATE(74161)
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{
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{
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netlist_sig_t tRippleCarryOut = 0;
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netlist_sig_t tRippleCarryOut = 0;
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if (m_CLEAR())
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if (!m_CLRQ())
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{
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{
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m_cnt = 0;
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m_cnt = 0;
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}
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}
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else if (m_CLK() && !m_last_CLK)
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else if (m_CLK() && !m_last_CLK)
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{
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{
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if (m_LOAD())
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if (!m_LOADQ())
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{
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{
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m_cnt = (m_D() << 3) | (m_C() << 2)
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m_cnt = (m_D() << 3) | (m_C() << 2)
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| (m_B() << 1) | (m_A() << 0);
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| (m_B() << 1) | (m_A() << 0);
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}
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}
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else if (m_ENABLET() && m_ENABLEP())
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else if (m_ENABLET() && m_ENABLEP())
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{
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{
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m_cnt++;
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m_cnt++;
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if (m_cnt > MAXCNT)
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if (m_cnt > MAXCNT)
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m_cnt = 0;
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m_cnt = 0;
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}
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}
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}
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}
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if (m_ENABLET() && (m_cnt == MAXCNT))
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if (m_ENABLET() && (m_cnt == MAXCNT))
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tRippleCarryOut = 1;
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{
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tRippleCarryOut = 1;
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}
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m_last_CLK = m_CLK();
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m_last_CLK = m_CLK();
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for (std::size_t i=0; i<4; i++)
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for (std::size_t i=0; i<4; i++)
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m_Q[i].push((m_cnt >> i) & 1, delay[i]);
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m_Q[i].push((m_cnt >> i) & 1, delay[i]);
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m_RCO.push(tRippleCarryOut, NLTIME_FROM_NS(20)); //FIXME
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m_RCO.push(tRippleCarryOut, NLTIME_FROM_NS(20)); //FIXME
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@ -27,21 +27,17 @@
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#include "nl_setup.h"
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#include "nl_setup.h"
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#define TTL_74161(name, cA, cB, cC, cD, cCLEAR, cLOAD, cCLK, cENABLEP, cENABLET, cQA, cQB, cQC, cQD) \
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#define TTL_74161(name, cA, cB, cC, cD, cCLRQ, cLOADQ, cCLK, cENABLEP, cENABLET) \
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NET_REGISTER_DEV(TTL_74161, name) \
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NET_REGISTER_DEV(TTL_74161, name) \
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NET_CONNECT(name, A, cA) \
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NET_CONNECT(name, A, cA) \
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NET_CONNECT(name, B, cB) \
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NET_CONNECT(name, B, cB) \
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NET_CONNECT(name, C, cC) \
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NET_CONNECT(name, C, cC) \
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NET_CONNECT(name, D, cD) \
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NET_CONNECT(name, D, cD) \
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NET_CONNECT(name, CLEAR, cCLEAR) \
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NET_CONNECT(name, CLRQ, cCLRQ) \
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NET_CONNECT(name, LOAD, cLOAD) \
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NET_CONNECT(name, LOADQ, cLOADQ) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, ENABLEP, cENABLEP) \
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NET_CONNECT(name, ENABLEP, cENABLEP) \
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NET_CONNECT(name, ENABLET, cENABLET) \
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NET_CONNECT(name, ENABLET, cENABLET)
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NET_CONNECT(name, QA, cQA) \
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NET_CONNECT(name, QB, cQB) \
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NET_CONNECT(name, QC, cQC) \
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NET_CONNECT(name, QD, cQD) \
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#define TTL_74161_DIP(name) \
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#define TTL_74161_DIP(name) \
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NET_REGISTER_DEV(TTL_74161_DIP, name)
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NET_REGISTER_DEV(TTL_74161_DIP, name)
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// license:BSD-3-Clause
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// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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// copyright-holders:Ryan Holtz
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/*
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/*
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* nld_74166.c
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* nld_74166.cpp
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*
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*
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*/
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*/
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#include "nl_setup.h"
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#include "nl_setup.h"
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#define TTL_74166(name) \
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#define TTL_74166(name, cCLK, cCLKINH, cSH_LDQ, cSER, cA, cB, cC, cD, cE, cF, cG, cH, cCLRQ) \
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NET_REGISTER_DEV(TTL_74166, name)
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NET_REGISTER_DEV(TTL_74166, name) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, CLKINH, cCLKINH) \
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NET_CONNECT(name, SH_LDQ, cSH_LDQ) \
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NET_CONNECT(name, SER, cSER) \
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NET_CONNECT(name, A, cA) \
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NET_CONNECT(name, B, cB) \
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NET_CONNECT(name, C, cC) \
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NET_CONNECT(name, D, cD) \
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NET_CONNECT(name, E, cE) \
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NET_CONNECT(name, F, cF) \
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NET_CONNECT(name, G, cG) \
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NET_CONNECT(name, H, cH) \
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NET_CONNECT(name, CLRQ, cCLRQ)
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#define TTL_74166_DIP(name) \
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#define TTL_74166_DIP(name) \
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NET_REGISTER_DEV(TTL_74166_DIP, name)
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NET_REGISTER_DEV(TTL_74166_DIP, name)
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#include "nl_setup.h"
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#include "nl_setup.h"
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#define TTL_74174(name) \
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#define TTL_74174(name, cCLK, cD1, cD2, cD3, cD4, cD5, cD6, cCLRQ) \
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NET_REGISTER_DEV(TTL_74174, name)
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NET_REGISTER_DEV(TTL_74174, name) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, D1, cD1) \
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NET_CONNECT(name, D2, cD2) \
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NET_CONNECT(name, D3, cD3) \
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NET_CONNECT(name, D4, cD4) \
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NET_CONNECT(name, D5, cD5) \
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NET_CONNECT(name, D6, cD6) \
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NET_CONNECT(name, CLRQ, cCLRQ)
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#define TTL_74174_DIP(name) \
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#define TTL_74174_DIP(name) \
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NET_REGISTER_DEV(TTL_74174_DIP, name)
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NET_REGISTER_DEV(TTL_74174_DIP, name)
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#include "nl_setup.h"
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#include "nl_setup.h"
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#define TTL_74175(name) \
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#define TTL_74175(name, cCLK, cD1, cD2, cD3, cD4, cCLRQ) \
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NET_REGISTER_DEV(TTL_74175, name)
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NET_REGISTER_DEV(TTL_74175, name) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, D1, cD1) \
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NET_CONNECT(name, D2, cD2) \
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NET_CONNECT(name, D3, cD3) \
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NET_CONNECT(name, D4, cD4) \
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NET_CONNECT(name, CLRQ, cCLRQ)
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#define TTL_74175_DIP(name) \
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#define TTL_74175_DIP(name) \
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NET_REGISTER_DEV(TTL_74175_DIP, name)
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NET_REGISTER_DEV(TTL_74175_DIP, name)
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#include "nl_setup.h"
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#include "nl_setup.h"
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#define TTL_74193(name) \
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#define TTL_74193(name, cA, cB, cC, cD, cCLEAR, cLOADQ, cCU, cCD) \
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NET_REGISTER_DEV(TTL_74193, name)
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NET_REGISTER_DEV(TTL_74193, name) \
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NET_CONNECT(name, A, cA) \
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NET_CONNECT(name, B, cB) \
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NET_CONNECT(name, C, cC) \
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NET_CONNECT(name, D, cD) \
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NET_CONNECT(name, CLEAR, cCLEAR) \
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NET_CONNECT(name, LOADQ, cLOADQ) \
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NET_CONNECT(name, CU, cCU) \
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NET_CONNECT(name, CD, cCD)
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#define TTL_74193_DIP(name) \
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#define TTL_74193_DIP(name) \
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NET_REGISTER_DEV(TTL_74193_DIP, name)
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NET_REGISTER_DEV(TTL_74193_DIP, name)
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@ -18,11 +18,14 @@ namespace netlist
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, m_J(*this, "J")
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, m_J(*this, "J")
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, m_K(*this, "K")
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, m_K(*this, "K")
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, m_CLRQ(*this, "CLRQ")
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, m_CLRQ(*this, "CLRQ")
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, m_last_CLK(*this, "m_last_CLK", 0)
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, m_q(*this, "m_q", 0)
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, m_Q(*this, "Q")
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, m_Q(*this, "Q")
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, m_QQ(*this, "QQ")
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, m_QQ(*this, "QQ")
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{
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{
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}
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}
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NETLIB_RESETI();
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NETLIB_UPDATEI();
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NETLIB_UPDATEI();
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public:
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public:
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@ -31,7 +34,10 @@ namespace netlist
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logic_input_t m_K;
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logic_input_t m_K;
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logic_input_t m_CLRQ;
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logic_input_t m_CLRQ;
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logic_output_t m_Q;
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state_var<unsigned> m_last_CLK;
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state_var<unsigned> m_q;
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logic_output_t m_Q;
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logic_output_t m_QQ;
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logic_output_t m_QQ;
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};
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};
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NETLIB_SUB(7473A) m_2;
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NETLIB_SUB(7473A) m_2;
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};
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};
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NETLIB_UPDATE(7473)
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NETLIB_RESET(7473)
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{
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m_last_CLK = 0;
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}
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NETLIB_UPDATE(7473)
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{
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{
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const auto JK = (m_J() << 1) | m_K();
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const auto JK = (m_J() << 1) | m_K();
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unsigned q = 0;
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if (m_CLRQ())
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if (!m_CLRQ())
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{
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{
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q = m_Q.net().Q();
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if (!m_CLK() && m_last_CLK)
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switch (JK)
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{
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{
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switch (JK)
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case 1: // (!m_J) & m_K))
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{
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q = 0;
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case 1: // (!m_J) & m_K))
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break;
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m_q = 0;
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case 2: // (m_J) & !m_K))
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break;
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q = 1;
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case 2: // (m_J) & !m_K))
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break;
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m_q = 1;
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case 3: // (m_J) & m_K))
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break;
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q ^= 1;
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case 3: // (m_J) & m_K))
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break;
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m_q ^= 1;
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default:
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break;
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case 0:
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default:
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break;
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case 0:
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}
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break;
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}
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}
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}
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}
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m_Q.push(q, NLTIME_FROM_NS(20)); // FIXME: timing
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m_last_CLK = m_CLK();
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m_QQ.push(q ^ 1, NLTIME_FROM_NS(20)); // FIXME: timing
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m_Q.push(m_q, NLTIME_FROM_NS(20)); // FIXME: timing
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m_QQ.push(m_q ^ 1, NLTIME_FROM_NS(20)); // FIXME: timing
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}
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}
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NETLIB_DEVICE_IMPL(7473)
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NETLIB_DEVICE_IMPL(7473)
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* Naming conventions follow Texas instruments datasheet
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* Naming conventions follow Texas instruments datasheet
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*
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*
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* FIXME: Currently, only the 73 is implemented.
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* FIXME: Currently, only the 73 is implemented.
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* The 73 uses the same model.
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* The 73A uses the same model.
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*
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*
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*/
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*/
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@ -27,7 +27,7 @@ namespace netlist
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logic_input_t m_RC;
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logic_input_t m_RC;
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logic_input_t m_IN;
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logic_input_t m_IN;
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state_var<uint_fast32_t[5]> m_buffer;
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state_var<uint_fast16_t[5]> m_buffer;
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logic_output_t m_OUT;
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logic_output_t m_OUT;
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};
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};
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@ -98,16 +98,14 @@ namespace netlist
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NETLIB_UPDATE(AM2847)
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NETLIB_UPDATE(AM2847)
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{
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{
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unsigned cp = m_CP();
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if (m_last_CP && !m_CP())
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if (cp != m_last_CP && cp != 0)
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{
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{
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m_A.shift();
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m_A.shift();
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m_B.shift();
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m_B.shift();
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m_C.shift();
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m_C.shift();
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m_D.shift();
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m_D.shift();
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}
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}
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m_last_CP = m_CP();
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m_last_CP = m_CP();
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}
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}
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inline NETLIB_FUNC_VOID(Am2847_shifter, shift, (void))
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inline NETLIB_FUNC_VOID(Am2847_shifter, shift, (void))
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@ -116,9 +114,9 @@ namespace netlist
|
|||||||
uint_fast32_t in = (m_RC() ? out : m_IN());
|
uint_fast32_t in = (m_RC() ? out : m_IN());
|
||||||
for (std::size_t i=0; i < 5; i++)
|
for (std::size_t i=0; i < 5; i++)
|
||||||
{
|
{
|
||||||
uint_fast32_t shift_in = (i == 4) ? in : m_buffer[i + 1];
|
uint_fast16_t shift_in = (i == 4) ? in : m_buffer[i + 1];
|
||||||
m_buffer[i] >>= 1;
|
m_buffer[i] >>= 1;
|
||||||
m_buffer[i] |= shift_in << 31;
|
m_buffer[i] |= shift_in << 15;
|
||||||
}
|
}
|
||||||
|
|
||||||
m_OUT.push(out, NLTIME_FROM_NS(200));
|
m_OUT.push(out, NLTIME_FROM_NS(200));
|
||||||
|
@ -23,8 +23,17 @@
|
|||||||
|
|
||||||
#include "nl_setup.h"
|
#include "nl_setup.h"
|
||||||
|
|
||||||
#define TTL_AM2847(name) \
|
#define TTL_AM2847(name, cCP, cINA, cINB, cINC, cIND, cRCA, cRCB, cRCC, cRCD) \
|
||||||
NET_REGISTER_DEV(TTL_AM2847, name)
|
NET_REGISTER_DEV(TTL_AM2847, name) \
|
||||||
|
NET_CONNECT(name, CP, cCP) \
|
||||||
|
NET_CONNECT(name, INA, cINA) \
|
||||||
|
NET_CONNECT(name, INB, cINB) \
|
||||||
|
NET_CONNECT(name, INC, cINC) \
|
||||||
|
NET_CONNECT(name, IND, cIND) \
|
||||||
|
NET_CONNECT(name, RCA, cRCA) \
|
||||||
|
NET_CONNECT(name, RCB, cRCB) \
|
||||||
|
NET_CONNECT(name, RCC, cRCC) \
|
||||||
|
NET_CONNECT(name, RCD, cRCD)
|
||||||
|
|
||||||
#define TTL_AM2847_DIP(name) \
|
#define TTL_AM2847_DIP(name) \
|
||||||
NET_REGISTER_DEV(TTL_AM2847_DIP, name)
|
NET_REGISTER_DEV(TTL_AM2847_DIP, name)
|
||||||
|
@ -14,13 +14,13 @@ namespace netlist
|
|||||||
NETLIB_OBJECT(DM9334)
|
NETLIB_OBJECT(DM9334)
|
||||||
{
|
{
|
||||||
NETLIB_CONSTRUCTOR(DM9334)
|
NETLIB_CONSTRUCTOR(DM9334)
|
||||||
, m_C(*this, "C")
|
, m_CQ(*this, "CQ")
|
||||||
, m_E(*this, "E")
|
, m_EQ(*this, "EQ")
|
||||||
, m_D(*this, "D")
|
, m_D(*this, "D")
|
||||||
, m_A(*this, {{"A0", "A1", "A2"}})
|
, m_A(*this, {{"A0", "A1", "A2"}})
|
||||||
, m_Q(*this, {{"Q0", "Q1", "Q2", "Q3", "Q4", "Q5", "Q6", "Q7"}})
|
, m_Q(*this, {{"Q0", "Q1", "Q2", "Q3", "Q4", "Q5", "Q6", "Q7"}})
|
||||||
, m_last_C(*this, "m_last_C", 0)
|
, m_last_CQ(*this, "m_last_CQ", 0)
|
||||||
, m_last_E(*this, "m_last_E", 0)
|
, m_last_EQ(*this, "m_last_EQ", 0)
|
||||||
, m_last_D(*this, "m_last_D", 0)
|
, m_last_D(*this, "m_last_D", 0)
|
||||||
, m_last_A(*this, "m_last_A", 0)
|
, m_last_A(*this, "m_last_A", 0)
|
||||||
, m_last_Q(*this, "m_last_Q", 0)
|
, m_last_Q(*this, "m_last_Q", 0)
|
||||||
@ -31,14 +31,14 @@ namespace netlist
|
|||||||
NETLIB_UPDATEI();
|
NETLIB_UPDATEI();
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
logic_input_t m_C;
|
logic_input_t m_CQ;
|
||||||
logic_input_t m_E;
|
logic_input_t m_EQ;
|
||||||
logic_input_t m_D;
|
logic_input_t m_D;
|
||||||
object_array_t<logic_input_t, 3> m_A;
|
object_array_t<logic_input_t, 3> m_A;
|
||||||
object_array_t<logic_output_t, 8> m_Q;
|
object_array_t<logic_output_t, 8> m_Q;
|
||||||
|
|
||||||
state_var<unsigned> m_last_C;
|
state_var<unsigned> m_last_CQ;
|
||||||
state_var<unsigned> m_last_E;
|
state_var<unsigned> m_last_EQ;
|
||||||
state_var<unsigned> m_last_D;
|
state_var<unsigned> m_last_D;
|
||||||
state_var<unsigned> m_last_A;
|
state_var<unsigned> m_last_A;
|
||||||
state_var<unsigned> m_last_Q;
|
state_var<unsigned> m_last_Q;
|
||||||
@ -61,16 +61,16 @@ namespace netlist
|
|||||||
register_subalias("11", m_Q[6]);
|
register_subalias("11", m_Q[6]);
|
||||||
register_subalias("12", m_Q[7]);
|
register_subalias("12", m_Q[7]);
|
||||||
register_subalias("13", m_D);
|
register_subalias("13", m_D);
|
||||||
register_subalias("14", m_E);
|
register_subalias("14", m_EQ);
|
||||||
register_subalias("15", m_C);
|
register_subalias("15", m_CQ);
|
||||||
|
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
NETLIB_RESET(DM9334)
|
NETLIB_RESET(DM9334)
|
||||||
{
|
{
|
||||||
m_last_C = 0;
|
m_last_CQ = 0;
|
||||||
m_last_E = 0;
|
m_last_EQ = 0;
|
||||||
m_last_D = 0;
|
m_last_D = 0;
|
||||||
m_last_A = 0;
|
m_last_A = 0;
|
||||||
m_last_Q = 0;
|
m_last_Q = 0;
|
||||||
@ -101,9 +101,9 @@ namespace netlist
|
|||||||
delay = NLTIME_FROM_NS(35);
|
delay = NLTIME_FROM_NS(35);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else if (m_E() != m_last_E)
|
else if (m_EQ() != m_last_EQ)
|
||||||
{
|
{
|
||||||
if (m_last_E)
|
if (m_last_EQ)
|
||||||
{
|
{
|
||||||
delay = NLTIME_FROM_NS(27);
|
delay = NLTIME_FROM_NS(27);
|
||||||
}
|
}
|
||||||
@ -115,9 +115,9 @@ namespace netlist
|
|||||||
|
|
||||||
uint_fast8_t q = m_last_Q;
|
uint_fast8_t q = m_last_Q;
|
||||||
|
|
||||||
if (!m_C())
|
if (!m_CQ())
|
||||||
{
|
{
|
||||||
if (m_E())
|
if (m_EQ())
|
||||||
{
|
{
|
||||||
q = 0;
|
q = 0;
|
||||||
}
|
}
|
||||||
@ -126,23 +126,20 @@ namespace netlist
|
|||||||
q = m_D() << a;
|
q = m_D() << a;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else if(!m_E())
|
else if(!m_EQ())
|
||||||
{
|
{
|
||||||
q &= ~(1 << a);
|
q &= ~(1 << a);
|
||||||
q |= (m_D() << a);
|
q |= (m_D() << a);
|
||||||
}
|
}
|
||||||
|
|
||||||
m_last_C = m_C();
|
m_last_CQ = m_CQ();
|
||||||
m_last_E = m_E();
|
m_last_EQ = m_EQ();
|
||||||
m_last_D = m_D();
|
m_last_D = m_D();
|
||||||
m_last_A = a;
|
m_last_A = a;
|
||||||
|
m_last_Q = q;
|
||||||
|
|
||||||
if (q != m_last_Q)
|
for (std::size_t i=0; i<8; i++)
|
||||||
{
|
m_Q[i].push((q >> i) & 1, delay);
|
||||||
m_last_Q = q;
|
|
||||||
for (std::size_t i=0; i<8; i++)
|
|
||||||
m_Q[i].push((q >> i) & 1, delay);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
NETLIB_DEVICE_IMPL(DM9334)
|
NETLIB_DEVICE_IMPL(DM9334)
|
||||||
|
@ -67,10 +67,10 @@
|
|||||||
|
|
||||||
#include "nl_setup.h"
|
#include "nl_setup.h"
|
||||||
|
|
||||||
#define TTL_DM9334(name, cC, cE, cD, cA0, cA1, cA2) \
|
#define TTL_DM9334(name, cCQ, cEQ, cD, cA0, cA1, cA2) \
|
||||||
NET_REGISTER_DEV(TTL_DM9334, name) \
|
NET_REGISTER_DEV(TTL_DM9334, name) \
|
||||||
NET_CONNECT(name, C, cC) \
|
NET_CONNECT(name, CQ, cCQ) \
|
||||||
NET_CONNECT(name, E, cE) \
|
NET_CONNECT(name, EQ, cEQ) \
|
||||||
NET_CONNECT(name, D, cD) \
|
NET_CONNECT(name, D, cD) \
|
||||||
NET_CONNECT(name, A0, cA0) \
|
NET_CONNECT(name, A0, cA0) \
|
||||||
NET_CONNECT(name, A1, cA1) \
|
NET_CONNECT(name, A1, cA1) \
|
||||||
|
@ -826,7 +826,7 @@ NETLIST_START(TTL74XX_lib)
|
|||||||
TT_FAMILY("74XX")
|
TT_FAMILY("74XX")
|
||||||
TRUTHTABLE_END()
|
TRUTHTABLE_END()
|
||||||
|
|
||||||
TRUTHTABLE_START(TTL_74260_GATE, 2, 1, "")
|
TRUTHTABLE_START(TTL_74260_GATE, 5, 1, "")
|
||||||
TT_HEAD("A,B,C,D,E|Q ")
|
TT_HEAD("A,B,C,D,E|Q ")
|
||||||
TT_LINE("0,0,0,0,0|1|10")
|
TT_LINE("0,0,0,0,0|1|10")
|
||||||
TT_LINE("X,X,X,X,1|0|12")
|
TT_LINE("X,X,X,X,1|0|12")
|
||||||
@ -837,7 +837,7 @@ NETLIST_START(TTL74XX_lib)
|
|||||||
TT_FAMILY("74XX")
|
TT_FAMILY("74XX")
|
||||||
TRUTHTABLE_END()
|
TRUTHTABLE_END()
|
||||||
|
|
||||||
TRUTHTABLE_START(TTL_74260_NOR, 2, 1, "A,B,C,D,E")
|
TRUTHTABLE_START(TTL_74260_NOR, 5, 1, "A,B,C,D,E")
|
||||||
TT_HEAD("A,B,C,D,E|Q ")
|
TT_HEAD("A,B,C,D,E|Q ")
|
||||||
TT_LINE("0,0,0,0,0|1|10")
|
TT_LINE("0,0,0,0,0|1|10")
|
||||||
TT_LINE("X,X,X,X,1|0|12")
|
TT_LINE("X,X,X,X,1|0|12")
|
||||||
|
@ -187,7 +187,7 @@
|
|||||||
|
|
||||||
|
|
||||||
#define TTL_74260_GATE(name) \
|
#define TTL_74260_GATE(name) \
|
||||||
NET_REGISTER_DEV(TTL_7486_GATE, name)
|
NET_REGISTER_DEV(TTL_74260_GATE, name)
|
||||||
|
|
||||||
#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \
|
#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \
|
||||||
NET_REGISTER_DEV(TTL_74260_NOR, name) \
|
NET_REGISTER_DEV(TTL_74260_NOR, name) \
|
||||||
|
Loading…
Reference in New Issue
Block a user