-netlist: Various fixes: [Ryan Holtz]

* 7473: Made device only transition on a falling clock.
 * 74161: Inverted Clear and Clock inputs to match datasheet.
 * 74260: Fixed number of inputs.
 * Am2847: Fixed shift register size (was 160 bits, should have been 80 bits)
 * DM9334: Inverted C and E inputs to match datasheet.
This commit is contained in:
therealmogminer@gmail.com 2016-12-21 20:19:21 +01:00
parent 66abfa8e6d
commit 2987115966
15 changed files with 148 additions and 95 deletions

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@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*
* nld_74161.c
* nld_74161.cpp
*
*/
@ -20,8 +20,8 @@ namespace netlist
, m_B(*this, "B")
, m_C(*this, "C")
, m_D(*this, "D")
, m_CLEAR(*this, "CLEAR")
, m_LOAD(*this, "LOAD")
, m_CLRQ(*this, "CLRQ")
, m_LOADQ(*this, "LOADQ")
, m_CLK(*this, "CLK")
, m_ENABLEP(*this, "ENABLEP")
, m_ENABLET(*this, "ENABLET")
@ -40,8 +40,8 @@ namespace netlist
logic_input_t m_B;
logic_input_t m_C;
logic_input_t m_D;
logic_input_t m_CLEAR;
logic_input_t m_LOAD;
logic_input_t m_CLRQ;
logic_input_t m_LOADQ;
logic_input_t m_CLK;
logic_input_t m_ENABLEP;
logic_input_t m_ENABLET;
@ -57,7 +57,7 @@ namespace netlist
{
NETLIB_CONSTRUCTOR_DERIVED(74161_dip, 74161)
{
register_subalias("1", m_CLEAR);
register_subalias("1", m_CLRQ);
register_subalias("2", m_CLK);
register_subalias("3", m_A);
register_subalias("4", m_B);
@ -65,7 +65,7 @@ namespace netlist
register_subalias("6", m_D);
register_subalias("7", m_ENABLEP);
register_subalias("9", m_LOAD);
register_subalias("9", m_LOADQ);
register_subalias("10", m_ENABLET);
register_subalias("11", m_Q[3]);
register_subalias("12", m_Q[2]);
@ -94,13 +94,13 @@ namespace netlist
NETLIB_UPDATE(74161)
{
netlist_sig_t tRippleCarryOut = 0;
if (m_CLEAR())
if (!m_CLRQ())
{
m_cnt = 0;
}
else if (m_CLK() && !m_last_CLK)
{
if (m_LOAD())
if (!m_LOADQ())
{
m_cnt = (m_D() << 3) | (m_C() << 2)
| (m_B() << 1) | (m_A() << 0);
@ -114,7 +114,9 @@ namespace netlist
}
if (m_ENABLET() && (m_cnt == MAXCNT))
{
tRippleCarryOut = 1;
}
m_last_CLK = m_CLK();

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@ -27,21 +27,17 @@
#include "nl_setup.h"
#define TTL_74161(name, cA, cB, cC, cD, cCLEAR, cLOAD, cCLK, cENABLEP, cENABLET, cQA, cQB, cQC, cQD) \
#define TTL_74161(name, cA, cB, cC, cD, cCLRQ, cLOADQ, cCLK, cENABLEP, cENABLET) \
NET_REGISTER_DEV(TTL_74161, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLEAR, cCLEAR) \
NET_CONNECT(name, LOAD, cLOAD) \
NET_CONNECT(name, CLRQ, cCLRQ) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, ENABLEP, cENABLEP) \
NET_CONNECT(name, ENABLET, cENABLET) \
NET_CONNECT(name, QA, cQA) \
NET_CONNECT(name, QB, cQB) \
NET_CONNECT(name, QC, cQC) \
NET_CONNECT(name, QD, cQD) \
NET_CONNECT(name, ENABLET, cENABLET)
#define TTL_74161_DIP(name) \
NET_REGISTER_DEV(TTL_74161_DIP, name)

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@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*
* nld_74166.c
* nld_74166.cpp
*
*/

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@ -28,8 +28,21 @@
#include "nl_setup.h"
#define TTL_74166(name) \
NET_REGISTER_DEV(TTL_74166, name)
#define TTL_74166(name, cCLK, cCLKINH, cSH_LDQ, cSER, cA, cB, cC, cD, cE, cF, cG, cH, cCLRQ) \
NET_REGISTER_DEV(TTL_74166, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, CLKINH, cCLKINH) \
NET_CONNECT(name, SH_LDQ, cSH_LDQ) \
NET_CONNECT(name, SER, cSER) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, E, cE) \
NET_CONNECT(name, F, cF) \
NET_CONNECT(name, G, cG) \
NET_CONNECT(name, H, cH) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74166_DIP(name) \
NET_REGISTER_DEV(TTL_74166_DIP, name)

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@ -38,8 +38,17 @@
#include "nl_setup.h"
#define TTL_74174(name) \
NET_REGISTER_DEV(TTL_74174, name)
#define TTL_74174(name, cCLK, cD1, cD2, cD3, cD4, cD5, cD6, cCLRQ) \
NET_REGISTER_DEV(TTL_74174, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, D5, cD5) \
NET_CONNECT(name, D6, cD6) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74174_DIP(name) \
NET_REGISTER_DEV(TTL_74174_DIP, name)

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@ -38,8 +38,15 @@
#include "nl_setup.h"
#define TTL_74175(name) \
NET_REGISTER_DEV(TTL_74175, name)
#define TTL_74175(name, cCLK, cD1, cD2, cD3, cD4, cCLRQ) \
NET_REGISTER_DEV(TTL_74175, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74175_DIP(name) \
NET_REGISTER_DEV(TTL_74175_DIP, name)

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@ -28,8 +28,16 @@
#include "nl_setup.h"
#define TTL_74193(name) \
NET_REGISTER_DEV(TTL_74193, name)
#define TTL_74193(name, cA, cB, cC, cD, cCLEAR, cLOADQ, cCU, cCD) \
NET_REGISTER_DEV(TTL_74193, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLEAR, cCLEAR) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, CU, cCU) \
NET_CONNECT(name, CD, cCD)
#define TTL_74193_DIP(name) \
NET_REGISTER_DEV(TTL_74193_DIP, name)

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@ -18,11 +18,14 @@ namespace netlist
, m_J(*this, "J")
, m_K(*this, "K")
, m_CLRQ(*this, "CLRQ")
, m_last_CLK(*this, "m_last_CLK", 0)
, m_q(*this, "m_q", 0)
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
{
}
NETLIB_RESETI();
NETLIB_UPDATEI();
public:
@ -31,6 +34,9 @@ namespace netlist
logic_input_t m_K;
logic_input_t m_CLRQ;
state_var<unsigned> m_last_CLK;
state_var<unsigned> m_q;
logic_output_t m_Q;
logic_output_t m_QQ;
};
@ -98,33 +104,41 @@ namespace netlist
NETLIB_SUB(7473A) m_2;
};
NETLIB_RESET(7473)
{
m_last_CLK = 0;
}
NETLIB_UPDATE(7473)
{
const auto JK = (m_J() << 1) | m_K();
unsigned q = 0;
if (!m_CLRQ())
if (m_CLRQ())
{
if (!m_CLK() && m_last_CLK)
{
q = m_Q.net().Q();
switch (JK)
{
case 1: // (!m_J) & m_K))
q = 0;
m_q = 0;
break;
case 2: // (m_J) & !m_K))
q = 1;
m_q = 1;
break;
case 3: // (m_J) & m_K))
q ^= 1;
m_q ^= 1;
break;
default:
case 0:
break;
}
}
}
m_Q.push(q, NLTIME_FROM_NS(20)); // FIXME: timing
m_QQ.push(q ^ 1, NLTIME_FROM_NS(20)); // FIXME: timing
m_last_CLK = m_CLK();
m_Q.push(m_q, NLTIME_FROM_NS(20)); // FIXME: timing
m_QQ.push(m_q ^ 1, NLTIME_FROM_NS(20)); // FIXME: timing
}
NETLIB_DEVICE_IMPL(7473)

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@ -53,7 +53,7 @@
* Naming conventions follow Texas instruments datasheet
*
* FIXME: Currently, only the 73 is implemented.
* The 73 uses the same model.
* The 73A uses the same model.
*
*/

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@ -27,7 +27,7 @@ namespace netlist
logic_input_t m_RC;
logic_input_t m_IN;
state_var<uint_fast32_t[5]> m_buffer;
state_var<uint_fast16_t[5]> m_buffer;
logic_output_t m_OUT;
};
@ -98,15 +98,13 @@ namespace netlist
NETLIB_UPDATE(AM2847)
{
unsigned cp = m_CP();
if (cp != m_last_CP && cp != 0)
if (m_last_CP && !m_CP())
{
m_A.shift();
m_B.shift();
m_C.shift();
m_D.shift();
}
m_last_CP = m_CP();
}
@ -116,9 +114,9 @@ namespace netlist
uint_fast32_t in = (m_RC() ? out : m_IN());
for (std::size_t i=0; i < 5; i++)
{
uint_fast32_t shift_in = (i == 4) ? in : m_buffer[i + 1];
uint_fast16_t shift_in = (i == 4) ? in : m_buffer[i + 1];
m_buffer[i] >>= 1;
m_buffer[i] |= shift_in << 31;
m_buffer[i] |= shift_in << 15;
}
m_OUT.push(out, NLTIME_FROM_NS(200));

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@ -23,8 +23,17 @@
#include "nl_setup.h"
#define TTL_AM2847(name) \
NET_REGISTER_DEV(TTL_AM2847, name)
#define TTL_AM2847(name, cCP, cINA, cINB, cINC, cIND, cRCA, cRCB, cRCC, cRCD) \
NET_REGISTER_DEV(TTL_AM2847, name) \
NET_CONNECT(name, CP, cCP) \
NET_CONNECT(name, INA, cINA) \
NET_CONNECT(name, INB, cINB) \
NET_CONNECT(name, INC, cINC) \
NET_CONNECT(name, IND, cIND) \
NET_CONNECT(name, RCA, cRCA) \
NET_CONNECT(name, RCB, cRCB) \
NET_CONNECT(name, RCC, cRCC) \
NET_CONNECT(name, RCD, cRCD)
#define TTL_AM2847_DIP(name) \
NET_REGISTER_DEV(TTL_AM2847_DIP, name)

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@ -14,13 +14,13 @@ namespace netlist
NETLIB_OBJECT(DM9334)
{
NETLIB_CONSTRUCTOR(DM9334)
, m_C(*this, "C")
, m_E(*this, "E")
, m_CQ(*this, "CQ")
, m_EQ(*this, "EQ")
, m_D(*this, "D")
, m_A(*this, {{"A0", "A1", "A2"}})
, m_Q(*this, {{"Q0", "Q1", "Q2", "Q3", "Q4", "Q5", "Q6", "Q7"}})
, m_last_C(*this, "m_last_C", 0)
, m_last_E(*this, "m_last_E", 0)
, m_last_CQ(*this, "m_last_CQ", 0)
, m_last_EQ(*this, "m_last_EQ", 0)
, m_last_D(*this, "m_last_D", 0)
, m_last_A(*this, "m_last_A", 0)
, m_last_Q(*this, "m_last_Q", 0)
@ -31,14 +31,14 @@ namespace netlist
NETLIB_UPDATEI();
protected:
logic_input_t m_C;
logic_input_t m_E;
logic_input_t m_CQ;
logic_input_t m_EQ;
logic_input_t m_D;
object_array_t<logic_input_t, 3> m_A;
object_array_t<logic_output_t, 8> m_Q;
state_var<unsigned> m_last_C;
state_var<unsigned> m_last_E;
state_var<unsigned> m_last_CQ;
state_var<unsigned> m_last_EQ;
state_var<unsigned> m_last_D;
state_var<unsigned> m_last_A;
state_var<unsigned> m_last_Q;
@ -61,16 +61,16 @@ namespace netlist
register_subalias("11", m_Q[6]);
register_subalias("12", m_Q[7]);
register_subalias("13", m_D);
register_subalias("14", m_E);
register_subalias("15", m_C);
register_subalias("14", m_EQ);
register_subalias("15", m_CQ);
}
};
NETLIB_RESET(DM9334)
{
m_last_C = 0;
m_last_E = 0;
m_last_CQ = 0;
m_last_EQ = 0;
m_last_D = 0;
m_last_A = 0;
m_last_Q = 0;
@ -101,9 +101,9 @@ namespace netlist
delay = NLTIME_FROM_NS(35);
}
}
else if (m_E() != m_last_E)
else if (m_EQ() != m_last_EQ)
{
if (m_last_E)
if (m_last_EQ)
{
delay = NLTIME_FROM_NS(27);
}
@ -115,9 +115,9 @@ namespace netlist
uint_fast8_t q = m_last_Q;
if (!m_C())
if (!m_CQ())
{
if (m_E())
if (m_EQ())
{
q = 0;
}
@ -126,24 +126,21 @@ namespace netlist
q = m_D() << a;
}
}
else if(!m_E())
else if(!m_EQ())
{
q &= ~(1 << a);
q |= (m_D() << a);
}
m_last_C = m_C();
m_last_E = m_E();
m_last_CQ = m_CQ();
m_last_EQ = m_EQ();
m_last_D = m_D();
m_last_A = a;
if (q != m_last_Q)
{
m_last_Q = q;
for (std::size_t i=0; i<8; i++)
m_Q[i].push((q >> i) & 1, delay);
}
}
NETLIB_DEVICE_IMPL(DM9334)
NETLIB_DEVICE_IMPL(DM9334_dip)

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@ -67,10 +67,10 @@
#include "nl_setup.h"
#define TTL_DM9334(name, cC, cE, cD, cA0, cA1, cA2) \
#define TTL_DM9334(name, cCQ, cEQ, cD, cA0, cA1, cA2) \
NET_REGISTER_DEV(TTL_DM9334, name) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, E, cE) \
NET_CONNECT(name, CQ, cCQ) \
NET_CONNECT(name, EQ, cEQ) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \

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@ -826,7 +826,7 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_74260_GATE, 2, 1, "")
TRUTHTABLE_START(TTL_74260_GATE, 5, 1, "")
TT_HEAD("A,B,C,D,E|Q ")
TT_LINE("0,0,0,0,0|1|10")
TT_LINE("X,X,X,X,1|0|12")
@ -837,7 +837,7 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_74260_NOR, 2, 1, "A,B,C,D,E")
TRUTHTABLE_START(TTL_74260_NOR, 5, 1, "A,B,C,D,E")
TT_HEAD("A,B,C,D,E|Q ")
TT_LINE("0,0,0,0,0|1|10")
TT_LINE("X,X,X,X,1|0|12")

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@ -187,7 +187,7 @@
#define TTL_74260_GATE(name) \
NET_REGISTER_DEV(TTL_7486_GATE, name)
NET_REGISTER_DEV(TTL_74260_GATE, name)
#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \
NET_REGISTER_DEV(TTL_74260_NOR, name) \