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https://github.com/holub/mame
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z8: Register overhaul
- Create address space for internal register file - Add port output registers to debug state - Lock out interrupts on reset until EI
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AJR
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commit
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@ -30,6 +30,7 @@ protected:
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{
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Z8_PC, Z8_SP, Z8_RP,
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Z8_IMR, Z8_IRQ, Z8_IPR,
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Z8_P0, Z8_P1, Z8_P2, Z8_P3,
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Z8_P01M, Z8_P3M, Z8_P2M,
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Z8_PRE0, Z8_T0, Z8_PRE1, Z8_T1, Z8_TMR,
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@ -66,14 +67,17 @@ protected:
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void program_map(address_map &map);
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void preprogrammed_map(address_map &map);
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void register_map(address_map &map);
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private:
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address_space_config m_program_config;
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address_space_config m_data_config;
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address_space_config m_register_config;
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address_space *m_program;
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memory_access_cache<0, 0, ENDIANNESS_BIG> *m_cache;
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address_space *m_data;
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address_space *m_regs;
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// callbacks
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devcb_read8 m_input_cb[4];
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@ -81,43 +85,93 @@ private:
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uint32_t m_rom_size;
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/* registers */
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uint16_t m_pc; /* program counter */
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uint16_t m_ppc; /* program counter at last opcode fetch */
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uint8_t m_r[256]; /* register file */
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uint8_t m_input[4]; /* port input latches */
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uint8_t m_output[4]; /* port output latches */
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uint8_t m_t0; /* timer 0 current count */
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uint8_t m_t1; /* timer 1 current count */
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// basic registers
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uint16_t m_pc; // program counter
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uint16_t m_ppc; // program counter at last opcode fetch
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PAIR16 m_sp; // stack pointer (8-bit for internal stack, 16-bit for external stack)
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uint8_t m_rp; // register pointer
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uint8_t m_flags; // condition flags
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uint8_t m_imr; // interrupt mask
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uint8_t m_irq; // interrupt request
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uint8_t m_ipr; // interrupt priority
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/* fake registers */
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uint16_t m_fake_sp; /* fake stack pointer */
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uint8_t m_fake_r[16]; /* fake working registers */
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// port registers
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uint8_t m_input[4]; // port input latches
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uint8_t m_output[4]; // port output latches
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uint8_t m_p01m; // port 0/1 mode
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uint8_t m_p2m; // port 2 mode
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uint8_t m_p3m; // port 3 mode
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/* interrupts */
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int m_irq_line[4]; /* IRQ line state */
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// timer registers
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uint8_t m_tmr; // timer mode
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uint8_t m_t[2]; // initial values
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uint8_t m_count[2]; // current counts
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uint8_t m_pre[2]; // prescalers
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// fake registers
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uint8_t m_fake_r[16]; // fake working registers
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// interrupts
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int m_irq_line[4]; // IRQ line state
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bool m_irq_taken;
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bool m_irq_initialized; // IRQ must be unlocked by EI after reset
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/* execution logic */
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int m_icount; /* instruction counter */
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// execution logic
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int32_t m_icount; // instruction counter
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/* timers */
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// timers
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emu_timer *m_t0_timer;
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emu_timer *m_t1_timer;
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TIMER_CALLBACK_MEMBER( t0_tick );
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TIMER_CALLBACK_MEMBER( t1_tick );
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void request_interrupt(int irq);
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void take_interrupt(int irq);
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void process_interrupts();
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uint8_t p0_read();
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void p0_write(uint8_t data);
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uint8_t p1_read();
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void p1_write(uint8_t data);
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uint8_t p2_read();
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void p2_write(uint8_t data);
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uint8_t p3_read();
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void p3_write(uint8_t data);
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uint8_t sio_read();
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void sio_write(uint8_t data);
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uint8_t tmr_read();
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void tmr_write(uint8_t data);
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uint8_t t0_read();
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void t0_write(uint8_t data);
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uint8_t t1_read();
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void t1_write(uint8_t data);
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void pre0_write(uint8_t data);
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void pre1_write(uint8_t data);
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void p01m_write(uint8_t data);
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void p2m_write(uint8_t data);
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void p3m_write(uint8_t data);
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void ipr_write(uint8_t data);
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uint8_t irq_read();
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void irq_write(uint8_t data);
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uint8_t imr_read();
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void imr_write(uint8_t data);
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uint8_t flags_read();
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void flags_write(uint8_t data);
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uint8_t rp_read();
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void rp_write(uint8_t data);
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uint8_t sph_read();
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void sph_write(uint8_t data);
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uint8_t spl_read();
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void spl_write(uint8_t data);
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inline uint16_t mask_external_address(uint16_t addr);
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inline uint8_t fetch();
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inline uint8_t fetch_opcode();
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inline uint16_t fetch_word();
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inline uint8_t register_read(uint8_t offset);
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inline uint8_t register_read(uint8_t offset) { return m_regs->read_byte(offset); }
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inline uint16_t register_pair_read(uint8_t offset);
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inline void register_write(uint8_t offset, uint8_t data);
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inline void register_write(uint8_t offset, uint8_t data) { m_regs->write_byte(offset, data); }
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inline void register_pair_write(uint8_t offset, uint16_t data);
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inline uint8_t get_working_register(int offset);
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inline uint8_t get_register(uint8_t offset);
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@ -17,7 +17,7 @@
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#define IR get_intermediate_register(get_register(fetch()))
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#define RR get_intermediate_register(get_register(fetch()))
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#define IM fetch()
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#define flag(_flag) ((m_r[Z8_REGISTER_FLAGS] & Z8_FLAGS##_##_flag) ? 1 : 0)
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#define flag(_flag) ((m_flags & Z8_FLAGS_##_flag) ? 1 : 0)
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#define mode_r1_r2(_func) \
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uint8_t dst_src = fetch();\
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@ -37,7 +37,7 @@
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_func(dst, src);
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#define mode_IR2_R1(_func) \
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uint8_t src = m_r[read(R)];\
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uint8_t src = register_read(read(R));\
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uint8_t dst = R;\
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_func(dst, src);
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@ -550,14 +550,14 @@ INSTRUCTION( iret )
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{
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/* FLAGS <- @SP
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SP <- SP + 1 */
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register_write(Z8_REGISTER_FLAGS, stack_pop_byte());
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flags_write(stack_pop_byte());
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/* PC <- @SP
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SP <- SP + 2 */
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m_pc = stack_pop_word();
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/* IMR (7) <- 1 */
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m_r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE;
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m_imr |= Z8_IMR_ENABLE;
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}
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INSTRUCTION( ret )
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@ -773,10 +773,10 @@ INSTRUCTION( swap_IR1 ) { mode_IR1(swap) }
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CPU CONTROL INSTRUCTIONS
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***************************************************************************/
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INSTRUCTION( ccf ) { m_r[Z8_REGISTER_FLAGS] ^= Z8_FLAGS_C; }
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INSTRUCTION( di ) { m_r[Z8_REGISTER_IMR] &= ~Z8_IMR_ENABLE; }
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INSTRUCTION( ei ) { m_r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE; }
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INSTRUCTION( ccf ) { m_flags ^= Z8_FLAGS_C; }
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INSTRUCTION( di ) { m_imr &= ~Z8_IMR_ENABLE; }
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INSTRUCTION( ei ) { m_imr |= Z8_IMR_ENABLE; m_irq_initialized = true; }
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INSTRUCTION( nop ) { /* no operation */ }
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INSTRUCTION( rcf ) { set_flag_c(0); }
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INSTRUCTION( scf ) { set_flag_c(1); }
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INSTRUCTION( srp_IM ) { m_r[Z8_REGISTER_RP] = fetch(); }
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INSTRUCTION( srp_IM ) { rp_write(fetch()); }
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