Merge pull request #1821 from Bavarese/patch-21
DEC Rainbow 100: correct cursor position in REGIS
This commit is contained in:
R. Belmont
GitHub
commit
29e89fda5b
@ -2,7 +2,7 @@
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// ENABLE BY UNCOMMENTING. ADDITIONALLY, SET SMOOTH SCROLL IN EMULATION (DISABLE BY SETTING JUMP SCROLL. To enter SETUP hit ScrollLock)-
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//#define BOOST_DEBUG_PERFORMANCE
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/* GDC COLOR EMULATION
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//-------------------- Differences to VT240: ---------------------------------------------------
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// - Registers of graphics option not directly mapped (indirect access via mode register)
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@ -754,24 +754,23 @@ UPD7220_DISPLAY_PIXELS_MEMBER( rainbow_state::hgdc_display_pixels )
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return; // no output from graphics option
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}
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address = ( m_GDC_SCROLL_BUFFER[ ((address & 0x7FC0) >> 7) & 0xff ] << 7) | (address & 0x7F);
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// ********************* GET BITMAP DATA FOR 4 PLANES ***************************************
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// _READ_ BIT MAP from 2 or 4 planes (plane 0 is least, plane 3 most significant). See page 42 / 43
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if(m_GDC_MODE_REGISTER & GDC_MODE_HIGHRES)
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{
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plane0 = m_video_ram[((address & 0x7fff) + 0x00000) >> 1];
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plane1 = m_video_ram[((address & 0x7fff) + 0x10000) >> 1];
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plane2 = plane3 = 0;
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address = ( m_GDC_SCROLL_BUFFER[ ((address & 0x7FC0) >> 7) & 0xff ] << 7) | (address & 0x7F);
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plane0 = m_video_ram[((address & 0x7fff) + 0x00000) >> 1];
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plane1 = m_video_ram[((address & 0x7fff) + 0x10000) >> 1];
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plane2 = plane3 = 0;
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}
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else
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else
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{
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// MED.RESOLUTION (4 planes, 4 color bits, 16 color map entries / 16 (4) MONOCHROME SHADES)
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// MANUAL SAYS: (GDC "sees" 4 planes X 16 bits X 8K words)!
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plane0 = m_video_ram[((address & 0x3fff) + 0x00000) >> 1];
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plane1 = m_video_ram[((address & 0x3fff) + 0x10000) >> 1];
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plane2 = m_video_ram[((address & 0x3fff) + 0x20000) >> 1];
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plane3 = m_video_ram[((address & 0x3fff) + 0x30000) >> 1];
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address = ( m_GDC_SCROLL_BUFFER[ ((address & 0x3FC0) >> 7) & 0xff ] << 7) | (address & 0x7F);
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// MED.RESOLUTION (4 planes, 4 color bits, 16 color map entries / 16 -or 4- MONOCHROME SHADES)
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plane0 = m_video_ram[((address & 0x3fff) + 0x00000) >> 1];
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plane1 = m_video_ram[((address & 0x3fff) + 0x10000) >> 1];
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plane2 = m_video_ram[((address & 0x3fff) + 0x20000) >> 1];
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plane3 = m_video_ram[((address & 0x3fff) + 0x30000) >> 1];
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}
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bool mono = (m_inp13->read() == MONO_MONITOR) ? true : false; // 1 = MONO, 2 = COLOR, 3 = DUAL MONITOR
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@ -829,7 +828,7 @@ void rainbow_state::machine_start()
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if (rom[0xf4000 + 0x3ffc] == 0x31) // 100-B (5.01) 0x35 would test for V5.05
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{
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rom[0xf4000 + 0x0303] = 0x00; // disable CRC check
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rom[0xf4000 + 0x135e] = 0x00; // FLOPPY / RX-50 WORKAROUND: in case of Z80 RESPONSE FAILURE ($80 bit set in AL), do not block floppy access.
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rom[0xf4000 + 0x135e] = 0x00; // Floppy / RX-50 workaround: in case of Z80 RESPONSE FAILURE ($80 bit set in AL), do not block floppy access.
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rom[0xf4000 + 0x198F] = 0xeb; // cond.JMP to uncond.JMP (disables error message 60...)
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}
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@ -844,7 +843,7 @@ AM_RANGE(0x10000, END_OF_RAM) AM_RAM
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// There is a 2212 (256 x 4 bit) NVRAM from 0xed000 to 0xed0ff (*)
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// shadowed at $ec000 - $ecfff and from $ed100 - $edfff.
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// (*) ED000 - ED0FF is the area the DEC-100-B BIOS accesses and checks
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// (*) ED000 - ED0FF is the area the DEC-100-B Bios accesses and checks
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// - Specs say that the CPU has direct access to volatile RAM only.
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// So NVRAM is hidden and loads & saves are triggered within the
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@ -2727,36 +2726,32 @@ READ16_MEMBER(rainbow_state::vram_r)
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// NOTE: Rainbow has separate registers for fore and background.
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WRITE16_MEMBER(rainbow_state::vram_w)
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{
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if(!(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR))
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{
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// SCROLL_MAP IN BITMAP MODE ONLY...?
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if(m_GDC_MODE_REGISTER & GDC_MODE_HIGHRES)
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offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x3FC0) >> 6 ] << 6) | (offset & 0x3F);
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else
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offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x1FC0) >> 6 ] << 6) | (offset & 0x3F);
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}
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if(m_GDC_MODE_REGISTER & GDC_MODE_HIGHRES)
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offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x3FC0) >> 6 ] << 6) | (offset & 0x3F);
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else
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offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x1FC0) >> 6 ] << 6) | (offset & 0x3F);
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offset &= 0xffff; // same as in VT240?
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uint16_t chr = data; // VT240 : uint8_t
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if(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR) // VT240 : if(SELECT_VECTOR_PATTERN_REGISTER)
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{
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chr = BITSWAP8(m_vpat, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx);
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chr |= (chr << 8);
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if(m_patcnt-- == 0)
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{
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m_patcnt = m_patmult;
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if(m_patidx-- == 0)
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m_patidx = 7;
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}
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chr = BITSWAP8(m_vpat, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx);
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chr |= (chr << 8);
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if(m_patcnt-- == 0)
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{
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m_patcnt = m_patmult;
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if(m_patidx-- == 0)
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m_patidx = 7;
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}
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}
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else
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else
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{
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chr = m_GDC_WRITE_BUFFER[ m_GDC_write_buffer_index++ ];
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m_GDC_write_buffer_index &= 0xf;
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chr = m_GDC_WRITE_BUFFER[ m_GDC_write_buffer_index++ ];
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m_GDC_write_buffer_index &= 0xf;
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chr |= (m_GDC_WRITE_BUFFER[m_GDC_write_buffer_index++] << 8);
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m_GDC_write_buffer_index &= 0xf;
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chr |= (m_GDC_WRITE_BUFFER[m_GDC_write_buffer_index++] << 8);
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m_GDC_write_buffer_index &= 0xf;
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}
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if(m_GDC_MODE_REGISTER & GDC_MODE_ENABLE_WRITES) // 0x10
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@ -2791,10 +2786,10 @@ WRITE16_MEMBER(rainbow_state::vram_w)
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break;
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}
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if(!(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR)) // 0 : (NOT VECTOR MODE) Text Mode and Write Mask Batch
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if(!(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR)) // 0 : Text Mode and Write Mask Batch
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out = (out & ~m_GDC_WRITE_MASK) | (mem & m_GDC_WRITE_MASK); // // M_MASK (1st use)
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else
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out = (out & ~data) | (mem & data); // VECTOR MODE !
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out = (out & ~data) | (mem & data); // vector mode
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if(m_GDC_MODE_REGISTER & GDC_MODE_ENABLE_WRITES) // 0x10
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m_video_ram[(offset & 0xffff) + (0x8000 * i)] = out;
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@ -2845,13 +2840,13 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
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if(offset > 0) // Port $50 reset done @ boot ROM 1EB4/8 regardless if option present.
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if (m_inp7->read() != 1)
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{
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if(last_message != 1)
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{
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printf("\nCOLOR GRAPHICS ADAPTER INVOKED. PLEASE TURN ON THE APPROPRIATE DIP SWITCH, THEN RESTART.\n");
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printf("OFFSET: %x (PC=%x)\n", 0x50 +offset , machine().device("maincpu")->safe_pc());
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last_message = 1;
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}
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return;
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if(last_message != 1)
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{
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printf("\nCOLOR GRAPHICS ADAPTER INVOKED. PLEASE TURN ON THE APPROPRIATE DIP SWITCH, THEN RESTART.\n");
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printf("OFFSET: %x (PC=%x)\n", 0x50 +offset , machine().device("maincpu")->safe_pc());
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last_message = 1;
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}
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return;
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}
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switch(offset)
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@ -2860,15 +2855,12 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
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// FIXME: "Any write to this port also resynchronizes the
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// read/modify/write memory cycles of the Graphics Option to those of the GDC." (?)
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//if( (!(m_PORT50 & 1)) && (data & 1)) // PDF QV069 suggests 1 -> 0 -> 1
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if( data & 1 ) // ; most programs just set bit 0 (PACMAN).
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if( data & 1 ) // PDF QV069 suggests 1 -> 0 -> 1. Most programs just set bit 0 (PACMAN).
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{
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// Graphics option software reset (separate from GDC reset...)
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OPTION_GRFX_RESET
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OPTION_RESET_PATTERNS
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}
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m_PORT50 = data;
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break;
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case 1: // 51h - DATA loaded into register previously written to 53h.
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