From b2078dc4b231c72cd0185dc24fba46c7a730de93 Mon Sep 17 00:00:00 2001 From: Ted Green Date: Fri, 20 May 2016 08:25:06 -0600 Subject: [PATCH] (nw) Switched to using generic IDE PCI device --- src/mame/drivers/iteagle.cpp | 11 +- src/mame/machine/iteagle_fpga.cpp | 217 +++++------------------------- src/mame/machine/iteagle_fpga.h | 42 ++---- 3 files changed, 47 insertions(+), 223 deletions(-) diff --git a/src/mame/drivers/iteagle.cpp b/src/mame/drivers/iteagle.cpp index 9e725636055..b02384cb22a 100644 --- a/src/mame/drivers/iteagle.cpp +++ b/src/mame/drivers/iteagle.cpp @@ -109,6 +109,7 @@ www.multitech.com #include "video/voodoo_pci.h" #include "sound/es1373.h" #include "machine/iteagle_fpga.h" +#include "machine/pci-ide.h" //************************************* @@ -142,8 +143,8 @@ void iteagle_state::machine_reset() { } -#define PCI_ID_IDE ":pci:06.0" -// Primary IDE Control ":pci:06.1" +#define PCI_ID_PERIPH ":pci:06.0" +#define PCI_ID_IDE ":pci:06.1" // Seconday IDE Control ":pci:06.2" #define PCI_ID_SOUND ":pci:07.0" #define PCI_ID_FPGA ":pci:08.0" @@ -159,8 +160,10 @@ static MACHINE_CONFIG_START( iteagle, iteagle_state ) MCFG_PCI_ROOT_ADD( ":pci") MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu") - MCFG_ITEAGLE_IDE_ADD( PCI_ID_IDE) - MCFG_ITEAGLE_IDE_IRQ_ADD( ":maincpu", MIPS3_IRQ2) + MCFG_ITEAGLE_PERIPH_ADD( PCI_ID_PERIPH) + MCFG_IDE_PCI_ADD( PCI_ID_IDE, 0x1080C693, 0x00, 0x0) + MCFG_IDE_PCI_IRQ_ADD( ":maincpu", MIPS3_IRQ2) + MCFG_ITEAGLE_FPGA_ADD( PCI_ID_FPGA, ":maincpu", MIPS3_IRQ1, MIPS3_IRQ4) MCFG_ES1373_ADD( PCI_ID_SOUND) MCFG_SOUND_ROUTE(0, PCI_ID_SOUND":lspeaker", 1.0) diff --git a/src/mame/machine/iteagle_fpga.cpp b/src/mame/machine/iteagle_fpga.cpp index 7f4c6218f67..9ce5063bf5c 100644 --- a/src/mame/machine/iteagle_fpga.cpp +++ b/src/mame/machine/iteagle_fpga.cpp @@ -8,9 +8,7 @@ #define LOG_RTC (0) #define LOG_RAM (0) #define LOG_EEPROM (0) -#define LOG_IDE (0) -#define LOG_IDE_CTRL (0) -#define LOG_IDE_REG (0) +#define LOG_PERIPH (0) const device_type ITEAGLE_FPGA = &device_creator; @@ -521,7 +519,7 @@ machine_config_constructor iteagle_eeprom_device::device_mconfig_additions() con iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : pci_device(mconfig, ITEAGLE_EEPROM, "ITEagle EEPROM AT93C46", tag, owner, clock, "eeprom", __FILE__), - m_eeprom(*this, "eeprom"), m_sw_version(0) + m_eeprom(*this, "eeprom"), m_sw_version(0), m_hw_version(0) { } @@ -603,98 +601,57 @@ WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w ) } //************************************ -// Attached IDE Controller +// Attached Peripheral Controller //************************************ -const device_type ITEAGLE_IDE = &device_creator; +static MACHINE_CONFIG_FRAGMENT(eagle1) + MCFG_NVRAM_ADD_0FILL("eagle1_rtc") +MACHINE_CONFIG_END -DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_ide_device) +machine_config_constructor iteagle_periph_device::device_mconfig_additions() const +{ + return MACHINE_CONFIG_NAME(eagle1); +} + +const device_type ITEAGLE_PERIPH = &device_creator; + +DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_periph_device) AM_RANGE(0x000, 0x0cf) AM_READWRITE(ctrl_r, ctrl_w) ADDRESS_MAP_END - -DEVICE_ADDRESS_MAP_START(ide_map, 32, iteagle_ide_device) - AM_RANGE(0x0, 0x7) AM_READWRITE(ide_r, ide_w) -ADDRESS_MAP_END - -DEVICE_ADDRESS_MAP_START(ide_ctrl_map, 32, iteagle_ide_device) - AM_RANGE(0x0, 0x3) AM_READWRITE(ide_ctrl_r, ide_ctrl_w) -ADDRESS_MAP_END - -DEVICE_ADDRESS_MAP_START(ide2_map, 32, iteagle_ide_device) - AM_RANGE(0x0, 0x7) AM_READWRITE(ide2_r, ide2_w) -ADDRESS_MAP_END - -DEVICE_ADDRESS_MAP_START(ide2_ctrl_map, 32, iteagle_ide_device) - AM_RANGE(0x0, 0x3) AM_READWRITE(ide2_ctrl_r, ide2_ctrl_w) -ADDRESS_MAP_END - - -static MACHINE_CONFIG_FRAGMENT( iteagle_ide ) - MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", nullptr, true) - MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide_interrupt)) - MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM) - MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, nullptr, "cdrom", true) - MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(iteagle_ide_device, ide2_interrupt)) - MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM) -MACHINE_CONFIG_END - -machine_config_constructor iteagle_ide_device::device_mconfig_additions() const -{ - return MACHINE_CONFIG_NAME( iteagle_ide ); -} - -iteagle_ide_device::iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : pci_device(mconfig, ITEAGLE_IDE, "ITEagle IDE Controller", tag, owner, clock, "ide", __FILE__), - m_ide(*this, "ide"), - m_ide2(*this, "ide2"), - m_irq_num(-1) +iteagle_periph_device::iteagle_periph_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_device(mconfig, ITEAGLE_PERIPH, "ITEagle Peripheral Controller", tag, owner, clock, "periph", __FILE__), + m_rtc(*this, "eagle1_rtc") { } -void iteagle_ide_device::set_irq_info(const char *tag, const int irq_num) +void iteagle_periph_device::device_start() { - m_cpu_tag = tag; - m_irq_num = irq_num; -} - -void iteagle_ide_device::device_start() -{ - m_cpu = machine().device(m_cpu_tag); - m_irq_status = 0; pci_device::device_start(); - add_map(sizeof(m_ctrl_regs), M_IO, FUNC(iteagle_ide_device::ctrl_map)); + pci_device::set_multifunction_device(true); + add_map(sizeof(m_ctrl_regs), M_IO, FUNC(iteagle_periph_device::ctrl_map)); // ctrl defaults to base address 0x00000000 bank_infos[0].adr = 0x000; - - add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide_map)); - bank_infos[1].adr = 0x1f0; - add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide_ctrl_map)); - bank_infos[2].adr = 0x3f4; - add_map(0x8, M_IO, FUNC(iteagle_ide_device::ide2_map)); - bank_infos[3].adr = 0x170; - add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide2_ctrl_map)); - bank_infos[4].adr = 0x374; + m_rtc_regs.resize(0x100); + m_rtc_regs[0xa] = 0x20; // 32.768 MHz + m_rtc_regs[0xb] = 0x02; // 24-hour format + m_rtc->set_base(m_rtc_regs.data(), m_rtc_regs.size()); } -void iteagle_ide_device::device_reset() +void iteagle_periph_device::device_reset() { pci_device::device_reset(); memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs)); m_ctrl_regs[0x10/4] = 0x00000000; // 0x6=No SIMM, 0x2, 0x1, 0x0 = SIMM . Top 16 bits are compared to 0x3. Bit 0 might be lan chip present. - memset(m_rtc_regs, 0, sizeof(m_rtc_regs)); - m_rtc_regs[0xa] = 0x20; // 32.768 MHz - m_rtc_regs[0xb] = 0x02; // 24-hour format - m_irq_status = 0; } -READ32_MEMBER( iteagle_ide_device::ctrl_r ) +READ32_MEMBER( iteagle_periph_device::ctrl_r ) { system_time systime; UINT32 result = m_ctrl_regs[offset]; switch (offset) { case 0x0/4: - if (LOG_IDE_REG) + if (LOG_PERIPH) logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); osd_printf_debug("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; @@ -720,11 +677,11 @@ READ32_MEMBER( iteagle_ide_device::ctrl_r ) m_rtc_regs[0xd] = 0x80; // Reg D Valid time/ram Status result = (result & 0xffff00ff) | (m_rtc_regs[m_ctrl_regs[0x70/4]&0xff]<<8); } - if (LOG_IDE_REG) + if (LOG_PERIPH) logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; default: - if (LOG_IDE_REG) + if (LOG_PERIPH) logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); osd_printf_debug("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); break; @@ -732,22 +689,16 @@ READ32_MEMBER( iteagle_ide_device::ctrl_r ) return result; } -WRITE32_MEMBER( iteagle_ide_device::ctrl_w ) +WRITE32_MEMBER( iteagle_periph_device::ctrl_w ) { COMBINE_DATA(&m_ctrl_regs[offset]); switch (offset) { case 0x20/4: // IDE LED if (ACCESSING_BITS_16_23) { // Sets register index - if (LOG_IDE_REG) - logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); } else if (ACCESSING_BITS_24_31) { // Bit 25 is IDE LED - if (1 && LOG_IDE_REG) - logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); } else { - if (LOG_IDE_REG) - logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); } break; case 0x70/4: @@ -755,112 +706,8 @@ WRITE32_MEMBER( iteagle_ide_device::ctrl_w ) m_rtc_regs[m_ctrl_regs[0x70/4]&0xff] = (data>>8)&0xff; } default: - if (LOG_IDE_REG) - logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); break; } -} - -READ32_MEMBER( iteagle_ide_device::ide_r ) -{ - UINT32 result = m_ide->read_cs0(space, offset, mem_mask); - if (offset==0x4/4 && ACCESSING_BITS_24_31) { - if (m_irq_num!=-1 && m_irq_status==1) { - m_irq_status = 0; - m_cpu->set_input_line(m_irq_num, CLEAR_LINE); - if (LOG_IDE_CTRL) - logerror("%s:ide_r Clearing interrupt\n", machine().describe_context()); - } - } - if (LOG_IDE && mem_mask!=0xffffffff) - logerror("%s:ide_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); - return result; -} -WRITE32_MEMBER( iteagle_ide_device::ide_w ) -{ - m_ide->write_cs0(space, offset, data, mem_mask); - if (offset==0x4/4 && ACCESSING_BITS_24_31) { - if (m_irq_num!=-1 && m_irq_status==1) { - m_irq_status = 0; - m_cpu->set_input_line(m_irq_num, CLEAR_LINE); - if (LOG_IDE_CTRL) - logerror("%s:ide_w Clearing interrupt\n", machine().describe_context()); - } - } - if (LOG_IDE) - logerror("%s:ide_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); -} -READ32_MEMBER( iteagle_ide_device::ide_ctrl_r ) -{ - UINT32 result = m_ide->read_cs1(space, offset+1, mem_mask); - if (LOG_IDE_CTRL) - logerror("%s:ide_ctrl_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); - return result; -} -WRITE32_MEMBER( iteagle_ide_device::ide_ctrl_w ) -{ - m_ide->write_cs1(space, offset+1, data, mem_mask); - if (LOG_IDE_CTRL) - logerror("%s:ide_ctrl_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); -} -WRITE_LINE_MEMBER(iteagle_ide_device::ide_interrupt) -{ - if (m_irq_num!=-1 && m_irq_status==0) { - m_irq_status = 1; - m_cpu->set_input_line(m_irq_num, ASSERT_LINE); - if (LOG_IDE_CTRL) - logerror("%s:ide_interrupt Setting interrupt\n", machine().describe_context()); - } -} - -READ32_MEMBER( iteagle_ide_device::ide2_r ) -{ - UINT32 result = m_ide2->read_cs0(space, offset, mem_mask); - if (offset==0x4/4 && ACCESSING_BITS_24_31) { - if (m_irq_num!=-1 && m_irq_status==1) { - m_irq_status = 0; - m_cpu->set_input_line(m_irq_num, CLEAR_LINE); - if (LOG_IDE_CTRL) - logerror("%s:ide2_r Clearing interrupt\n", machine().describe_context()); - } - } - if (LOG_IDE) - logerror("%s:ide2_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); - return result; -} -WRITE32_MEMBER( iteagle_ide_device::ide2_w ) -{ - m_ide2->write_cs0(space, offset, data, mem_mask); - if (offset==0x4/4 && ACCESSING_BITS_24_31) { - if (m_irq_num!=-1 && m_irq_status==1) { - m_irq_status = 0; - m_cpu->set_input_line(m_irq_num, CLEAR_LINE); - if (LOG_IDE_CTRL) - logerror("%s:ide2_w Clearing interrupt\n", machine().describe_context()); - } - } - if (LOG_IDE) - logerror("%s:ide2_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); -} -READ32_MEMBER( iteagle_ide_device::ide2_ctrl_r ) -{ - UINT32 result = m_ide2->read_cs1(space, offset+1, mem_mask); - if (LOG_IDE_CTRL) - logerror("%s:ide2_ctrl_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); - return result; -} -WRITE32_MEMBER( iteagle_ide_device::ide2_ctrl_w ) -{ - m_ide2->write_cs1(space, offset+1, data, mem_mask); - if (LOG_IDE_CTRL) - logerror("%s:ide2_ctrl_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); -} -WRITE_LINE_MEMBER(iteagle_ide_device::ide2_interrupt) -{ - if (m_irq_num!=-1 && m_irq_status==0) { - m_irq_status = 1; - m_cpu->set_input_line(m_irq_num, ASSERT_LINE); - if (LOG_IDE_CTRL) - logerror("%s:ide2_interrupt Setting interrupt\n", machine().describe_context()); - } + if (LOG_PERIPH) + logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset * 4, data, mem_mask); } diff --git a/src/mame/machine/iteagle_fpga.h b/src/mame/machine/iteagle_fpga.h index 66d2238c2a9..27cf051e6ef 100644 --- a/src/mame/machine/iteagle_fpga.h +++ b/src/mame/machine/iteagle_fpga.h @@ -7,7 +7,7 @@ #define ITEAGLE_FPGA_H #include "machine/pci.h" -#include "machine/idectrl.h" +#include "machine/nvram.h" #include "machine/eepromser.h" //MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id) @@ -26,11 +26,9 @@ downcast(device)->set_info(_sw_version, _hw_version); // Mimic Cypress CY82C693 Peripheral Controller -#define MCFG_ITEAGLE_IDE_ADD(_tag) \ - MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_IDE, 0x1080C693, 0x00, 0x060100, 0x00) +#define MCFG_ITEAGLE_PERIPH_ADD(_tag) \ + MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_PERIPH, 0x1080C693, 0x00, 0x060100, 0x00) -#define MCFG_ITEAGLE_IDE_IRQ_ADD(_cpu_tag, _irq_num) \ - downcast(device)->set_irq_info(_cpu_tag, _irq_num); class iteagle_fpga_device : public pci_device, public device_nvram_interface @@ -117,54 +115,30 @@ private: DECLARE_WRITE32_MEMBER( eeprom_w ); }; -class iteagle_ide_device : public pci_device { +class iteagle_periph_device : public pci_device { public: - iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - // optional information overrides + iteagle_periph_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); virtual machine_config_constructor device_mconfig_additions() const override; - void set_irq_info(const char *tag, const int irq_num); - - required_device m_ide; - required_device m_ide2; - DECLARE_WRITE_LINE_MEMBER(ide_interrupt); - DECLARE_WRITE_LINE_MEMBER(ide2_interrupt); protected: virtual void device_start() override; virtual void device_reset() override; private: - const char *m_cpu_tag; - cpu_device *m_cpu; - int m_irq_num; - int m_irq_status; + optional_device m_rtc; UINT32 m_ctrl_regs[0xd0/4]; - UINT8 m_rtc_regs[0x100]; + std::vector m_rtc_regs; DECLARE_ADDRESS_MAP(ctrl_map, 32); - DECLARE_ADDRESS_MAP(ide_map, 32); - DECLARE_ADDRESS_MAP(ide_ctrl_map, 32); - DECLARE_ADDRESS_MAP(ide2_map, 32); - DECLARE_ADDRESS_MAP(ide2_ctrl_map, 32); DECLARE_READ32_MEMBER( ctrl_r ); DECLARE_WRITE32_MEMBER( ctrl_w ); - DECLARE_READ32_MEMBER( ide_r ); - DECLARE_WRITE32_MEMBER( ide_w ); - DECLARE_READ32_MEMBER( ide_ctrl_r ); - DECLARE_WRITE32_MEMBER( ide_ctrl_w ); - - DECLARE_READ32_MEMBER( ide2_r ); - DECLARE_WRITE32_MEMBER( ide2_w ); - DECLARE_READ32_MEMBER( ide2_ctrl_r ); - DECLARE_WRITE32_MEMBER( ide2_ctrl_w ); - }; extern const device_type ITEAGLE_FPGA; extern const device_type ITEAGLE_EEPROM; -extern const device_type ITEAGLE_IDE; +extern const device_type ITEAGLE_PERIPH; #endif