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https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
(nw) hpz80unk : added uarts and notes
This commit is contained in:
Robbbert
parent
d724f49d42
commit
2a40a00e2c
@ -12,17 +12,26 @@ Looks like roms are in 2 banks in range C000-FFFF.
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BASIC is included, if we can find out how to access it.
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Commands:
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A disassemble
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D
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Axxxx Disassemble (. to quit)
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DAxxxx,yyyy Ascii Dump of memory
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DBxxxx,yyyy Binary Dump of memory
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DHxxxx,yyyy Hex Dump of memory
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DOxxxx,yyyy Octal dump of memory
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G
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H
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L
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M
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P Read Port
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R
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U
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W Punch papertape
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X choose Q,V,R,P (Q to quit; others ask for ram and prom ranges)
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MMxxxx Modify Memory (. to quit)
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Pxx Binary Display of Port
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Pxx,xx Write to port
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RC ???
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RF ???
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RM ???
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RT ???
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UC Displays 11111111
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US ???
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UZ Displays FFFF
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W Punch papertape
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X choose Q,V,R,P (Q to quit; others ask for ram and prom ranges)
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Y nothing
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Z nothing
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@ -34,34 +43,60 @@ Z nothing
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#include "machine/terminal.h"
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#include "machine/ay31015.h"
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#include "bus/rs232/rs232.h"
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#define TERMINAL_TAG "terminal"
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class hpz80unk_state : public driver_device
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{
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public:
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hpz80unk_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_terminal(*this, TERMINAL_TAG),
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m_p_rom(*this, "p_rom")
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{
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}
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_p_rom(*this, "rom")
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, m_uart1(*this, "uart1")
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, m_uart2(*this, "uart2")
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, m_uart3(*this, "uart3")
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{ }
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required_device<cpu_device> m_maincpu;
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required_device<generic_terminal_device> m_terminal;
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DECLARE_READ8_MEMBER(port00_r);
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DECLARE_READ8_MEMBER(port01_r);
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DECLARE_READ8_MEMBER(port02_r);
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DECLARE_READ8_MEMBER(port03_r);
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DECLARE_READ8_MEMBER(port04_r);
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DECLARE_READ8_MEMBER(port0d_r);
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DECLARE_WRITE8_MEMBER(port01_w);
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DECLARE_WRITE8_MEMBER(port04_w);
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DECLARE_WRITE8_MEMBER(port0e_w);
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DECLARE_READ8_MEMBER(portfc_r);
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void kbd_put(u8 data);
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required_shared_ptr<uint8_t> m_p_rom;
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uint8_t m_term_data;
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private:
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uint8_t m_port02_data;
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virtual void machine_reset() override;
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required_device<cpu_device> m_maincpu;
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required_shared_ptr<uint8_t> m_p_rom;
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optional_device<ay31015_device> m_uart1;
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optional_device<ay31015_device> m_uart2;
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optional_device<ay31015_device> m_uart3;
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};
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READ8_MEMBER( hpz80unk_state::port00_r )
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{
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return (m_uart1->get_output_pin(AY31015_DAV) << 1) | (m_uart1->get_output_pin(AY31015_TBMT)) | 0xfc;
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}
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READ8_MEMBER( hpz80unk_state::port01_r )
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{
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m_uart1->set_input_pin(AY31015_RDAV, 0);
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uint8_t result = m_uart1->get_received_data();
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m_uart1->set_input_pin(AY31015_RDAV, 1);
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return result;}
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WRITE8_MEMBER( hpz80unk_state::port01_w )
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{
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m_uart1->set_transmit_data(data);
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}
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READ8_MEMBER( hpz80unk_state::port02_r )
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{
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m_port02_data ^= 1;
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@ -70,14 +105,30 @@ READ8_MEMBER( hpz80unk_state::port02_r )
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READ8_MEMBER( hpz80unk_state::port03_r )
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{
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return (m_term_data) ? 0xff : 0xfd;
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return (m_uart2->get_output_pin(AY31015_DAV) << 1) | (m_uart2->get_output_pin(AY31015_TBMT)) | 0xfc;
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}
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READ8_MEMBER( hpz80unk_state::port04_r )
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{
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uint8_t ret = m_term_data;
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m_term_data = 0;
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return ret;
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m_uart2->set_input_pin(AY31015_RDAV, 0);
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uint8_t result = m_uart2->get_received_data();
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m_uart2->set_input_pin(AY31015_RDAV, 1);
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return result;
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}
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WRITE8_MEMBER( hpz80unk_state::port04_w )
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{
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m_uart2->set_transmit_data(data);
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}
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READ8_MEMBER( hpz80unk_state::port0d_r )
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{
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return (m_uart3->get_output_pin(AY31015_DAV) << 1) | (m_uart3->get_output_pin(AY31015_TBMT)) | 0xfc;
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}
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WRITE8_MEMBER( hpz80unk_state::port0e_w )
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{
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m_uart3->set_transmit_data(data);
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}
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READ8_MEMBER( hpz80unk_state::portfc_r )
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@ -88,21 +139,33 @@ READ8_MEMBER( hpz80unk_state::portfc_r )
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static ADDRESS_MAP_START( hpz80unk_mem, AS_PROGRAM, 8, hpz80unk_state )
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x0000, 0xbfff) AM_RAM
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AM_RANGE(0xc000, 0xffff) AM_ROM AM_SHARE("p_rom")
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AM_RANGE(0xc000, 0xffff) AM_ROM AM_SHARE("rom")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( hpz80unk_io, AS_IO, 8, hpz80unk_state )
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ADDRESS_MAP_UNMAP_HIGH
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x01, 0x01) AM_DEVWRITE(TERMINAL_TAG, generic_terminal_device, write)
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AM_RANGE(0x00, 0x00) AM_READ(port00_r) // uart1 status
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AM_RANGE(0x01, 0x01) AM_READWRITE(port01_r,port01_w) // uart1 data
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AM_RANGE(0x02, 0x02) AM_READ(port02_r)
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AM_RANGE(0x03, 0x03) AM_READ(port03_r)
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AM_RANGE(0x04, 0x04) AM_READ(port04_r)
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AM_RANGE(0x03, 0x03) AM_READ(port03_r) // uart2 status
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AM_RANGE(0x04, 0x04) AM_READWRITE(port04_r,port04_w) // uart2 data
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AM_RANGE(0x0d, 0x0d) AM_READ(port0d_r) // uart3 status
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AM_RANGE(0x0e, 0x0e) AM_WRITE(port0e_w) // uart3 data
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AM_RANGE(0x1d, 0x1e) // top of memory is written here, little-endian
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AM_RANGE(0x1f, 0x1f) AM_READ_PORT("DSW") // select which uarts to use
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AM_RANGE(0xfc, 0xfc) AM_READ(portfc_r)
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ADDRESS_MAP_END
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/* Input ports */
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static INPUT_PORTS_START( hpz80unk )
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// this is a theoretical switch
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PORT_START("DSW")
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PORT_DIPNAME( 0x03, 0x00, "UART selection")
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PORT_DIPSETTING( 0x00, "In UART1, Out UART1")
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PORT_DIPSETTING( 0x01, "In UART1, Out UART2")
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PORT_DIPSETTING( 0x02, "In UART1, Out UART3")
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PORT_DIPSETTING( 0x03, "In UART2, Out UART1")
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INPUT_PORTS_END
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@ -110,14 +173,44 @@ void hpz80unk_state::machine_reset()
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{
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uint8_t* user1 = memregion("user1")->base();
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memcpy((uint8_t*)m_p_rom, user1, 0x4000);
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m_maincpu->set_pc(0xc000);
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// no idea if these are hard-coded, or programmable
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m_uart1->set_input_pin(AY31015_XR, 0);
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m_uart1->set_input_pin(AY31015_XR, 1);
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m_uart1->set_input_pin(AY31015_SWE, 0);
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m_uart1->set_input_pin(AY31015_NP, 1);
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m_uart1->set_input_pin(AY31015_TSB, 0);
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m_uart1->set_input_pin(AY31015_NB1, 1);
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m_uart1->set_input_pin(AY31015_NB2, 1);
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m_uart1->set_input_pin(AY31015_EPS, 1);
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m_uart1->set_input_pin(AY31015_CS, 1);
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m_uart1->set_input_pin(AY31015_CS, 0);
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m_uart2->set_input_pin(AY31015_XR, 0);
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m_uart2->set_input_pin(AY31015_XR, 1);
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m_uart2->set_input_pin(AY31015_SWE, 0);
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m_uart2->set_input_pin(AY31015_NP, 1);
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m_uart2->set_input_pin(AY31015_TSB, 0);
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m_uart2->set_input_pin(AY31015_NB1, 1);
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m_uart2->set_input_pin(AY31015_NB2, 1);
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m_uart2->set_input_pin(AY31015_EPS, 1);
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m_uart2->set_input_pin(AY31015_CS, 1);
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m_uart2->set_input_pin(AY31015_CS, 0);
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m_uart3->set_input_pin(AY31015_XR, 0);
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m_uart3->set_input_pin(AY31015_XR, 1);
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m_uart3->set_input_pin(AY31015_SWE, 0);
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m_uart3->set_input_pin(AY31015_NP, 1);
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m_uart3->set_input_pin(AY31015_TSB, 0);
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m_uart3->set_input_pin(AY31015_NB1, 1);
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m_uart3->set_input_pin(AY31015_NB2, 1);
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m_uart3->set_input_pin(AY31015_EPS, 1);
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m_uart3->set_input_pin(AY31015_CS, 1);
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m_uart3->set_input_pin(AY31015_CS, 0);
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// this should be rom/ram banking
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}
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void hpz80unk_state::kbd_put(u8 data)
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{
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m_term_data = data;
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}
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static MACHINE_CONFIG_START( hpz80unk )
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/* basic machine hardware */
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@ -126,8 +219,26 @@ static MACHINE_CONFIG_START( hpz80unk )
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MCFG_CPU_IO_MAP(hpz80unk_io)
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/* video hardware */
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MCFG_DEVICE_ADD(TERMINAL_TAG, GENERIC_TERMINAL, 0)
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MCFG_GENERIC_TERMINAL_KEYBOARD_CB(PUT(hpz80unk_state, kbd_put))
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MCFG_DEVICE_ADD("uart1", AY51013, 0) // COM2502
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MCFG_AY51013_TX_CLOCK(153600)
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MCFG_AY51013_RX_CLOCK(153600)
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MCFG_AY51013_READ_SI_CB(DEVREADLINE("rs232a", rs232_port_device, rxd_r))
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MCFG_AY51013_WRITE_SO_CB(DEVWRITELINE("rs232a", rs232_port_device, write_txd))
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MCFG_RS232_PORT_ADD("rs232a", default_rs232_devices, "terminal")
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MCFG_DEVICE_ADD("uart2", AY51013, 0) // COM2502
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MCFG_AY51013_TX_CLOCK(153600)
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MCFG_AY51013_RX_CLOCK(153600)
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MCFG_AY51013_READ_SI_CB(DEVREADLINE("rs232b", rs232_port_device, rxd_r))
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MCFG_AY51013_WRITE_SO_CB(DEVWRITELINE("rs232b", rs232_port_device, write_txd))
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MCFG_RS232_PORT_ADD("rs232b", default_rs232_devices, nullptr)
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MCFG_DEVICE_ADD("uart3", AY51013, 0) // COM2502
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MCFG_AY51013_TX_CLOCK(153600)
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MCFG_AY51013_RX_CLOCK(153600)
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MCFG_AY51013_READ_SI_CB(DEVREADLINE("rs232c", rs232_port_device, rxd_r))
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MCFG_AY51013_WRITE_SO_CB(DEVWRITELINE("rs232c", rs232_port_device, write_txd))
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MCFG_RS232_PORT_ADD("rs232c", default_rs232_devices, nullptr)
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MACHINE_CONFIG_END
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/* ROM definition */
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