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https://github.com/holub/mame
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Merge pull request #1761 from mamehaze/mk6
begin SH4 MMU improvements (with a view to seeing what mk6 needs)
This commit is contained in:
MetalliC
GitHub
commit
2a590ad3c9
@ -651,6 +651,19 @@ Published by Others (T-yyy*** serial codes, for yyy depending on the publisher)
|
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</part>
|
||||
</software>
|
||||
|
||||
<software name="cookpico">
|
||||
<description>Cooking Pico (Jpn)</description>
|
||||
<year>1999</year>
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||||
<publisher>Sega Toys</publisher>
|
||||
<part name="cart" interface="pico_cart">
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||||
<feature name="pcb" value="171-7967" />
|
||||
<feature name="ic1" value="9K0-0001A-RV" />
|
||||
<dataarea name="rom" size="2097152">
|
||||
<rom name="9k0-0001a-rv.ic1" size="2097152" crc="b94f7d54" sha1="dabeb440adbb7477cc880c51fb0cfc1e5f99d23b" offset="000000" loadflag="load16_word_swap" />
|
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</dataarea>
|
||||
</part>
|
||||
</software>
|
||||
|
||||
<software name="crayola">
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<description>Crayola - Create a World (USA)</description>
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<year>19??</year>
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||||
|
||||
@ -17,6 +17,19 @@
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</part>
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</software>
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||||
|
||||
<software name="doraedbl">
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<description>Doraemon Nobita no Dou Butsu Land</description>
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<year>1996</year>
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<publisher>Sega</publisher>
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<part name="cart" interface="sawatte_cart">
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<feature name="pcb" value="171-7323A" />
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<feature name="ic1" value="MPR-19040" />
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||||
<dataarea name="rom" size="524288">
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||||
<rom name="mpr-19040.ic1" size="524288" crc="0c9bae2f" sha1="bc5030fab99e8f4b1bcc8ed77c1cc07d8407df93" offset="0" />
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</dataarea>
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||||
</part>
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||||
</software>
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<software name="mickkuda">
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<description>Mickey no Kudamonoya-san</description>
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<year>1996</year>
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@ -77,7 +90,20 @@
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</part>
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</software>
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<software name="micknatk">
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<software name="soreike">
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<description>Soreike! Anpanman Onamae Na~ni</description>
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<year>1996</year>
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<publisher>Sega</publisher>
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<part name="cart" interface="sawatte_cart">
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<feature name="pcb" value="171-7323A" />
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<feature name="ic1" value="MPR-19041" />
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<dataarea name="rom" size="524288">
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<rom name="mpr-19041.ic1" size="524288" crc="ec924165" sha1="b25a5637c8cc1f2f6224595853d540195be86ec9" offset="0" />
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</dataarea>
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</part>
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</software>
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<software name="micknatk">
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<description>Tokyo Disneyland - Mickey no Nakayoshi Tankentai</description>
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<year>1998</year>
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<publisher>Sega?</publisher>
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@ -122,4 +148,17 @@
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</part>
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</software>
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<software name="uht">
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<description>Ultra Hero Touch</description>
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<year>1997</year>
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<publisher>Bandai</publisher>
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<part name="cart" interface="sawatte_cart">
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<feature name="pcb" value="171-7323A" />
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<feature name="ic1" value="MPR-19828-T" />
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<dataarea name="rom" size="524288">
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<rom name="mpr-19828-t.ic1" size="524288" crc="57988dc7" sha1="438a35b2a46ec82b5e31478d9e244928f98891ab" offset="0" />
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</dataarea>
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</part>
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</software>
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</softwarelist>
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@ -75,7 +75,11 @@ static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_base_device )
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AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x01FFF000)
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AM_RANGE(0x1E000000, 0x1E000FFF) AM_RAM AM_MIRROR(0x01FFF000)
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AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) // todo: store queues should be write only on DC's SH4, executing PREFM shouldn't cause an actual memory read access!
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AM_RANGE(0xF6000000, 0xF7FFFFFF) AM_READWRITE(sh4_tlb_r,sh4_tlb_w)
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AM_RANGE(0xF6000000, 0xF6FFFFFF) AM_READWRITE(sh4_utlb_address_array_r,sh4_utlb_address_array_w)
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AM_RANGE(0xF7000000, 0xF77FFFFF) AM_READWRITE(sh4_utlb_data_array1_r,sh4_utlb_data_array1_w)
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AM_RANGE(0xF7800000, 0xF7FFFFFF) AM_READWRITE(sh4_utlb_data_array2_r,sh4_utlb_data_array2_w)
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AM_RANGE(0xFE000000, 0xFFFFFFFF) AM_READWRITE32(sh4_internal_r, sh4_internal_w, 0xffffffffffffffffU)
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ADDRESS_MAP_END
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@ -180,6 +184,37 @@ void sh34_base_device::TODO(const uint16_t opcode)
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{
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}
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void sh34_base_device::LDTLB(const uint16_t opcode)
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{
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logerror("unhandled LDTLB for this CPU type\n");
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}
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void sh4_base_device::LDTLB(const uint16_t opcode)
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{
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int replace = (m_m[MMUCR] & 0x0000fc00) >> 10;
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logerror("using LDTLB to replace UTLB entry %02x\n", replace);
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// these come from PTEH
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m_utlb[replace].VPN = (m_m[PTEH] & 0xfffffc00) >> 10;
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// m_utlb[replace].D = (m_m[PTEH] & 0x00000200) >> 9; // from PTEL
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// m_utlb[replace].V = (m_m[PTEH] & 0x00000100) >> 8; // from PTEL
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m_utlb[replace].ASID = (m_m[PTEH] & 0x000000ff) >> 0;
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// these come from PTEL
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m_utlb[replace].PPN = (m_m[PTEL] & 0x1ffffc00) >> 10;
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m_utlb[replace].V = (m_m[PTEL] & 0x00000100) >> 8;
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m_utlb[replace].PSZ = (m_m[PTEL] & 0x00000080) >> 6;
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m_utlb[replace].PSZ |=(m_m[PTEL] & 0x00000010) >> 4;
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m_utlb[replace].PPR= (m_m[PTEL] & 0x00000060) >> 5;
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m_utlb[replace].C = (m_m[PTEL] & 0x00000008) >> 3;
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m_utlb[replace].D = (m_m[PTEL] & 0x00000004) >> 2;
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m_utlb[replace].SH = (m_m[PTEL] & 0x00000002) >> 1;
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m_utlb[replace].WT = (m_m[PTEL] & 0x00000001) >> 0;
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// these come from PTEA
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m_utlb[replace].TC = (m_m[PTEA] & 0x00000008) >> 3;
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m_utlb[replace].SA = (m_m[PTEA] & 0x00000007) >> 0;
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}
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#if 0
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int sign_of(int n)
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{
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@ -3331,7 +3366,7 @@ inline void sh34_base_device::execute_one_0000(const uint16_t opcode)
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case 0x08: CLRT(opcode); break;
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case 0x18: SETT(opcode); break;
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case 0x28: CLRMAC(opcode); break;
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case 0x38: TODO(opcode); break;
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case 0x38: LDTLB(opcode); break;
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case 0x48: CLRS(opcode); break;
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case 0x58: SETS(opcode); break;
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case 0x68: NOP(opcode); break;
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@ -3339,7 +3374,7 @@ inline void sh34_base_device::execute_one_0000(const uint16_t opcode)
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case 0x88: CLRT(opcode); break;
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case 0x98: SETT(opcode); break;
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case 0xa8: CLRMAC(opcode); break;
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case 0xb8: TODO(opcode); break;
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case 0xb8: LDTLB(opcode); break;
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case 0xc8: CLRS(opcode); break;
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case 0xd8: SETS(opcode); break;
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case 0xe8: NOP(opcode); break;
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@ -4028,6 +4063,47 @@ void sh4be_device::execute_run()
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} while( m_sh4_icount > 0 );
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}
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void sh4_base_device::device_start()
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{
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sh34_base_device::device_start();
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int i;
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for (i=0;i<64;i++)
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{
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m_utlb[i].ASID = 0;
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m_utlb[i].VPN = 0;
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m_utlb[i].V = 0;
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m_utlb[i].PPN = 0;
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m_utlb[i].PSZ = 0;
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m_utlb[i].SH = 0;
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m_utlb[i].C = 0;
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m_utlb[i].PPR = 0;
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m_utlb[i].D = 0;
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m_utlb[i].WT = 0;
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m_utlb[i].SA = 0;
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m_utlb[i].TC = 0;
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}
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for (i=0;i<64;i++)
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{
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save_item(NAME(m_utlb[i].ASID), i);
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save_item(NAME(m_utlb[i].VPN), i);
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save_item(NAME(m_utlb[i].V), i);
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save_item(NAME(m_utlb[i].PPN), i);
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save_item(NAME(m_utlb[i].PSZ), i);
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save_item(NAME(m_utlb[i].SH), i);
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save_item(NAME(m_utlb[i].C), i);
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save_item(NAME(m_utlb[i].PPR), i);
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save_item(NAME(m_utlb[i].D), i);
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save_item(NAME(m_utlb[i].WT), i);
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save_item(NAME(m_utlb[i].SA), i);
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save_item(NAME(m_utlb[i].TC), i);
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}
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}
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void sh34_base_device::device_start()
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{
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for (int i=0; i<3; i++)
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@ -4134,8 +4210,6 @@ void sh34_base_device::device_start()
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save_item(NAME( m_ioport16_direction));
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save_item(NAME(m_ioport4_pullup));
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save_item(NAME(m_ioport4_direction));
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save_item(NAME(m_sh4_tlb_address));
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save_item(NAME(m_sh4_tlb_data));
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save_item(NAME(m_sh4_mmu_enabled));
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save_item(NAME(m_sh3internal_upper));
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save_item(NAME(m_sh3internal_lower));
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@ -136,6 +136,26 @@ struct sh4_ddt_dma
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int mode;
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};
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// ASID [7:0] | VPN [31:10] | V | | PPN [28:10] | SZ[1:0] | SH | C | PR[1:0] | D | WT | SA[2:0] | TC
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struct sh4_utlb
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{
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uint8_t ASID;
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uint32_t VPN;
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uint8_t V;
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uint32_t PPN;
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uint8_t PSZ;
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uint8_t SH;
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uint8_t C;
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uint8_t PPR;
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uint8_t D;
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uint8_t WT;
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uint8_t SA;
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uint8_t TC;
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};
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typedef void (*sh4_ftcsr_callback)(uint32_t);
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@ -358,8 +378,6 @@ protected:
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void (*m_ftcsr_read_callback)(uint32_t data);
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/* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */
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uint32_t m_sh4_tlb_address[64];
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uint32_t m_sh4_tlb_data[64];
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uint8_t m_sh4_mmu_enabled;
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int m_cpu_type;
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@ -451,6 +469,7 @@ protected:
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void LDSMMACH(const uint16_t opcode);
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void LDSMMACL(const uint16_t opcode);
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void LDSMPR(const uint16_t opcode);
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virtual void LDTLB(const uint16_t opcode);
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void MAC_L(const uint16_t opcode);
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void MAC_W(const uint16_t opcode);
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void MOV(const uint16_t opcode);
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@ -627,7 +646,7 @@ protected:
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void increment_rtc_time(int mode);
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void sh4_dmac_nmi();
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void sh4_handler_ipra_w(uint32_t data, uint32_t mem_mask);
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uint32_t sh4_getsqremap(uint32_t address);
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virtual uint32_t sh4_getsqremap(uint32_t address);
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void sh4_parse_configuration();
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void sh4_timer_recompute(int which);
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uint32_t sh4_handle_tcnt0_addr_r(uint32_t mem_mask);
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@ -736,10 +755,20 @@ public:
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DECLARE_WRITE32_MEMBER( sh4_internal_w );
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DECLARE_READ32_MEMBER( sh4_internal_r );
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DECLARE_READ64_MEMBER( sh4_tlb_r );
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DECLARE_WRITE64_MEMBER( sh4_tlb_w );
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DECLARE_READ64_MEMBER( sh4_utlb_address_array_r );
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DECLARE_WRITE64_MEMBER( sh4_utlb_address_array_w );
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DECLARE_READ64_MEMBER( sh4_utlb_data_array1_r );
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DECLARE_WRITE64_MEMBER( sh4_utlb_data_array1_w );
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DECLARE_READ64_MEMBER( sh4_utlb_data_array2_r );
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DECLARE_WRITE64_MEMBER( sh4_utlb_data_array2_w );
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virtual void LDTLB(const uint16_t opcode) override;
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virtual uint32_t sh4_getsqremap(uint32_t address) override;
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sh4_utlb m_utlb[64];
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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};
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@ -676,9 +676,57 @@ WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
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// printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask);
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switch( offset )
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switch( offset )
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{
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case PTEH: // for use with LDTLB opcode
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m_m[PTEH] &= 0xffffffff;
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/*
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NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
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N = VPM = Virtual Page Number
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A = ASID = Address Space Identifier
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same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
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*/
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break;
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case PTEL:
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m_m[PTEL] &= 0xffffffff;
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/*
|
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---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
|
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|
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same format as data array 1 of the utlb
|
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*/
|
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break;
|
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|
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case PTEA:
|
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m_m[PTEA] &= 0xffffffff;
|
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/*
|
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---- ---- ---- ---- ---- ---- ---- TSSS
|
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|
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same format as data array 2 of the utlb
|
||||
*/
|
||||
break;
|
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|
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case MMUCR: // MMU Control
|
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logerror("MMUCR %08x\n", data);
|
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m_m[MMUCR] &= 0xffffffff;
|
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/*
|
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LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
|
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|
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L = LRUI = Least recently used ITLB
|
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B = URB = UTLB replace boundary
|
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C = URC = UTLB replace counter
|
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Q = SQMD = Store Queue Mode Bit
|
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V = SV = Single Virtual Mode Bit
|
||||
T = TI = TLB invaldiate
|
||||
A = AT = Address translation bit (enable)
|
||||
*/
|
||||
|
||||
|
||||
|
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if (data & MMUCR_AT)
|
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{
|
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printf("SH4 MMU Enabled\n");
|
||||
@ -686,16 +734,7 @@ WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
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printf("The MMU emulation is a hack specific to that system\n");
|
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m_sh4_mmu_enabled = 1;
|
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|
||||
// should be a different bit!
|
||||
{
|
||||
int i;
|
||||
for (i=0;i<64;i++)
|
||||
{
|
||||
m_sh4_tlb_address[i] = 0;
|
||||
m_sh4_tlb_data[i] = 0;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1185,6 +1224,11 @@ void sh34_base_device::sh4_parse_configuration()
|
||||
}
|
||||
|
||||
uint32_t sh34_base_device::sh4_getsqremap(uint32_t address)
|
||||
{
|
||||
return address;
|
||||
}
|
||||
|
||||
uint32_t sh4_base_device::sh4_getsqremap(uint32_t address)
|
||||
{
|
||||
if (!m_sh4_mmu_enabled)
|
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return address;
|
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@ -1195,9 +1239,9 @@ uint32_t sh34_base_device::sh4_getsqremap(uint32_t address)
|
||||
|
||||
for (i=0;i<64;i++)
|
||||
{
|
||||
uint32_t topcmp = m_sh4_tlb_address[i]&0xfff00000;
|
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uint32_t topcmp = (m_utlb[i].VPN<<10)&0xfff00000;
|
||||
if (topcmp==topaddr)
|
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return (address&0x000fffff) | ((m_sh4_tlb_data[i])&0xfff00000);
|
||||
return (address&0x000fffff) | ((m_utlb[i].PPN<<10)&0xfff00000);
|
||||
}
|
||||
|
||||
}
|
||||
@ -1205,34 +1249,147 @@ uint32_t sh34_base_device::sh4_getsqremap(uint32_t address)
|
||||
return address;
|
||||
}
|
||||
|
||||
READ64_MEMBER( sh4_base_device::sh4_tlb_r )
|
||||
{
|
||||
int offs = offset*8;
|
||||
|
||||
if (offs >= 0x01000000)
|
||||
WRITE64_MEMBER( sh4_base_device::sh4_utlb_address_array_w )
|
||||
{
|
||||
/* uses bits 13:8 of address to select which UTLB entry we're addressing
|
||||
bit 7 of the address enables 'associative' mode, causing a search
|
||||
operation rather than a direct write.
|
||||
|
||||
NNNN NNNN NNNN NNNN NNNN NNDV AAAA AAAA
|
||||
|
||||
N = VPM = Virtual Page Number
|
||||
D = Dirty Bit
|
||||
V = Validity Bit
|
||||
A = ASID = Address Space Identifier
|
||||
*/
|
||||
|
||||
logerror("sh4_utlb_address_array_w %08x %08x\n", offset, data);
|
||||
int offs = offset << 3;
|
||||
|
||||
uint8_t associative = (offs >> 7) & 1;
|
||||
|
||||
if (!associative)
|
||||
{
|
||||
uint8_t i = (offs>>8)&63;
|
||||
return m_sh4_tlb_data[i];
|
||||
// non-associative mode
|
||||
uint8_t i = (offs >> 8) & 63;
|
||||
|
||||
m_utlb[i].VPN = (data & 0xfffffc00) >> 10;
|
||||
m_utlb[i].D = (data & 0x00000200) >> 9;
|
||||
m_utlb[i].V = (data & 0x00000100) >> 8;
|
||||
m_utlb[i].ASID = (data & 0x000000ff) >> 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t i = (offs>>8)&63;
|
||||
return m_sh4_tlb_address[i];
|
||||
// associative mode
|
||||
fatalerror("SH4MMU: associative mode writes unsupported\n");
|
||||
}
|
||||
}
|
||||
|
||||
WRITE64_MEMBER( sh4_base_device::sh4_tlb_w )
|
||||
READ64_MEMBER( sh4_base_device::sh4_utlb_address_array_r )
|
||||
{
|
||||
// associative bit is ignored for reads
|
||||
int offs = offset*8;
|
||||
|
||||
if (offs >= 0x01000000)
|
||||
{
|
||||
uint8_t i = (offs>>8)&63;
|
||||
m_sh4_tlb_data[i] = data&0xffffffff;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t i = (offs>>8)&63;
|
||||
m_sh4_tlb_address[i] = data&0xffffffff;
|
||||
}
|
||||
uint32_t ret = 0;
|
||||
|
||||
uint8_t i = (offs >> 8) & 63;
|
||||
|
||||
ret |= m_utlb[i].VPN << 10;
|
||||
ret |= m_utlb[i].D << 9;
|
||||
ret |= m_utlb[i].V << 8;
|
||||
ret |= m_utlb[i].ASID << 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
WRITE64_MEMBER( sh4_base_device::sh4_utlb_data_array1_w )
|
||||
{
|
||||
/* uses bits 13:8 of address to select which UTLB entry we're addressing
|
||||
|
||||
---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
|
||||
|
||||
P = PPN = Physical page number
|
||||
V = Validity bit
|
||||
z = SZ = Page Size (2 bits, split)
|
||||
D = Dirty Bit
|
||||
R = PR = Protection Key Data
|
||||
C = Cacheable bit
|
||||
H = Share status
|
||||
W = Write through
|
||||
- = unused (should be 0)
|
||||
*/
|
||||
logerror("sh4_utlb_data_array1_w %08x %08x\n", offset, data);
|
||||
int offs = offset*8;
|
||||
|
||||
uint8_t i = (offs>>8)&63;
|
||||
|
||||
m_utlb[i].PPN = (data & 0x1ffffc00) >> 10;
|
||||
m_utlb[i].V = (data & 0x00000100) >> 8;
|
||||
m_utlb[i].PSZ = (data & 0x00000080) >> 6;
|
||||
m_utlb[i].PSZ |=(data & 0x00000010) >> 4;
|
||||
m_utlb[i].PPR= (data & 0x00000060) >> 5;
|
||||
m_utlb[i].C = (data & 0x00000008) >> 3;
|
||||
m_utlb[i].D = (data & 0x00000004) >> 2;
|
||||
m_utlb[i].SH = (data & 0x00000002) >> 1;
|
||||
m_utlb[i].WT = (data & 0x00000001) >> 0;
|
||||
}
|
||||
|
||||
|
||||
READ64_MEMBER(sh4_base_device::sh4_utlb_data_array1_r)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
int offs = offset*8;
|
||||
|
||||
uint8_t i = (offs>>8)&63;
|
||||
|
||||
ret |= m_utlb[i].PPN << 10;
|
||||
ret |= m_utlb[i].V << 8;
|
||||
ret |= (m_utlb[i].PSZ & 2) << 6;
|
||||
ret |= (m_utlb[i].PSZ & 1) << 4;
|
||||
ret |= m_utlb[i].PPR << 5;
|
||||
ret |= m_utlb[i].C << 3;
|
||||
ret |= m_utlb[i].D << 2;
|
||||
ret |= m_utlb[i].SH << 1;
|
||||
ret |= m_utlb[i].WT << 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
WRITE64_MEMBER( sh4_base_device::sh4_utlb_data_array2_w )
|
||||
{
|
||||
/* uses bits 13:8 of address to select which UTLB entry we're addressing
|
||||
|
||||
---- ---- ---- ---- ---- ---- ---- TSSS
|
||||
|
||||
T = TC = Timing Control
|
||||
S = SA = Space attributes
|
||||
- = unused (should be 0)
|
||||
|
||||
*/
|
||||
|
||||
logerror("sh4_utlb_data_array2_w %08x %08x\n", offset, data);
|
||||
int offs = offset*8;
|
||||
|
||||
uint8_t i = (offs>>8)&63;
|
||||
|
||||
m_utlb[i].TC = (data & 0x00000008) >> 3;
|
||||
m_utlb[i].SA = (data & 0x00000007) >> 0;
|
||||
}
|
||||
|
||||
|
||||
READ64_MEMBER(sh4_base_device::sh4_utlb_data_array2_r)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
int offs = offset*8;
|
||||
|
||||
uint8_t i = (offs>>8)&63;
|
||||
|
||||
ret |= m_utlb[i].TC << 3;
|
||||
ret |= m_utlb[i].SA << 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -5,7 +5,7 @@
|
||||
|
||||
a sound-only Pico type system (one of the boards even says S-PICO)
|
||||
|
||||
CPU is unknown (I can't see one?!) cartridge dumps should be good, but not confirmed, might be data only for an MCU?
|
||||
CPU is unknown (I can't see one?! MCU with internal ROM?) cartridge dumps have been tested as working using a flash cart.
|
||||
driver does nothing except allow the softlist to be connected to the -romident commands etc.
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user