YM2612/3834 updates [Eke-Eke, Nemesis]
- Split YM2612/3834 to a separate file to avoid disturbing other OPN chips - SSG-EG, envelope, LFO, and CSM behavior all improved to better match tested behavior on real YM2612 chips
This commit is contained in:
R. Belmont
parent
fd4684ace5
commit
2a76fb52c6
1
.gitattributes
vendored
1
.gitattributes
vendored
@ -819,6 +819,7 @@ src/emu/sound/flt_vol.c svneol=native#text/plain
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src/emu/sound/flt_vol.h svneol=native#text/plain
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src/emu/sound/fm.c svneol=native#text/plain
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src/emu/sound/fm.h svneol=native#text/plain
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src/emu/sound/fm2612.c svneol=native#text/plain
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src/emu/sound/fmopl.c svneol=native#text/plain
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src/emu/sound/fmopl.h svneol=native#text/plain
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src/emu/sound/gaelco.c svneol=native#text/plain
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@ -132,7 +132,7 @@
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#endif
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/* shared function building option */
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#define BUILD_OPN (BUILD_YM2203||BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B||BUILD_YM2612||BUILD_YM3438)
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#define BUILD_OPN (BUILD_YM2203||BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
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#define BUILD_OPN_PRESCALER (BUILD_YM2203||BUILD_YM2608)
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@ -148,7 +148,6 @@
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#define TYPE_YM2203 (TYPE_SSG)
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#define TYPE_YM2608 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM)
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#define TYPE_YM2610 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM |TYPE_2610)
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#define TYPE_YM2612 (TYPE_DAC |TYPE_LFOPAN |TYPE_6CH)
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@ -292,47 +291,6 @@ O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
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};
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static const UINT8 eg_rate_select2612[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) from tests on YM2612 */
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/* 32 infinite time rates */
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O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
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O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
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O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
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O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
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/* rates 00-11 */
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O( 18),O( 18),O( 0),O( 0),
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O( 0),O( 0),O( 2),O( 2), // Nemesis's tests
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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O( 0),O( 1),O( 2),O( 3),
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/* rate 12 */
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O( 4),O( 5),O( 6),O( 7),
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/* rate 13 */
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O( 8),O( 9),O(10),O(11),
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/* rate 14 */
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O(12),O(13),O(14),O(15),
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/* rate 15 */
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O(16),O(16),O(16),O(16),
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/* 32 dummy rates (same as 15 3) */
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O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
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O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
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O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
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O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
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};
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#undef O
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/*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
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@ -922,26 +880,9 @@ INLINE void FM_KEYON(UINT8 type, FM_CH *CH , int s )
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SLOT->key = 1;
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SLOT->phase = 0; /* restart Phase Generator */
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SLOT->ssgn = (SLOT->ssg & 0x04) >> 1;
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if ((type == TYPE_YM2612) || (type == TYPE_YM2608))
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{
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if( (SLOT->ar + SLOT->ksr) < 32+62 )
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{
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SLOT->state = EG_ATT; /* phase -> Attack */
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}
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else
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{
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/* directly switch to Decay */
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SLOT->volume = MIN_ATT_INDEX;
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SLOT->state = EG_DEC;
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}
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}
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else
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{
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SLOT->state = EG_ATT;
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}
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}
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}
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INLINE void FM_KEYOFF(FM_CH *CH , int s )
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{
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@ -1072,16 +1013,8 @@ INLINE void set_ar_ksr(UINT8 type, FM_CH *CH,FM_SLOT *SLOT,int v)
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if ((SLOT->ar + SLOT->ksr) < 32+62)
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{
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SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
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if ((type == TYPE_YM2612) || (type == TYPE_YM2608))
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{
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SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
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SLOT->eg_sel_ar = eg_rate_select2612[SLOT->ar + SLOT->ksr ];
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}
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else
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{
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SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
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}
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}
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else
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{
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SLOT->eg_sh_ar = 0;
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@ -1095,32 +1028,17 @@ INLINE void set_dr(UINT8 type, FM_SLOT *SLOT,int v)
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SLOT->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
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SLOT->eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
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if ((type == TYPE_YM2612) || (type == TYPE_YM2608))
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{
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SLOT->eg_sel_d1r= eg_rate_select2612[SLOT->d1r + SLOT->ksr];
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}
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else
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{
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SLOT->eg_sel_d1r= eg_rate_select[SLOT->d1r + SLOT->ksr];
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}
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}
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/* set sustain rate */
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INLINE void set_sr(UINT8 type, FM_SLOT *SLOT,int v)
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{
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SLOT->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
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SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
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if ((type == TYPE_YM2612) || (type == TYPE_YM2608))
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{
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SLOT->eg_sel_d2r= eg_rate_select2612[SLOT->d2r + SLOT->ksr];
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}
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else
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{
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SLOT->eg_sel_d2r= eg_rate_select[SLOT->d2r + SLOT->ksr];
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}
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}
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/* set release rate */
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INLINE void set_sl_rr(UINT8 type, FM_SLOT *SLOT,int v)
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@ -1130,15 +1048,8 @@ INLINE void set_sl_rr(UINT8 type, FM_SLOT *SLOT,int v)
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SLOT->rr = 34 + ((v&0x0f)<<2);
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SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
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if ((type == TYPE_YM2612) || (type == TYPE_YM2608))
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{
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SLOT->eg_sel_rr = eg_rate_select2612[SLOT->rr + SLOT->ksr];
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}
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else
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{
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SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
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}
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}
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@ -1238,28 +1149,6 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
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break;
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case EG_DEC: /* decay phase */
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if ((OPN->type == TYPE_YM2612) || (OPN->type == TYPE_YM2608))
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{
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if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d1r)-1) ) )
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{
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if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
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{
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SLOT->volume += 6 * eg_inc[SLOT->eg_sel_d1r + ((OPN->eg_cnt>>SLOT->eg_sh_d1r)&7)];
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}
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else
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{
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SLOT->volume += eg_inc[SLOT->eg_sel_d1r + ((OPN->eg_cnt>>SLOT->eg_sh_d1r)&7)];
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}
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}
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/* check transition even if no volume update: this fixes the case when SL = MIN_ATT_INDEX */
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if ( SLOT->volume >= (INT32)(SLOT->sl) )
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{
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SLOT->volume = (INT32)(SLOT->sl);
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SLOT->state = EG_SUS;
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}
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}
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else
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{
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if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
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{
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@ -1290,21 +1179,11 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
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if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d2r)-1) ) )
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{
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if ((OPN->type == TYPE_YM2612) || (OPN->type == TYPE_YM2608))
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{
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SLOT->volume += 6 * eg_inc[SLOT->eg_sel_d2r + ((OPN->eg_cnt>>SLOT->eg_sh_d2r)&7)];
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}
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else
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{
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SLOT->volume += 4 * eg_inc[SLOT->eg_sel_d2r + ((OPN->eg_cnt>>SLOT->eg_sh_d2r)&7)];
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}
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if ( SLOT->volume >= ENV_QUIET )
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{
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if ((OPN->type != TYPE_YM2612) && (OPN->type != TYPE_YM2608))
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{
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SLOT->volume = MAX_ATT_INDEX;
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}
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if (SLOT->ssg&0x01) /* bit 0 = hold */
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{
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@ -1323,20 +1202,6 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
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/* restart of the Phase Generator should be here */
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SLOT->phase = 0;
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if ((OPN->type == TYPE_YM2612) || (OPN->type == TYPE_YM2608))
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{
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if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
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{
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SLOT->state = EG_ATT; /* phase -> Attack */
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}
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else
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{
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/* Attack Rate is maximal: directly switch to Decay (or Substain) */
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SLOT->volume = MIN_ATT_INDEX;
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SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
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}
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}
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else
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{
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/* phase -> Attack */
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SLOT->volume = 511;
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@ -1368,14 +1233,7 @@ static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
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if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_rr)-1) ) )
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{
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/* SSG-EG affects Release phase also (Nemesis) */
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if ((SLOT->ssg&0x08) && ((OPN->type = TYPE_YM2612) || (OPN->type = TYPE_YM2608)))
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{
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SLOT->volume += 6 * eg_inc[SLOT->eg_sel_rr + ((OPN->eg_cnt>>SLOT->eg_sh_rr)&7)];
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}
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else
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{
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SLOT->volume += eg_inc[SLOT->eg_sel_rr + ((OPN->eg_cnt>>SLOT->eg_sh_rr)&7)];
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}
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if ( SLOT->volume >= MAX_ATT_INDEX )
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{
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@ -1591,15 +1449,8 @@ INLINE void refresh_fc_eg_slot(FM_OPN *OPN, FM_SLOT *SLOT , int fc , int kc )
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if ((SLOT->ar + SLOT->ksr) < 32+62)
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{
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SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
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if ((OPN->type == TYPE_YM2612) || (OPN->type == TYPE_YM2608))
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{
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SLOT->eg_sel_ar = eg_rate_select2612[SLOT->ar + SLOT->ksr ];
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}
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else
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{
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SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
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}
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}
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else
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{
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SLOT->eg_sh_ar = 0;
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@ -1610,20 +1461,11 @@ INLINE void refresh_fc_eg_slot(FM_OPN *OPN, FM_SLOT *SLOT , int fc , int kc )
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SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
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SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
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if ((OPN->type == TYPE_YM2612) || (OPN->type == TYPE_YM2608))
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{
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SLOT->eg_sel_d1r= eg_rate_select2612[SLOT->d1r + SLOT->ksr];
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SLOT->eg_sel_d2r= eg_rate_select2612[SLOT->d2r + SLOT->ksr];
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SLOT->eg_sel_rr = eg_rate_select2612[SLOT->rr + SLOT->ksr];
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}
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else
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{
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SLOT->eg_sel_d1r= eg_rate_select[SLOT->d1r + SLOT->ksr];
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SLOT->eg_sel_d2r= eg_rate_select[SLOT->d2r + SLOT->ksr];
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SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
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}
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}
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}
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/* update phase increment counters */
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/* Changed from INLINE to static to work around gcc 4.2.1 codegen bug */
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@ -4601,375 +4443,3 @@ int ym2610_timer_over(void *chip,int c)
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}
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#endif /* (BUILD_YM2610||BUILD_YM2610B) */
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#if (BUILD_YM2612||BUILD_YM3438)
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/*******************************************************************************/
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/* YM2612 local section */
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/*******************************************************************************/
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/* here's the virtual YM2612 */
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typedef struct
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{
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UINT8 REGS[512]; /* registers */
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FM_OPN OPN; /* OPN state */
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FM_CH CH[6]; /* channel state */
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UINT8 addr_A1; /* address line A1 */
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/* dac output (YM2612) */
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int dacen;
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INT32 dacout;
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} YM2612;
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static int dacen;
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/* Generate samples for one of the YM2612s */
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void ym2612_update_one(void *chip, FMSAMPLE **buffer, int length)
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{
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YM2612 *F2612 = (YM2612 *)chip;
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FM_OPN *OPN = &F2612->OPN;
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int i;
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FMSAMPLE *bufL,*bufR;
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INT32 dacout = F2612->dacout;
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FM_CH *cch[6];
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/* set bufer */
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bufL = buffer[0];
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bufR = buffer[1];
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cch[0] = &F2612->CH[0];
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cch[1] = &F2612->CH[1];
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cch[2] = &F2612->CH[2];
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cch[3] = &F2612->CH[3];
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cch[4] = &F2612->CH[4];
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cch[5] = &F2612->CH[5];
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/* DAC mode */
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dacen = F2612->dacen;
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/* refresh PG and EG */
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refresh_fc_eg_chan( OPN, cch[0] );
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refresh_fc_eg_chan( OPN, cch[1] );
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if( (OPN->ST.mode & 0xc0) )
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{
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/* 3SLOT MODE */
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if( cch[2]->SLOT[SLOT1].Incr==-1)
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{
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refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] );
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refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] );
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refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] );
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refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT4] , cch[2]->fc , cch[2]->kcode );
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}
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}else refresh_fc_eg_chan( OPN, cch[2] );
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refresh_fc_eg_chan( OPN, cch[3] );
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refresh_fc_eg_chan( OPN, cch[4] );
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refresh_fc_eg_chan( OPN, cch[5] );
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/* buffering */
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for(i=0; i < length ; i++)
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{
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advance_lfo(OPN);
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/* clear outputs */
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out_fm[0] = 0;
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out_fm[1] = 0;
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out_fm[2] = 0;
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out_fm[3] = 0;
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out_fm[4] = 0;
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out_fm[5] = 0;
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/* calculate FM */
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chan_calc(OPN, cch[0], 0 );
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chan_calc(OPN, cch[1], 1 );
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chan_calc(OPN, cch[2], 2 );
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chan_calc(OPN, cch[3], 3 );
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chan_calc(OPN, cch[4], 4 );
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if( dacen )
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*cch[5]->connect4 += dacout;
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else
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chan_calc(OPN, cch[5], 5 );
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/* advance envelope generator */
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OPN->eg_timer += OPN->eg_timer_add;
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while (OPN->eg_timer >= OPN->eg_timer_overflow)
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{
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OPN->eg_timer -= OPN->eg_timer_overflow;
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OPN->eg_cnt++;
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advance_eg_channel(OPN, &cch[0]->SLOT[SLOT1]);
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advance_eg_channel(OPN, &cch[1]->SLOT[SLOT1]);
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advance_eg_channel(OPN, &cch[2]->SLOT[SLOT1]);
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advance_eg_channel(OPN, &cch[3]->SLOT[SLOT1]);
|
||||
advance_eg_channel(OPN, &cch[4]->SLOT[SLOT1]);
|
||||
advance_eg_channel(OPN, &cch[5]->SLOT[SLOT1]);
|
||||
}
|
||||
|
||||
{
|
||||
int lt,rt;
|
||||
|
||||
lt = ((out_fm[0]>>0) & OPN->pan[0]);
|
||||
rt = ((out_fm[0]>>0) & OPN->pan[1]);
|
||||
lt += ((out_fm[1]>>0) & OPN->pan[2]);
|
||||
rt += ((out_fm[1]>>0) & OPN->pan[3]);
|
||||
lt += ((out_fm[2]>>0) & OPN->pan[4]);
|
||||
rt += ((out_fm[2]>>0) & OPN->pan[5]);
|
||||
lt += ((out_fm[3]>>0) & OPN->pan[6]);
|
||||
rt += ((out_fm[3]>>0) & OPN->pan[7]);
|
||||
lt += ((out_fm[4]>>0) & OPN->pan[8]);
|
||||
rt += ((out_fm[4]>>0) & OPN->pan[9]);
|
||||
lt += ((out_fm[5]>>0) & OPN->pan[10]);
|
||||
rt += ((out_fm[5]>>0) & OPN->pan[11]);
|
||||
|
||||
|
||||
lt >>= FINAL_SH;
|
||||
rt >>= FINAL_SH;
|
||||
|
||||
Limit( lt, MAXOUT, MINOUT );
|
||||
Limit( rt, MAXOUT, MINOUT );
|
||||
|
||||
#ifdef SAVE_SAMPLE
|
||||
SAVE_ALL_CHANNELS
|
||||
#endif
|
||||
|
||||
/* buffering */
|
||||
bufL[i] = lt;
|
||||
bufR[i] = rt;
|
||||
}
|
||||
|
||||
/* timer A control */
|
||||
INTERNAL_TIMER_A( &OPN->ST , cch[2] )
|
||||
}
|
||||
INTERNAL_TIMER_B(&OPN->ST,length)
|
||||
|
||||
}
|
||||
|
||||
#ifdef __STATE_H__
|
||||
void ym2612_postload(void *chip)
|
||||
{
|
||||
if (chip)
|
||||
{
|
||||
YM2612 *F2612 = (YM2612 *)chip;
|
||||
int r;
|
||||
|
||||
/* DAC data & port */
|
||||
F2612->dacout = ((int)F2612->REGS[0x2a] - 0x80) << 6; /* level unknown */
|
||||
F2612->dacen = F2612->REGS[0x2d] & 0x80;
|
||||
/* OPN registers */
|
||||
/* DT / MULTI , TL , KS / AR , AMON / DR , SR , SL / RR , SSG-EG */
|
||||
for(r=0x30;r<0x9e;r++)
|
||||
if((r&3) != 3)
|
||||
{
|
||||
OPNWriteReg(&F2612->OPN,r,F2612->REGS[r]);
|
||||
OPNWriteReg(&F2612->OPN,r|0x100,F2612->REGS[r|0x100]);
|
||||
}
|
||||
/* FB / CONNECT , L / R / AMS / PMS */
|
||||
for(r=0xb0;r<0xb6;r++)
|
||||
if((r&3) != 3)
|
||||
{
|
||||
OPNWriteReg(&F2612->OPN,r,F2612->REGS[r]);
|
||||
OPNWriteReg(&F2612->OPN,r|0x100,F2612->REGS[r|0x100]);
|
||||
}
|
||||
/* channels */
|
||||
/*FM_channel_postload(F2612->CH,6);*/
|
||||
}
|
||||
}
|
||||
|
||||
static void YM2612_save_state(YM2612 *F2612, const device_config *device)
|
||||
{
|
||||
state_save_register_device_item_array(device, 0, F2612->REGS);
|
||||
FMsave_state_st(device,&F2612->OPN.ST);
|
||||
FMsave_state_channel(device,F2612->CH,6);
|
||||
/* 3slots */
|
||||
state_save_register_device_item_array(device, 0, F2612->OPN.SL3.fc);
|
||||
state_save_register_device_item(device, 0, F2612->OPN.SL3.fn_h);
|
||||
state_save_register_device_item_array(device, 0, F2612->OPN.SL3.kcode);
|
||||
/* address register1 */
|
||||
state_save_register_device_item(device, 0, F2612->addr_A1);
|
||||
}
|
||||
#endif /* _STATE_H */
|
||||
|
||||
/* initialize YM2612 emulator(s) */
|
||||
void * ym2612_init(void *param, const device_config *device, int clock, int rate,
|
||||
FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler)
|
||||
{
|
||||
YM2612 *F2612;
|
||||
|
||||
/* allocate extend state space */
|
||||
if( (F2612 = (YM2612 *)malloc(sizeof(YM2612)))==NULL)
|
||||
return NULL;
|
||||
/* clear */
|
||||
memset(F2612,0,sizeof(YM2612));
|
||||
/* allocate total level table (128kb space) */
|
||||
if( !init_tables() )
|
||||
{
|
||||
free( F2612 );
|
||||
return NULL;
|
||||
}
|
||||
|
||||
F2612->OPN.ST.param = param;
|
||||
F2612->OPN.type = TYPE_YM2612;
|
||||
F2612->OPN.P_CH = F2612->CH;
|
||||
F2612->OPN.ST.device = device;
|
||||
F2612->OPN.ST.clock = clock;
|
||||
F2612->OPN.ST.rate = rate;
|
||||
/* F2612->OPN.ST.irq = 0; */
|
||||
/* F2612->OPN.ST.status = 0; */
|
||||
/* Extend handler */
|
||||
F2612->OPN.ST.timer_handler = timer_handler;
|
||||
F2612->OPN.ST.IRQ_Handler = IRQHandler;
|
||||
|
||||
#ifdef __STATE_H__
|
||||
YM2612_save_state(F2612, device);
|
||||
#endif
|
||||
return F2612;
|
||||
}
|
||||
|
||||
/* shut down emulator */
|
||||
void ym2612_shutdown(void *chip)
|
||||
{
|
||||
YM2612 *F2612 = (YM2612 *)chip;
|
||||
|
||||
FMCloseTable();
|
||||
free(F2612);
|
||||
}
|
||||
|
||||
/* reset one of chip */
|
||||
void ym2612_reset_chip(void *chip)
|
||||
{
|
||||
int i;
|
||||
YM2612 *F2612 = (YM2612 *)chip;
|
||||
FM_OPN *OPN = &F2612->OPN;
|
||||
|
||||
OPNSetPres( OPN, 6*24, 6*24, 0);
|
||||
/* status clear */
|
||||
FM_IRQMASK_SET(&OPN->ST,0x03);
|
||||
FM_BUSY_CLEAR(&OPN->ST);
|
||||
OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
|
||||
|
||||
OPN->eg_timer = 0;
|
||||
OPN->eg_cnt = 0;
|
||||
|
||||
FM_STATUS_RESET(&OPN->ST, 0xff);
|
||||
|
||||
reset_channels( &OPN->ST , &F2612->CH[0] , 6 );
|
||||
for(i = 0xb6 ; i >= 0xb4 ; i-- )
|
||||
{
|
||||
OPNWriteReg(OPN,i ,0xc0);
|
||||
OPNWriteReg(OPN,i|0x100,0xc0);
|
||||
}
|
||||
for(i = 0xb2 ; i >= 0x30 ; i-- )
|
||||
{
|
||||
OPNWriteReg(OPN,i ,0);
|
||||
OPNWriteReg(OPN,i|0x100,0);
|
||||
}
|
||||
for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(OPN,i,0);
|
||||
/* DAC mode clear */
|
||||
F2612->dacen = 0;
|
||||
}
|
||||
|
||||
/* YM2612 write */
|
||||
/* n = number */
|
||||
/* a = address */
|
||||
/* v = value */
|
||||
int ym2612_write(void *chip, int a, UINT8 v)
|
||||
{
|
||||
YM2612 *F2612 = (YM2612 *)chip;
|
||||
int addr;
|
||||
|
||||
v &= 0xff; /* adjust to 8 bit bus */
|
||||
|
||||
switch( a&3){
|
||||
case 0: /* address port 0 */
|
||||
F2612->OPN.ST.address = v;
|
||||
F2612->addr_A1 = 0;
|
||||
break;
|
||||
|
||||
case 1: /* data port 0 */
|
||||
if (F2612->addr_A1 != 0)
|
||||
break; /* verified on real YM2608 */
|
||||
|
||||
addr = F2612->OPN.ST.address;
|
||||
F2612->REGS[addr] = v;
|
||||
switch( addr & 0xf0 )
|
||||
{
|
||||
case 0x20: /* 0x20-0x2f Mode */
|
||||
switch( addr )
|
||||
{
|
||||
case 0x2a: /* DAC data (YM2612) */
|
||||
ym2612_update_req(F2612->OPN.ST.param);
|
||||
F2612->dacout = ((int)v - 0x80) << 6; /* level unknown */
|
||||
break;
|
||||
case 0x2b: /* DAC Sel (YM2612) */
|
||||
/* b7 = dac enable */
|
||||
F2612->dacen = v & 0x80;
|
||||
break;
|
||||
default: /* OPN section */
|
||||
ym2612_update_req(F2612->OPN.ST.param);
|
||||
/* write register */
|
||||
OPNWriteMode(&(F2612->OPN),addr,v);
|
||||
}
|
||||
break;
|
||||
default: /* 0x30-0xff OPN section */
|
||||
ym2612_update_req(F2612->OPN.ST.param);
|
||||
/* write register */
|
||||
OPNWriteReg(&(F2612->OPN),addr,v);
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* address port 1 */
|
||||
F2612->OPN.ST.address = v;
|
||||
F2612->addr_A1 = 1;
|
||||
break;
|
||||
|
||||
case 3: /* data port 1 */
|
||||
if (F2612->addr_A1 != 1)
|
||||
break; /* verified on real YM2608 */
|
||||
|
||||
addr = F2612->OPN.ST.address;
|
||||
F2612->REGS[addr | 0x100] = v;
|
||||
ym2612_update_req(F2612->OPN.ST.param);
|
||||
OPNWriteReg(&(F2612->OPN),addr | 0x100,v);
|
||||
break;
|
||||
}
|
||||
return F2612->OPN.ST.irq;
|
||||
}
|
||||
|
||||
UINT8 ym2612_read(void *chip,int a)
|
||||
{
|
||||
YM2612 *F2612 = (YM2612 *)chip;
|
||||
|
||||
switch( a&3){
|
||||
case 0: /* status 0 */
|
||||
return FM_STATUS_FLAG(&F2612->OPN.ST);
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
LOG(LOG_WAR,("YM2612 #%p:A=%d read unmapped area\n",F2612->OPN.ST.param,a));
|
||||
return FM_STATUS_FLAG(&F2612->OPN.ST);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ym2612_timer_over(void *chip,int c)
|
||||
{
|
||||
YM2612 *F2612 = (YM2612 *)chip;
|
||||
|
||||
if( c )
|
||||
{ /* Timer B */
|
||||
TimerBOver( &(F2612->OPN.ST) );
|
||||
}
|
||||
else
|
||||
{ /* Timer A */
|
||||
ym2612_update_req(F2612->OPN.ST.param);
|
||||
/* timer update */
|
||||
TimerAOver( &(F2612->OPN.ST) );
|
||||
/* CSM mode key,TL controll */
|
||||
if( F2612->OPN.ST.mode & 0x80 )
|
||||
{ /* CSM mode total level latch and auto key on */
|
||||
CSMKeyControll( F2612->OPN.type, &(F2612->CH[2]) );
|
||||
}
|
||||
}
|
||||
return F2612->OPN.ST.irq;
|
||||
}
|
||||
|
||||
#endif /* (BUILD_YM2612||BUILD_YM3238) */
|
||||
|
||||
2641
src/emu/sound/fm2612.c
Normal file
2641
src/emu/sound/fm2612.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -729,7 +729,7 @@ SOUNDOBJS += $(SOUNDOBJ)/2610intf.o $(SOUNDOBJ)/ay8910.o $(SOUNDOBJ)/fm.o $(SOUN
|
||||
endif
|
||||
|
||||
ifneq ($(filter YM2612 YM3438,$(SOUNDS)),)
|
||||
SOUNDOBJS += $(SOUNDOBJ)/2612intf.o $(SOUNDOBJ)/ay8910.o $(SOUNDOBJ)/fm.o
|
||||
SOUNDOBJS += $(SOUNDOBJ)/2612intf.o $(SOUNDOBJ)/ay8910.o $(SOUNDOBJ)/fm2612.o
|
||||
endif
|
||||
|
||||
ifneq ($(filter YM3812,$(SOUNDS)),)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user