Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-05-01 04:06:58 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

indy_indigo2.cpp: More modularization and architectural cleanup (nw)

Browse Source 
- hpc3: Add ten address spaces for the generic PIO channels, with configurable 8-bit or 16-bit access; add miscellaneous register; make DMA byte swap configurable
- hal2: Narrow all handlers and registers to 16 bits; simplify handlers
- ioc2: Simplify and narrow handlers to 8 bits; internalize a few things that HPC3 was using improperly
- Configure PIO channel 4 for Full House only

Note: HPC3 is now mostly but not entirely decoupled from HAL2 and IOC2. HAL2 is still accessed directly for DMA, and IOC2 is directly referenced by a few interrupt handlers which should be moved to that device once the "DMA done" interrupt logic is properly emulated.
This commit is contained in:
AJR 2019-06-03 13:41:08 -04:00
parent c3417aeeed
commit 2a8290d9c0
7 changed files with 387 additions and 246 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

76
src/mame/drivers/indy_indigo2.cpp
View File

@ -21,8 +21,8 @@
* 1f400000 - 1f5fffff GIO64 - EXP0 * 1f400000 - 1f5fffff GIO64 - EXP0
* 1f600000 - 1f9fffff GIO64 - EXP1 - Unused * 1f600000 - 1f9fffff GIO64 - EXP1 - Unused
* 1fa00000 - 1fa1ffff Memory Controller * 1fa00000 - 1fa1ffff Memory Controller
* 1fb00000 - 1fb1a7ff HPC3 CHIP1 * 1fb00000 - 1fb7ffff HPC3 CHIP1
* 1fb80000 - 1fb9a7ff HPC3 CHIP0 * 1fb80000 - 1fbfffff HPC3 CHIP0
* 1fc00000 - 1fffffff BIOS * 1fc00000 - 1fffffff BIOS
* 20000000 - 2fffffff High System Memory * 20000000 - 2fffffff High System Memory
* 30000000 - 7fffffff Reserved * 30000000 - 7fffffff Reserved
@ -102,13 +102,23 @@ public:
void indy_4610(machine_config &config); void indy_4610(machine_config &config);
protected: protected:
virtual void machine_start() override;
virtual void machine_reset() override; virtual void machine_reset() override;
DECLARE_WRITE64_MEMBER(write_ram); DECLARE_WRITE64_MEMBER(write_ram);
DECLARE_READ32_MEMBER(bus_error); DECLARE_READ32_MEMBER(bus_error);
uint8_t volume_r(offs_t offset);
void volume_w(offs_t offset, uint8_t data);
void ip24_map(address_map &map); void ip24_map(address_map &map);
void ip24_base_map(address_map &map); void ip24_base_map(address_map &map);
void pio0_map(address_map &map);
void pio1_map(address_map &map);
void pio2_map(address_map &map);
void pio3_map(address_map &map);
void pio5_map(address_map &map);
void pio6_map(address_map &map);
void wd33c93(device_t *device); void wd33c93(device_t *device);
@ -128,6 +138,9 @@ protected:
optional_device<gio64_slot_device> m_gio64_gfx; optional_device<gio64_slot_device> m_gio64_gfx;
optional_device<gio64_slot_device> m_gio64_exp0; optional_device<gio64_slot_device> m_gio64_exp0;
optional_device<gio64_slot_device> m_gio64_exp1; optional_device<gio64_slot_device> m_gio64_exp1;
uint8_t m_volume_l;
uint8_t m_volume_r;
}; };
class ip22_state : public ip24_state class ip22_state : public ip24_state
@ -147,6 +160,7 @@ private:
void wd33c93_2(device_t *device); void wd33c93_2(device_t *device);
void ip22_map(address_map &map); void ip22_map(address_map &map);
void pio4_map(address_map &map);
required_device<wd33c93b_device> m_scsi_ctrl2; required_device<wd33c93b_device> m_scsi_ctrl2;
}; };
@ -181,6 +195,28 @@ WRITE64_MEMBER(ip24_state::write_ram)
COMBINE_DATA(&m_mainram[offset]); COMBINE_DATA(&m_mainram[offset]);
} }
uint8_t ip24_state::volume_r(offs_t offset)
{
if (offset == 0)
return m_volume_r;
else
return m_volume_l;
}
void ip24_state::volume_w(offs_t offset, uint8_t data)
{
if (offset == 0)
{
m_volume_r = data;
m_hal2->set_right_volume(data);
}
else
{
m_volume_l = data;
m_hal2->set_left_volume(data);
}
}
void ip24_state::ip24_base_map(address_map &map) void ip24_state::ip24_base_map(address_map &map)
{ {
map(0x00000000, 0x0007ffff).bankrw("bank1"); /* mirror of first 512k of main RAM */ map(0x00000000, 0x0007ffff).bankrw("bank1"); /* mirror of first 512k of main RAM */
@ -199,12 +235,43 @@ void ip24_state::ip24_map(address_map &map)
map(0x00080000, 0x0009ffff).rw(m_vino, FUNC(vino_device::read), FUNC(vino_device::write)); map(0x00080000, 0x0009ffff).rw(m_vino, FUNC(vino_device::read), FUNC(vino_device::write));
} }
void ip24_state::pio0_map(address_map &map)
{
map(0x00, 0xff).rw(m_hal2, FUNC(hal2_device::read), FUNC(hal2_device::write));
}
void ip24_state::pio1_map(address_map &map)
{
map(0x00, 0xff).ram(); // hack
}
void ip24_state::pio2_map(address_map &map)
{
map(0x00, 0x01).rw(FUNC(ip24_state::volume_r), FUNC(ip24_state::volume_w)).umask16(0x00ff);
}
void ip24_state::pio6_map(address_map &map)
{
map(0x00, 0xff).rw(m_ioc2, FUNC(ioc2_device::read), FUNC(ioc2_device::write)).umask16(0x00ff);
}
void ip22_state::ip22_map(address_map &map) void ip22_state::ip22_map(address_map &map)
{ {
ip22_state::ip24_base_map(map); ip22_state::ip24_base_map(map);
map(0x00080000, 0x0009ffff).r(FUNC(ip22_state::eisa_io_r)); map(0x00080000, 0x0009ffff).r(FUNC(ip22_state::eisa_io_r));
} }
void ip22_state::pio4_map(address_map &map)
{
map(0x00, 0xff).rw("ioc2", FUNC(ioc2_full_house_device::int2_r), FUNC(ioc2_full_house_device::int2_w)).umask16(0x00ff);
}
void ip24_state::machine_start()
{
save_item(NAME(m_volume_l));
save_item(NAME(m_volume_r));
}
void ip24_state::machine_reset() void ip24_state::machine_reset()
{ {
// set up low RAM mirror // set up low RAM mirror
@ -258,6 +325,10 @@ void ip24_state::ip24_base(machine_config &config)
SGI_HPC3(config, m_hpc3, m_ioc2, m_hal2); SGI_HPC3(config, m_hpc3, m_ioc2, m_hal2);
m_hpc3->set_gio64_space(m_maincpu, AS_PROGRAM); m_hpc3->set_gio64_space(m_maincpu, AS_PROGRAM);
m_hpc3->set_addrmap(hpc3_device::AS_PIO0, &ip24_state::pio0_map);
m_hpc3->set_addrmap(hpc3_device::AS_PIO1, &ip24_state::pio1_map);
m_hpc3->set_addrmap(hpc3_device::AS_PIO2, &ip24_state::pio2_map);
m_hpc3->set_addrmap(hpc3_device::AS_PIO6, &ip24_state::pio6_map);
m_hpc3->hd_rd_cb<0>().set(m_scsi_ctrl, FUNC(wd33c93b_device::indir_r)); m_hpc3->hd_rd_cb<0>().set(m_scsi_ctrl, FUNC(wd33c93b_device::indir_r));
m_hpc3->hd_wr_cb<0>().set(m_scsi_ctrl, FUNC(wd33c93b_device::indir_w)); m_hpc3->hd_wr_cb<0>().set(m_scsi_ctrl, FUNC(wd33c93b_device::indir_w));
m_hpc3->hd_dma_rd_cb<0>().set(m_scsi_ctrl, FUNC(wd33c93b_device::dma_r)); m_hpc3->hd_dma_rd_cb<0>().set(m_scsi_ctrl, FUNC(wd33c93b_device::dma_r));
@ -342,6 +413,7 @@ void ip22_state::indigo2_4415(machine_config &config)
NSCSI_CONNECTOR(config, "scsibus2:6", scsi_devices, nullptr, false); NSCSI_CONNECTOR(config, "scsibus2:6", scsi_devices, nullptr, false);
NSCSI_CONNECTOR(config, "scsibus2:7", scsi_devices, nullptr, false); NSCSI_CONNECTOR(config, "scsibus2:7", scsi_devices, nullptr, false);
m_hpc3->set_addrmap(hpc3_device::AS_PIO4, &ip22_state::pio4_map);
m_hpc3->hd_rd_cb<1>().set(m_scsi_ctrl2, FUNC(wd33c93b_device::indir_r)); m_hpc3->hd_rd_cb<1>().set(m_scsi_ctrl2, FUNC(wd33c93b_device::indir_r));
m_hpc3->hd_wr_cb<1>().set(m_scsi_ctrl2, FUNC(wd33c93b_device::indir_w)); m_hpc3->hd_wr_cb<1>().set(m_scsi_ctrl2, FUNC(wd33c93b_device::indir_w));
m_hpc3->hd_dma_rd_cb<1>().set(m_scsi_ctrl2, FUNC(wd33c93b_device::dma_r)); m_hpc3->hd_dma_rd_cb<1>().set(m_scsi_ctrl2, FUNC(wd33c93b_device::dma_r));

46
src/mame/machine/hal2.cpp
View File

@ -50,19 +50,19 @@ void hal2_device::device_reset()
{ {
m_isr = 0; m_isr = 0;
m_iar = 0; m_iar = 0;
memset(m_idr, 0, sizeof(uint32_t) * 4); memset(m_idr, 0, sizeof(uint16_t) * 4);
memset(m_codeca_ctrl, 0, sizeof(uint32_t) * 2); memset(m_codeca_ctrl, 0, sizeof(uint16_t) * 2);
m_codeca_channel = 0; m_codeca_channel = 0;
m_codeca_clock = 0; m_codeca_clock = 0;
m_codeca_channel_count = 0; m_codeca_channel_count = 0;
memset(m_codecb_ctrl, 0, sizeof(uint32_t) * 2); memset(m_codecb_ctrl, 0, sizeof(uint16_t) * 2);
m_codecb_channel = 0; m_codecb_channel = 0;
m_codecb_clock = 0; m_codecb_clock = 0;
m_codecb_channel_count = 0; m_codecb_channel_count = 0;
memset(m_bres_clock_sel, 0, sizeof(uint32_t) * 3); memset(m_bres_clock_sel, 0, sizeof(uint16_t) * 3);
memset(m_bres_clock_inc, 0, sizeof(uint32_t) * 3); memset(m_bres_clock_inc, 0, sizeof(uint16_t) * 3);
memset(m_bres_clock_modctrl, 0, sizeof(uint32_t) * 3); memset(m_bres_clock_modctrl, 0, sizeof(uint16_t) * 3);
memset(m_bres_clock_freq, 0, sizeof(uint32_t) * 3); memset(m_bres_clock_freq, 0, sizeof(uint16_t) * 3);
for (int i = 0; i < 3; i++) for (int i = 0; i < 3; i++)
{ {
m_bres_clock_rate[i] = attotime::zero; m_bres_clock_rate[i] = attotime::zero;
@ -70,7 +70,7 @@ void hal2_device::device_reset()
m_curr_dac = 0; m_curr_dac = 0;
} }
READ32_MEMBER(hal2_device::read) uint16_t hal2_device::read(offs_t offset)
{ {
switch (offset) switch (offset)
{ {
@ -82,38 +82,38 @@ READ32_MEMBER(hal2_device::read)
return 0x4011; return 0x4011;
case INDIRECT_DATA0_REG: case INDIRECT_DATA0_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 0 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 0 Read: %04x\n", machine().describe_context(), m_idr[0]);
return m_idr[0]; return m_idr[0];
case INDIRECT_DATA1_REG: case INDIRECT_DATA1_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 1 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 1 Read: %04x\n", machine().describe_context(), m_idr[1]);
return m_idr[1]; return m_idr[1];
case INDIRECT_DATA2_REG: case INDIRECT_DATA2_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 2 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 2 Read: %04x\n", machine().describe_context(), m_idr[2]);
return m_idr[2]; return m_idr[2];
case INDIRECT_DATA3_REG: case INDIRECT_DATA3_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 3 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 3 Read: %04x\n", machine().describe_context(), m_idr[3]);
return m_idr[3]; return m_idr[3];
} }
LOGMASKED(LOG_READS | LOG_UNKNOWN, "%s: Unknown HAL2 read: %08x & %08x\n", machine().describe_context(), 0x1fbd8000 + offset*4, mem_mask); LOGMASKED(LOG_READS | LOG_UNKNOWN, "%s: Unknown HAL2 read: %08x\n", machine().describe_context(), 0x1fbd8000 + offset*4);
return 0; return 0;
} }
WRITE32_MEMBER(hal2_device::write) void hal2_device::write(offs_t offset, uint16_t data)
{ {
switch (offset) switch (offset)
{ {
case STATUS_REG: case STATUS_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Status Write: 0x%08x (%08x)\n", machine().describe_context(), data, mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Status Write: 0x%04x\n", machine().describe_context(), data);
LOGMASKED(LOG_WRITES, " HAL2 Global Reset %s\n", (data & ISR_GLOBAL_RESET) ? "Inactive" : "Active"); LOGMASKED(LOG_WRITES, " HAL2 Global Reset %s\n", (data & ISR_GLOBAL_RESET) ? "Inactive" : "Active");
LOGMASKED(LOG_WRITES, " HAL2 Codec Reset %s\n", (data & ISR_CODEC_RESET) ? "Inactive" : "Active"); LOGMASKED(LOG_WRITES, " HAL2 Codec Reset %s\n", (data & ISR_CODEC_RESET) ? "Inactive" : "Active");
m_isr &= ~0x1c; m_isr &= ~0x1c;
m_isr |= data & 0x1c; m_isr |= data & 0x1c;
break; break;
case INDIRECT_ADDRESS_REG: case INDIRECT_ADDRESS_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Address Register Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Address Register Write: %04x\n", machine().describe_context(), data);
m_iar = data; m_iar = data;
switch (data & IAR_TYPE) switch (data & IAR_TYPE)
{ {
@ -253,7 +253,7 @@ WRITE32_MEMBER(hal2_device::write)
{ {
m_bres_clock_inc[clock_gen] = m_idr[0]; m_bres_clock_inc[clock_gen] = m_idr[0];
m_bres_clock_modctrl[clock_gen] = m_idr[1]; m_bres_clock_modctrl[clock_gen] = m_idr[1];
LOGMASKED(LOG_WRITES, " Inc:%04x, ModCtrl:%04x\n", (uint16_t)m_idr[0], (uint16_t)m_idr[1]); LOGMASKED(LOG_WRITES, " Inc:%04x, ModCtrl:%04x\n", m_idr[0], m_idr[1]);
update_clock_freq(clock_gen); update_clock_freq(clock_gen);
} }
} }
@ -305,27 +305,27 @@ WRITE32_MEMBER(hal2_device::write)
return; return;
case INDIRECT_DATA0_REG: case INDIRECT_DATA0_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 0 Write: %04x\n", machine().describe_context(), data);
m_idr[0] = data; m_idr[0] = data;
return; return;
case INDIRECT_DATA1_REG: case INDIRECT_DATA1_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 1 Write: %04x\n", machine().describe_context(), data);
m_idr[1] = data; m_idr[1] = data;
return; return;
case INDIRECT_DATA2_REG: case INDIRECT_DATA2_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 2 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 2 Write: %04x\n", machine().describe_context(), data);
m_idr[2] = data; m_idr[2] = data;
return; return;
case INDIRECT_DATA3_REG: case INDIRECT_DATA3_REG:
LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 3 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 3 Write: %04x\n", machine().describe_context(), data);
m_idr[3] = data; m_idr[3] = data;
return; return;
default: default:
LOGMASKED(LOG_WRITES, "%s: Unknown HAL2 Write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fbd8000 + offset*4, data, mem_mask); LOGMASKED(LOG_WRITES, "%s: Unknown HAL2 Write: %08x = %04x\n", machine().describe_context(), 0x1fbd8000 + offset*4, data);
break; break;
} }
} }
@ -346,7 +346,7 @@ void hal2_device::update_clock_freq(int clock_gen)
return; return;
} }
const uint32_t mod = 0x10000 - (((uint16_t)m_bres_clock_modctrl[clock_gen] + 1) - m_bres_clock_inc[clock_gen]); const uint32_t mod = 0x10000 - ((m_bres_clock_modctrl[clock_gen] + 1) - m_bres_clock_inc[clock_gen]);
if (mod == 0) if (mod == 0)
m_bres_clock_rate[clock_gen] = attotime::from_ticks(1, m_bres_clock_freq[clock_gen] * m_bres_clock_inc[clock_gen]); m_bres_clock_rate[clock_gen] = attotime::from_ticks(1, m_bres_clock_freq[clock_gen] * m_bres_clock_inc[clock_gen]);
else else

36
src/mame/machine/hal2.h
View File

@ -25,8 +25,8 @@ public:
hal2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); hal2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
DECLARE_WRITE32_MEMBER(write); void write(offs_t offset, uint16_t data);
DECLARE_READ32_MEMBER(read); uint16_t read(offs_t offset);
attotime get_rate(const uint32_t channel); attotime get_rate(const uint32_t channel);
@ -83,27 +83,27 @@ protected:
required_device<dac_16bit_r2r_twos_complement_device> m_ldac; required_device<dac_16bit_r2r_twos_complement_device> m_ldac;
required_device<dac_16bit_r2r_twos_complement_device> m_rdac; required_device<dac_16bit_r2r_twos_complement_device> m_rdac;
uint32_t m_isr; uint16_t m_isr;
uint32_t m_iar; uint16_t m_iar;
uint32_t m_idr[4]; uint16_t m_idr[4];
uint32_t m_codeca_ctrl[2]; uint16_t m_codeca_ctrl[2];
uint32_t m_codeca_channel; uint16_t m_codeca_channel;
uint32_t m_codeca_clock; uint16_t m_codeca_clock;
uint32_t m_codeca_channel_count; uint16_t m_codeca_channel_count;
uint32_t m_codecb_ctrl[2]; uint16_t m_codecb_ctrl[2];
uint32_t m_codecb_channel; uint16_t m_codecb_channel;
uint32_t m_codecb_clock; uint16_t m_codecb_clock;
uint32_t m_codecb_channel_count; uint16_t m_codecb_channel_count;
uint32_t m_bres_clock_sel[3]; uint16_t m_bres_clock_sel[3];
uint32_t m_bres_clock_inc[3]; uint16_t m_bres_clock_inc[3];
uint32_t m_bres_clock_modctrl[3]; uint16_t m_bres_clock_modctrl[3];
uint32_t m_bres_clock_freq[3]; uint16_t m_bres_clock_freq[3];
attotime m_bres_clock_rate[3]; attotime m_bres_clock_rate[3];
uint32_t m_curr_dac; uint16_t m_curr_dac;
static const uint32_t s_channel_pair[4]; static const uint32_t s_channel_pair[4];
}; };

224
src/mame/machine/hpc3.cpp
View File

@ -15,10 +15,9 @@
#define LOG_SCSI_DMA (1 << 3) #define LOG_SCSI_DMA (1 << 3)
#define LOG_SCSI_IRQ (1 << 4) #define LOG_SCSI_IRQ (1 << 4)
#define LOG_ETHERNET (1 << 5) #define LOG_ETHERNET (1 << 5)
#define LOG_PBUS4 (1 << 6) #define LOG_CHAIN (1 << 6)
#define LOG_CHAIN (1 << 7) #define LOG_EEPROM (1 << 7)
#define LOG_EEPROM (1 << 8) #define LOG_ALL (LOG_UNKNOWN | LOG_PBUS_DMA | LOG_SCSI | LOG_SCSI_DMA | LOG_SCSI_IRQ | LOG_ETHERNET | LOG_CHAIN | LOG_EEPROM)
#define LOG_ALL (LOG_UNKNOWN | LOG_PBUS_DMA | LOG_SCSI | LOG_SCSI_DMA | LOG_SCSI_IRQ | LOG_ETHERNET | LOG_PBUS4 | LOG_CHAIN | LOG_EEPROM)
#define VERBOSE (0) #define VERBOSE (0)
#include "logmacro.h" #include "logmacro.h"
@ -27,6 +26,18 @@ DEFINE_DEVICE_TYPE(SGI_HPC3, hpc3_device, "hpc3", "SGI HPC3")
hpc3_device::hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) hpc3_device::hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, SGI_HPC3, tag, owner, clock) : device_t(mconfig, SGI_HPC3, tag, owner, clock)
, device_memory_interface(mconfig, *this)
, m_pio_space_config{
{"PIO channel 0", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 1", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 2", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 3", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 4", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 5", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 6", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 7", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 8", ENDIANNESS_LITTLE, 16, 8, -1},
{"PIO channel 9", ENDIANNESS_LITTLE, 16, 8, -1}}
, m_gio64_space(*this, finder_base::DUMMY_TAG, -1) , m_gio64_space(*this, finder_base::DUMMY_TAG, -1)
, m_ioc2(*this, finder_base::DUMMY_TAG) , m_ioc2(*this, finder_base::DUMMY_TAG)
, m_hal2(*this, finder_base::DUMMY_TAG) , m_hal2(*this, finder_base::DUMMY_TAG)
@ -46,6 +57,22 @@ hpc3_device::hpc3_device(const machine_config &mconfig, const char *tag, device_
{ {
} }
device_memory_interface::space_config_vector hpc3_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PIO0, &m_pio_space_config[0]),
std::make_pair(AS_PIO1, &m_pio_space_config[1]),
std::make_pair(AS_PIO2, &m_pio_space_config[2]),
std::make_pair(AS_PIO3, &m_pio_space_config[3]),
std::make_pair(AS_PIO4, &m_pio_space_config[4]),
std::make_pair(AS_PIO5, &m_pio_space_config[5]),
std::make_pair(AS_PIO6, &m_pio_space_config[6]),
std::make_pair(AS_PIO7, &m_pio_space_config[7]),
std::make_pair(AS_PIO8, &m_pio_space_config[8]),
std::make_pair(AS_PIO9, &m_pio_space_config[9])
};
}
void hpc3_device::device_resolve_objects() void hpc3_device::device_resolve_objects()
{ {
for (int index = 0; index < 2; index++) for (int index = 0; index < 2; index++)
@ -68,11 +95,13 @@ void hpc3_device::device_resolve_objects()
void hpc3_device::device_start() void hpc3_device::device_start()
{ {
for (uint32_t i = 0; i < 10; i++)
m_pio_space[i] = &space(AS_PIO0 + i);
save_item(NAME(m_intstat)); save_item(NAME(m_intstat));
save_item(NAME(m_misc));
save_item(NAME(m_cpu_aux_ctrl)); save_item(NAME(m_cpu_aux_ctrl));
save_item(NAME(m_pio_config)); save_item(NAME(m_pio_config));
save_item(NAME(m_volume_l));
save_item(NAME(m_volume_r));
for (uint32_t i = 0; i < 2; i++) for (uint32_t i = 0; i < 2; i++)
{ {
@ -170,16 +199,13 @@ void hpc3_device::map(address_map &map)
map(0x0002c000, 0x0002c0ff).rw(FUNC(hpc3_device::fifo_r<FIFO_ENET_RECV>), FUNC(hpc3_device::fifo_w<FIFO_ENET_RECV>)); // ENET Recv FIFO map(0x0002c000, 0x0002c0ff).rw(FUNC(hpc3_device::fifo_r<FIFO_ENET_RECV>), FUNC(hpc3_device::fifo_w<FIFO_ENET_RECV>)); // ENET Recv FIFO
map(0x0002e000, 0x0002e13f).rw(FUNC(hpc3_device::fifo_r<FIFO_ENET_XMIT>), FUNC(hpc3_device::fifo_w<FIFO_ENET_XMIT>)); // ENET Xmit FIFO map(0x0002e000, 0x0002e13f).rw(FUNC(hpc3_device::fifo_r<FIFO_ENET_XMIT>), FUNC(hpc3_device::fifo_w<FIFO_ENET_XMIT>)); // ENET Xmit FIFO
map(0x00030000, 0x00030003).r(FUNC(hpc3_device::intstat_r)); map(0x00030000, 0x00030003).r(FUNC(hpc3_device::intstat_r));
map(0x00030004, 0x00030007).rw(FUNC(hpc3_device::misc_r), FUNC(hpc3_device::misc_w));
map(0x00030008, 0x0003000b).rw(FUNC(hpc3_device::eeprom_r), FUNC(hpc3_device::eeprom_w)); map(0x00030008, 0x0003000b).rw(FUNC(hpc3_device::eeprom_r), FUNC(hpc3_device::eeprom_w));
map(0x0003000c, 0x0003000f).r(FUNC(hpc3_device::intstat_r)); map(0x0003000c, 0x0003000f).r(FUNC(hpc3_device::intstat_r));
map(0x00040000, 0x00047fff).rw(FUNC(hpc3_device::hd_r<0>), FUNC(hpc3_device::hd_w<0>)); map(0x00040000, 0x00047fff).rw(FUNC(hpc3_device::hd_r<0>), FUNC(hpc3_device::hd_w<0>));
map(0x00048000, 0x0004ffff).rw(FUNC(hpc3_device::hd_r<1>), FUNC(hpc3_device::hd_w<1>)); map(0x00048000, 0x0004ffff).rw(FUNC(hpc3_device::hd_r<1>), FUNC(hpc3_device::hd_w<1>));
map(0x00054000, 0x000544ff).rw(FUNC(hpc3_device::enet_r), FUNC(hpc3_device::enet_w)); map(0x00054000, 0x000544ff).rw(FUNC(hpc3_device::enet_r), FUNC(hpc3_device::enet_w));
map(0x00058000, 0x000583ff).rw(m_hal2, FUNC(hal2_device::read), FUNC(hal2_device::write)); map(0x00058000, 0x0005bfff).rw(FUNC(hpc3_device::pio_data_r), FUNC(hpc3_device::pio_data_w));
map(0x00058400, 0x000587ff).ram(); // hack
map(0x00058800, 0x00058807).rw(FUNC(hpc3_device::volume_r), FUNC(hpc3_device::volume_w));
map(0x00059000, 0x000593ff).rw(FUNC(hpc3_device::pbus4_r), FUNC(hpc3_device::pbus4_w));
map(0x00059800, 0x00059bff).rw(m_ioc2, FUNC(ioc2_device::read), FUNC(ioc2_device::write));
map(0x0005c000, 0x0005cfff).rw(FUNC(hpc3_device::dma_config_r), FUNC(hpc3_device::dma_config_w)); map(0x0005c000, 0x0005cfff).rw(FUNC(hpc3_device::dma_config_r), FUNC(hpc3_device::dma_config_w));
map(0x0005d000, 0x0005dfff).rw(FUNC(hpc3_device::pio_config_r), FUNC(hpc3_device::pio_config_w)); map(0x0005d000, 0x0005dfff).rw(FUNC(hpc3_device::pio_config_r), FUNC(hpc3_device::pio_config_w));
map(0x00060000, 0x0007ffff).rw(FUNC(hpc3_device::bbram_r), FUNC(hpc3_device::bbram_w)); map(0x00060000, 0x0007ffff).rw(FUNC(hpc3_device::bbram_r), FUNC(hpc3_device::bbram_w));
@ -213,7 +239,7 @@ void hpc3_device::do_pbus_dma(uint32_t channel)
if (dma.m_active && channel < 4) if (dma.m_active && channel < 4)
{ {
uint16_t temp16 = m_gio64_space->read_dword(dma.m_cur_ptr) >> 16; uint16_t temp16 = m_gio64_space->read_dword(dma.m_cur_ptr) >> 16;
int16_t stemp16 = (int16_t)((temp16 >> 8) | (temp16 << 8)); int16_t stemp16 = (int16_t)(BIT(m_pbus_dma[channel].m_config, 19) ? temp16 : swapendian_int16(temp16));
m_hal2->dma_write(channel, stemp16); m_hal2->dma_write(channel, stemp16);
@ -569,131 +595,55 @@ WRITE32_MEMBER(hpc3_device::hd_w)
} }
} }
READ32_MEMBER(hpc3_device::volume_r)
{
if (offset == 0)
return m_volume_r;
else
return m_volume_l;
}
WRITE32_MEMBER(hpc3_device::volume_w)
{
if (offset == 0)
{
m_volume_r = (uint8_t)data;
m_hal2->set_right_volume((uint8_t)data);
}
else
{
m_volume_l = (uint8_t)data;
m_hal2->set_left_volume((uint8_t)data);
}
}
template READ32_MEMBER(hpc3_device::hd_r<0>); template READ32_MEMBER(hpc3_device::hd_r<0>);
template READ32_MEMBER(hpc3_device::hd_r<1>); template READ32_MEMBER(hpc3_device::hd_r<1>);
template WRITE32_MEMBER(hpc3_device::hd_w<0>); template WRITE32_MEMBER(hpc3_device::hd_w<0>);
template WRITE32_MEMBER(hpc3_device::hd_w<1>); template WRITE32_MEMBER(hpc3_device::hd_w<1>);
READ32_MEMBER(hpc3_device::pbus4_r) uint32_t hpc3_device::pio_data_r(offs_t offset)
{ {
uint32_t ret = 0; uint32_t channel = (offset >> 8) & 15;
switch (offset) if (channel >= 10)
{ {
case 0x0000/4: channel = (channel & 1) ? 9 : 8;
ret = m_ioc2->get_local_int_status(0); }
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Status Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break; switch ((m_pio_config[channel] >> 18) & 3)
case 0x0004/4: {
ret = m_ioc2->get_local_int_mask(0); default:
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); case 0: // 8-bit, data on PBUS 7:0
break; return m_pio_space[channel]->read_word(offset & 0xff, 0x00ff) & 0xff;
case 0x0008/4:
ret = m_ioc2->get_local_int_status(1); case 2: // 8-bit, data on PBUS 15:8
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Status Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); return m_pio_space[channel]->read_word(offset & 0xff, 0xff00) >> 8;
break;
case 0x000c/4: case 1: // 16-bit, odd high
ret = m_ioc2->get_local_int_mask(1); case 3: // 16-bit, even high
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask); return m_pio_space[channel]->read_word(offset & 0xff, 0xffff);
break;
case 0x0010/4:
ret = m_ioc2->get_map_int_status();
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mappable Interrupt Status: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break;
case 0x0014/4:
ret = m_ioc2->get_map_int_mask(0);
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 0 Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break;
case 0x0018/4:
ret = m_ioc2->get_map_int_mask(1);
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 1 Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break;
case 0x0030/4:
ret = m_ioc2->get_pit_reg(0);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 0 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break;
case 0x0034/4:
ret = m_ioc2->get_pit_reg(1);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 1 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break;
case 0x0038/4:
ret = m_ioc2->get_pit_reg(2);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 2 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break;
case 0x003c/4:
ret = m_ioc2->get_pit_reg(3);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Control Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
break;
default:
LOGMASKED(LOG_PBUS4 | LOG_UNKNOWN, "%s: Unknown HPC3 PBUS4 Read: %08x (%08x)\n", machine().describe_context(), 0x1fbd9000 + (offset << 2), mem_mask);
break;
} }
return ret;
} }
WRITE32_MEMBER(hpc3_device::pbus4_w) void hpc3_device::pio_data_w(offs_t offset, uint32_t data)
{ {
switch (offset) uint32_t channel = (offset >> 8) & 15;
if (channel >= 10)
{ {
case 0x0004/4: channel = (channel & 1) ? 9 : 8;
m_ioc2->set_local_int_mask(0, data); }
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
switch ((m_pio_config[channel] >> 18) & 3)
{
case 0: // 8-bit, data on PBUS 7:0
m_pio_space[channel]->write_word(offset & 0xff, data & 0xffff, 0x00ff);
break; break;
case 0x000c/4:
m_ioc2->set_local_int_mask(1, data); case 2: // 8-bit, data on PBUS 15:8
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); m_pio_space[channel]->write_word(offset & 0xff, swapendian_int16(data & 0xffff), 0xff00);
break; break;
case 0x0014/4:
m_ioc2->set_map_int_mask(0, data); case 1: // 16-bit, odd high
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 0 Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask); case 3: // 16-bit, even high
break; m_pio_space[channel]->write_word(offset & 0xff, data & 0xffff, 0xffff);
case 0x0018/4:
m_ioc2->set_map_int_mask(1, data);
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 1 Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x0020/4:
m_ioc2->set_timer_int_clear(data);
LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Timer Interrupt Clear Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x0030/4:
m_ioc2->set_pit_reg(0, (uint8_t)data);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x0034/4:
m_ioc2->set_pit_reg(1, (uint8_t)data);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x0038/4:
m_ioc2->set_pit_reg(2, (uint8_t)data);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 2 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
case 0x003c/4:
m_ioc2->set_pit_reg(3, (uint8_t)data);
LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Control Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
break;
default:
LOGMASKED(LOG_PBUS4 | LOG_UNKNOWN, "%s: Unknown HPC3 PBUS4 Write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fbd9000 + (offset << 2), data, mem_mask);
break; break;
} }
} }
@ -805,7 +755,7 @@ WRITE32_MEMBER(hpc3_device::dma_config_w)
LOGMASKED(LOG_PBUS_DMA, " DMA Write State D3 gio_clk cycles: %d\n", BIT(data, 9) ? 2 : 3); LOGMASKED(LOG_PBUS_DMA, " DMA Write State D3 gio_clk cycles: %d\n", BIT(data, 9) ? 2 : 3);
LOGMASKED(LOG_PBUS_DMA, " DMA Write State D4 gio_clk cycles: %d\n", (data >> 10) & 0xf); LOGMASKED(LOG_PBUS_DMA, " DMA Write State D4 gio_clk cycles: %d\n", (data >> 10) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " DMA Write State D5 gio_clk cycles: %d\n", (data >> 14) & 0xf); LOGMASKED(LOG_PBUS_DMA, " DMA Write State D5 gio_clk cycles: %d\n", (data >> 14) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " Device Bit Width: %d\n", BIT(data, 18) ? 16 : 32); LOGMASKED(LOG_PBUS_DMA, " Device Bit Width: %d\n", BIT(data, 18) ? 16 : 8);
LOGMASKED(LOG_PBUS_DMA, " Even Address Bytes on %s\n", BIT(data, 19) ? "15..8" : "7..0"); LOGMASKED(LOG_PBUS_DMA, " Even Address Bytes on %s\n", BIT(data, 19) ? "15..8" : "7..0");
LOGMASKED(LOG_PBUS_DMA, " Device %s Real-Time\n", BIT(data, 21) ? "is" : "is not"); LOGMASKED(LOG_PBUS_DMA, " Device %s Real-Time\n", BIT(data, 21) ? "is" : "is not");
LOGMASKED(LOG_PBUS_DMA, " Burst Count: %d\n", (data >> 22) & 0x1f); LOGMASKED(LOG_PBUS_DMA, " Burst Count: %d\n", (data >> 22) & 0x1f);
@ -841,7 +791,7 @@ WRITE32_MEMBER(hpc3_device::pio_config_w)
LOGMASKED(LOG_PBUS_DMA, " PIO Write State P2 gio_clk cycles: %d\n", BIT(data, 9) ? 1 : 2); LOGMASKED(LOG_PBUS_DMA, " PIO Write State P2 gio_clk cycles: %d\n", BIT(data, 9) ? 1 : 2);
LOGMASKED(LOG_PBUS_DMA, " PIO Write State P3 gio_clk cycles: %d\n", (data >> 10) & 0xf); LOGMASKED(LOG_PBUS_DMA, " PIO Write State P3 gio_clk cycles: %d\n", (data >> 10) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " PIO Write State P4 gio_clk cycles: %d\n", (data >> 14) & 0xf); LOGMASKED(LOG_PBUS_DMA, " PIO Write State P4 gio_clk cycles: %d\n", (data >> 14) & 0xf);
LOGMASKED(LOG_PBUS_DMA, " Device Bit Width: %d\n", BIT(data, 18) ? 16 : 32); LOGMASKED(LOG_PBUS_DMA, " Device Bit Width: %d\n", BIT(data, 18) ? 16 : 8);
LOGMASKED(LOG_PBUS_DMA, " Even Address Bytes on %s\n", BIT(data, 19) ? "15..8" : "7..0"); LOGMASKED(LOG_PBUS_DMA, " Even Address Bytes on %s\n", BIT(data, 19) ? "15..8" : "7..0");
} }
@ -855,17 +805,6 @@ void hpc3_device::bbram_w(offs_t offset, uint32_t data)
m_bbram_wr_cb(offset, data); m_bbram_wr_cb(offset, data);
} }
READ32_MEMBER(hpc3_device::unkpbus0_r)
{
LOGMASKED(LOG_UNKNOWN, "%s: Unknown PBUS Read: %08x & %08x\n", machine().describe_context(), 0x1fbc8000 + offset*4, mem_mask);
return 0;
}
WRITE32_MEMBER(hpc3_device::unkpbus0_w)
{
LOGMASKED(LOG_UNKNOWN, "%s: Unknown PBUS Write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fbc8000 + offset*4, data, mem_mask);
}
void hpc3_device::dump_chain(uint32_t base) void hpc3_device::dump_chain(uint32_t base)
{ {
const uint32_t addr = m_gio64_space->read_dword(base); const uint32_t addr = m_gio64_space->read_dword(base);
@ -992,6 +931,19 @@ READ32_MEMBER(hpc3_device::intstat_r)
return m_intstat; return m_intstat;
} }
uint32_t hpc3_device::misc_r()
{
return m_misc;
}
void hpc3_device::misc_w(uint32_t data)
{
LOGMASKED(LOG_PBUS_DMA, "%s: Write miscellaneous register: %08x\n", machine().describe_context(), data);
LOGMASKED(LOG_PBUS_DMA, " Real time devices %sabled\n", BIT(data, 0) ? "en" : "dis");
LOGMASKED(LOG_PBUS_DMA, " DMA descriptors are %s endian\n", BIT(data, 1) ? "little" : "big");
m_misc = data & 3;
}
uint32_t hpc3_device::eeprom_r() uint32_t hpc3_device::eeprom_r()
{ {
uint32_t ret = (m_cpu_aux_ctrl & ~0x10) | (m_eeprom_dati_cb() << 4); uint32_t ret = (m_cpu_aux_ctrl & ~0x10) | (m_eeprom_dati_cb() << 4);

34
src/mame/machine/hpc3.h
View File

@ -14,9 +14,23 @@
#include "machine/hal2.h" #include "machine/hal2.h"
#include "machine/ioc2.h" #include "machine/ioc2.h"
class hpc3_device : public device_t class hpc3_device : public device_t, public device_memory_interface
{ {
public: public:
enum pbus_space
{
AS_PIO0 = 0,
AS_PIO1,
AS_PIO2,
AS_PIO3,
AS_PIO4,
AS_PIO5,
AS_PIO6,
AS_PIO7,
AS_PIO8,
AS_PIO9
};
hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); hpc3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
template <typename T, typename U> template <typename T, typename U>
@ -58,6 +72,8 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
virtual space_config_vector memory_space_config() const override;
enum fifo_type_t : uint32_t enum fifo_type_t : uint32_t
{ {
FIFO_PBUS, FIFO_PBUS,
@ -76,16 +92,14 @@ protected:
template <fifo_type_t Type> DECLARE_READ32_MEMBER(fifo_r); template <fifo_type_t Type> DECLARE_READ32_MEMBER(fifo_r);
template <fifo_type_t Type> DECLARE_WRITE32_MEMBER(fifo_w); template <fifo_type_t Type> DECLARE_WRITE32_MEMBER(fifo_w);
DECLARE_READ32_MEMBER(intstat_r); DECLARE_READ32_MEMBER(intstat_r);
uint32_t misc_r();
void misc_w(uint32_t data);
uint32_t eeprom_r(); uint32_t eeprom_r();
void eeprom_w(uint32_t data); void eeprom_w(uint32_t data);
DECLARE_READ32_MEMBER(volume_r); uint32_t pio_data_r(offs_t offset);
DECLARE_WRITE32_MEMBER(volume_w); void pio_data_w(offs_t offset, uint32_t data);
DECLARE_READ32_MEMBER(pbus4_r);
DECLARE_WRITE32_MEMBER(pbus4_w);
DECLARE_READ32_MEMBER(pbusdma_r); DECLARE_READ32_MEMBER(pbusdma_r);
DECLARE_WRITE32_MEMBER(pbusdma_w); DECLARE_WRITE32_MEMBER(pbusdma_w);
DECLARE_READ32_MEMBER(unkpbus0_r);
DECLARE_WRITE32_MEMBER(unkpbus0_w);
DECLARE_READ32_MEMBER(dma_config_r); DECLARE_READ32_MEMBER(dma_config_r);
DECLARE_WRITE32_MEMBER(dma_config_w); DECLARE_WRITE32_MEMBER(dma_config_w);
@ -155,7 +169,10 @@ protected:
ENET_XMIT = 1 ENET_XMIT = 1
}; };
const address_space_config m_pio_space_config[10];
required_address_space m_gio64_space; required_address_space m_gio64_space;
address_space *m_pio_space[10];
required_device<ioc2_device> m_ioc2; required_device<ioc2_device> m_ioc2;
required_device<hal2_device> m_hal2; required_device<hal2_device> m_hal2;
@ -174,9 +191,8 @@ protected:
devcb_write_line m_dma_complete_int_cb; devcb_write_line m_dma_complete_int_cb;
uint32_t m_intstat; uint32_t m_intstat;
uint32_t m_misc;
uint32_t m_cpu_aux_ctrl; uint32_t m_cpu_aux_ctrl;
uint8_t m_volume_l;
uint8_t m_volume_r;
struct scsi_dma_t struct scsi_dma_t
{ {

196
src/mame/machine/ioc2.cpp
View File

@ -301,8 +301,10 @@ void ioc2_device::check_mappable_interrupt(int channel)
} }
} }
READ32_MEMBER(ioc2_device::read) uint8_t ioc2_device::read(offs_t offset)
{ {
address_space &space = machine().dummy_space();
switch (offset) switch (offset)
{ {
case PI1_DATA_REG: case PI1_DATA_REG:
@ -504,64 +506,66 @@ READ32_MEMBER(ioc2_device::read)
return 0; return 0;
} }
WRITE32_MEMBER( ioc2_device::write ) void ioc2_device::write(offs_t offset, uint8_t data)
{ {
address_space &space = machine().dummy_space();
switch (offset) switch (offset)
{ {
case PI1_DATA_REG: case PI1_DATA_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Data Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Data Register: %02x\n", machine().describe_context(), data);
m_pi1->write(space, offset, (uint8_t)data); m_pi1->write(space, offset, data);
return; return;
case PI1_CTRL_REG: case PI1_CTRL_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Control Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Control Register: %02x\n", machine().describe_context(), data);
m_pi1->write(space, offset, (uint8_t)data); m_pi1->write(space, offset, data);
return; return;
case PI1_STATUS_REG: case PI1_STATUS_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Status Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Status Register: %02x\n", machine().describe_context(), data);
m_pi1->write(space, offset, (uint8_t)data); m_pi1->write(space, offset, data);
return; return;
case PI1_DMA_CTRL_REG: case PI1_DMA_CTRL_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 DMA Control Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 DMA Control Register: %02x\n", machine().describe_context(), data);
return; return;
case PI1_INT_STATUS_REG: case PI1_INT_STATUS_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Interrupt Status Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Interrupt Status Register: %02x\n", machine().describe_context(), data);
return; return;
case PI1_INT_MASK_REG: case PI1_INT_MASK_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Interrupt Mask Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Interrupt Mask Register: %02x\n", machine().describe_context(), data);
return; return;
case PI1_TIMER1_REG: case PI1_TIMER1_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer1 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Timer1 Register: %02x\n", machine().describe_context(), data);
return; return;
case PI1_TIMER2_REG: case PI1_TIMER2_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer2 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Timer2 Register: %02x\n", machine().describe_context(), data);
return; return;
case PI1_TIMER3_REG: case PI1_TIMER3_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer3 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Timer3 Register: %02x\n", machine().describe_context(), data);
return; return;
case PI1_TIMER4_REG: case PI1_TIMER4_REG:
LOGMASKED(LOG_PI1, "%s: Write PI1 Timer4 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PI1, "%s: Write PI1 Timer4 Register: %02x\n", machine().describe_context(), data);
return; return;
case SERIAL1_CMD_REG: case SERIAL1_CMD_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 1 Command Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_SERIAL, "%s: Write Serial 1 Command Register: %02x\n", machine().describe_context(), data);
m_scc->ba_cd_w(space, 3, data & 0xff); m_scc->ba_cd_w(space, 3, data & 0xff);
return; return;
case SERIAL1_DATA_REG: case SERIAL1_DATA_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 1 Data Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_SERIAL, "%s: Write Serial 1 Data Register: %02x\n", machine().describe_context(), data);
m_scc->ba_cd_w(space, 2, data & 0xff); m_scc->ba_cd_w(space, 2, data & 0xff);
return; return;
case SERIAL2_CMD_REG: case SERIAL2_CMD_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 2 Command Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_SERIAL, "%s: Write Serial 2 Command Register: %02x\n", machine().describe_context(), data);
m_scc->ba_cd_w(space, 1, data & 0xff); m_scc->ba_cd_w(space, 1, data & 0xff);
return; return;
case SERIAL2_DATA_REG: case SERIAL2_DATA_REG:
LOGMASKED(LOG_SERIAL, "%s: Write Serial 2 Data Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_SERIAL, "%s: Write Serial 2 Data Register: %02x\n", machine().describe_context(), data);
m_scc->ba_cd_w(space, 0, data & 0xff); m_scc->ba_cd_w(space, 0, data & 0xff);
return; return;
case KBD_MOUSE_REGS1: case KBD_MOUSE_REGS1:
LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 1: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 1: %02x\n", machine().describe_context(), data);
#if IOC2_NEW_KBDC #if IOC2_NEW_KBDC
m_kbdc->data_w(data & 0xff); m_kbdc->data_w(data & 0xff);
#else #else
@ -569,7 +573,7 @@ WRITE32_MEMBER( ioc2_device::write )
#endif #endif
return; return;
case KBD_MOUSE_REGS2: case KBD_MOUSE_REGS2:
LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 2: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 2: %02x\n", machine().describe_context(), data);
#if IOC2_NEW_KBDC #if IOC2_NEW_KBDC
m_kbdc->command_w(data & 0xff); m_kbdc->command_w(data & 0xff);
#else #else
@ -578,7 +582,7 @@ WRITE32_MEMBER( ioc2_device::write )
return; return;
case PANEL_REG: case PANEL_REG:
LOGMASKED(LOG_PANEL, "%s: Write Front Panel Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PANEL, "%s: Write Front Panel Register: %02x\n", machine().describe_context(), data);
m_front_panel_reg &= ~(data & (FRONT_PANEL_VOL_UP_INT | FRONT_PANEL_VOL_DOWN_INT | FRONT_PANEL_POWER_BUTTON_INT)); m_front_panel_reg &= ~(data & (FRONT_PANEL_VOL_UP_INT | FRONT_PANEL_VOL_DOWN_INT | FRONT_PANEL_POWER_BUTTON_INT));
if (!(m_front_panel_reg & FRONT_PANEL_INT_MASK)) if (!(m_front_panel_reg & FRONT_PANEL_INT_MASK))
lower_local_irq(1, INT3_LOCAL1_PANEL); lower_local_irq(1, INT3_LOCAL1_PANEL);
@ -592,7 +596,7 @@ WRITE32_MEMBER( ioc2_device::write )
// 2 RW Parallel Port DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [this makes sense. -ed.] // 2 RW Parallel Port DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [this makes sense. -ed.]
// 1 RW ISDN Channel B DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [is this a copy/paste error? perhaps "Parallel Port" should be "ISDN Channel B"?] // 1 RW ISDN Channel B DMA Select. A high bit selects the Parallel Port DMA channel. 0\h is the default after reset. [is this a copy/paste error? perhaps "Parallel Port" should be "ISDN Channel B"?]
// 0 RW [same text as above. Another copy/paste error, maybe? Should be channel A, with the bit selecting DMA channel 0/1 for ISDN channel A, the and the same for ISDN channel B in bit 1?] // 0 RW [same text as above. Another copy/paste error, maybe? Should be channel A, with the bit selecting DMA channel 0/1 for ISDN channel A, the and the same for ISDN channel B in bit 1?]
LOGMASKED(LOG_DMA_SEL, "%s: Write DMA Select Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_DMA_SEL, "%s: Write DMA Select Register: %02x\n", machine().describe_context(), data);
uint8_t old = m_dma_sel; uint8_t old = m_dma_sel;
m_dma_sel = data; m_dma_sel = data;
uint8_t changed = old ^ m_dma_sel; uint8_t changed = old ^ m_dma_sel;
@ -609,12 +613,12 @@ WRITE32_MEMBER( ioc2_device::write )
} }
case RESET_REG: case RESET_REG:
LOGMASKED(LOG_RESET, "%s: Write Reset Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_RESET, "%s: Write Reset Register: %02x\n", machine().describe_context(), data);
handle_reset_reg_write(data); handle_reset_reg_write(data);
return; return;
case WRITE_REG: case WRITE_REG:
LOGMASKED(LOG_WRITE, "%s: Write Write Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_WRITE, "%s: Write Write Register: %02x\n", machine().describe_context(), data);
m_write_reg = data; m_write_reg = data;
return; return;
@ -626,71 +630,173 @@ WRITE32_MEMBER( ioc2_device::write )
return; return;
case INT3_LOCAL0_MASK_REG: case INT3_LOCAL0_MASK_REG:
LOGMASKED(LOG_INT3, "%s: Write Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_INT3, "%s: Write Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), data);
set_local_int_mask(0, data); set_local_int_mask(0, data);
return; return;
case INT3_LOCAL1_MASK_REG: case INT3_LOCAL1_MASK_REG:
LOGMASKED(LOG_INT3, "%s: Write Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_INT3, "%s: Write Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), data);
set_local_int_mask(1, data); set_local_int_mask(1, data);
return; return;
case INT3_MAP_MASK0_REG: case INT3_MAP_MASK0_REG:
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), data);
set_map_int_mask(0, data); set_map_int_mask(0, data);
return; return;
case INT3_MAP_MASK1_REG: case INT3_MAP_MASK1_REG:
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), data);
set_map_int_mask(1, data); set_map_int_mask(1, data);
return; return;
case INT3_MAP_POLARITY_REG: case INT3_MAP_POLARITY_REG:
// TODO: Mappable interrupt polarity select // TODO: Mappable interrupt polarity select
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Polarity Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Polarity Register: %02x\n", machine().describe_context(), data);
m_int3_map_pol_reg = data; m_int3_map_pol_reg = data;
return; return;
case INT3_TIMER_CLEAR_REG: case INT3_TIMER_CLEAR_REG:
LOGMASKED(LOG_INT3, "%s: Write Interrupt Timer Clear Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_INT3, "%s: Write Interrupt Timer Clear Register: %02x\n", machine().describe_context(), data);
set_timer_int_clear(data); set_timer_int_clear(data);
return; return;
case TIMER_COUNT0_REG: case TIMER_COUNT0_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Count0 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PIT, "%s: Write Timer Count0 Register: %02x\n", machine().describe_context(), data);
m_pit->write(0, (uint8_t)data); m_pit->write(0, data);
return; return;
case TIMER_COUNT1_REG: case TIMER_COUNT1_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Count1 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PIT, "%s: Write Timer Count1 Register: %02x\n", machine().describe_context(), data);
m_pit->write(1, (uint8_t)data); m_pit->write(1, data);
return; return;
case TIMER_COUNT2_REG: case TIMER_COUNT2_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Count2 Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PIT, "%s: Write Timer Count2 Register: %02x\n", machine().describe_context(), data);
m_pit->write(2, (uint8_t)data); m_pit->write(2, data);
return; return;
case TIMER_CONTROL_REG: case TIMER_CONTROL_REG:
LOGMASKED(LOG_PIT, "%s: Write Timer Control Register: %02x\n", machine().describe_context(), (uint8_t)data); LOGMASKED(LOG_PIT, "%s: Write Timer Control Register: %02x\n", machine().describe_context(), data);
m_pit->write(3, (uint8_t)data); m_pit->write(3, data);
return; return;
} }
} }
void ioc2_device::set_local_int_mask(int channel, uint32_t mask) uint8_t ioc2_full_house_device::int2_r(offs_t offset)
{
uint8_t ret = 0;
switch (offset)
{
case 0x0000/4:
ret = m_int3_local_status_reg[0];
LOGMASKED(LOG_INT3, "%s: INT2 Local0 Interrupt Status Read: %02x\n", machine().describe_context(), ret);
break;
case 0x0004/4:
ret = m_int3_local_mask_reg[0];
LOGMASKED(LOG_INT3, "%s: INT2 Local0 Interrupt Mask Read: %02x\n", machine().describe_context(), ret);
break;
case 0x0008/4:
ret = m_int3_local_status_reg[1];
LOGMASKED(LOG_INT3, "%s: INT2 Local1 Interrupt Status Read: %02x\n", machine().describe_context(), ret);
break;
case 0x000c/4:
ret = m_int3_local_mask_reg[1];
LOGMASKED(LOG_INT3, "%s: INT2 Local1 Interrupt Mask Read: %02x\n", machine().describe_context(), ret);
break;
case 0x0010/4:
ret = m_int3_map_status_reg;
LOGMASKED(LOG_INT3, "%s: INT2 Mappable Interrupt Status: %02x\n", machine().describe_context(), ret);
break;
case 0x0014/4:
ret = m_int3_map_mask_reg[0];
LOGMASKED(LOG_INT3, "%s: INT2 Mapped Interrupt 0 Mask Read: %02x\n", machine().describe_context(), ret);
break;
case 0x0018/4:
ret = m_int3_map_mask_reg[1];
LOGMASKED(LOG_INT3, "%s: INT2 Mapped Interrupt 1 Mask Read: %02x\n", machine().describe_context(), ret);
break;
case 0x0030/4:
ret = m_pit->read(0);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Counter 0 Read: %02x\n", machine().describe_context(), ret);
break;
case 0x0034/4:
ret = m_pit->read(1);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Counter 1 Read: %02x\n", machine().describe_context(), ret);
break;
case 0x0038/4:
ret = m_pit->read(2);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Counter 2 Read: %02x\n", machine().describe_context(), ret);
break;
case 0x003c/4:
ret = m_pit->read(3);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Control Read: %02x\n", machine().describe_context(), ret);
break;
default:
LOGMASKED(LOG_READ, "%s: Unknown INT2 Read: %08x\n", machine().describe_context(), 0x1fbd9000 + (offset << 2));
break;
}
return ret;
}
void ioc2_full_house_device::int2_w(offs_t offset, uint8_t data)
{
switch (offset)
{
case 0x0004/4:
set_local_int_mask(0, data);
LOGMASKED(LOG_INT3, "%s: INT2 Local0 Interrupt Mask Write: %02x\n", machine().describe_context(), data);
break;
case 0x000c/4:
set_local_int_mask(1, data);
LOGMASKED(LOG_INT3, "%s: INT2 Local1 Interrupt Mask Write: %02x\n", machine().describe_context(), data);
break;
case 0x0014/4:
set_map_int_mask(0, data);
LOGMASKED(LOG_INT3, "%s: INT2 Mapped Interrupt 0 Mask Write: %02x\n", machine().describe_context(), data);
break;
case 0x0018/4:
set_map_int_mask(1, data);
LOGMASKED(LOG_INT3, "%s: INT2 Mapped Interrupt 1 Mask Write: %02x\n", machine().describe_context(), data);
break;
case 0x0020/4:
set_timer_int_clear(data);
LOGMASKED(LOG_INT3, "%s: INT2 Timer Interrupt Clear Write: %02x\n", machine().describe_context(), data);
break;
case 0x0030/4:
m_pit->write(0, data);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Counter 0 Write: %02x\n", machine().describe_context(), data);
break;
case 0x0034/4:
m_pit->write(1, data);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Counter 1 Write: %02x\n", machine().describe_context(), data);
break;
case 0x0038/4:
m_pit->write(2, data);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Counter 2 Write: %02x\n", machine().describe_context(), data);
break;
case 0x003c/4:
m_pit->write(3, data);
LOGMASKED(LOG_PIT, "%s: INT2 PIT Control Write: %02x\n", machine().describe_context(), data);
break;
default:
LOGMASKED(LOG_WRITE, "%s: Unknown INT2 Write: %08x = %02x\n", machine().describe_context(), 0x1fbd9000 + (offset << 2), data);
break;
}
}
void ioc2_device::set_local_int_mask(int channel, uint8_t mask)
{ {
uint8_t old = m_int3_local_mask_reg[channel]; uint8_t old = m_int3_local_mask_reg[channel];
m_int3_local_mask_reg[channel] = (uint8_t)mask; m_int3_local_mask_reg[channel] = mask;
bool old_line = (old & m_int3_local_status_reg[channel]) != 0; bool old_line = (old & m_int3_local_status_reg[channel]) != 0;
bool new_line = (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]) != 0; bool new_line = (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]) != 0;
if (old_line != new_line) if (old_line != new_line)
{ {
const uint32_t int_bits = (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]); const uint8_t int_bits = (m_int3_local_mask_reg[channel] & m_int3_local_status_reg[channel]);
m_maincpu->set_input_line(channel, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE); m_maincpu->set_input_line(channel, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE);
} }
} }
void ioc2_device::set_map_int_mask(int channel, uint32_t mask) void ioc2_device::set_map_int_mask(int channel, uint8_t mask)
{ {
m_int3_map_mask_reg[channel] = (uint8_t)mask; m_int3_map_mask_reg[channel] = mask;
check_mappable_interrupt(channel); check_mappable_interrupt(channel);
} }
void ioc2_device::set_timer_int_clear(uint32_t data) void ioc2_device::set_timer_int_clear(uint8_t data)
{ {
if (BIT(data, 0)) if (BIT(data, 0))
{ {

21
src/mame/machine/ioc2.h
View File

@ -30,8 +30,8 @@ class ioc2_device : public device_t
public: public:
template <typename T> void set_cpu_tag(T &&tag) { m_maincpu.set_tag(std::forward<T>(tag)); } template <typename T> void set_cpu_tag(T &&tag) { m_maincpu.set_tag(std::forward<T>(tag)); }
DECLARE_WRITE32_MEMBER( write ); void write(offs_t offset, uint8_t data);
DECLARE_READ32_MEMBER( read ); uint8_t read(offs_t offset);
DECLARE_INPUT_CHANGED_MEMBER( power_button ); DECLARE_INPUT_CHANGED_MEMBER( power_button );
DECLARE_INPUT_CHANGED_MEMBER( volume_down ); DECLARE_INPUT_CHANGED_MEMBER( volume_down );
@ -70,19 +70,11 @@ public:
INT3_LOCAL1_RETRACE = 0x80, INT3_LOCAL1_RETRACE = 0x80,
}; };
uint32_t get_local_int_status(int channel) const { return m_int3_local_status_reg[channel]; } void set_local_int_mask(int channel, const uint8_t mask);
uint32_t get_local_int_mask(int channel) const { return m_int3_local_mask_reg[channel]; } void set_map_int_mask(int channel, const uint8_t mask);
uint32_t get_map_int_status() const { return m_int3_map_status_reg; } void set_timer_int_clear(const uint8_t data);
uint32_t get_map_int_mask(int channel) const { return m_int3_map_mask_reg[channel]; }
void set_local_int_mask(int channel, const uint32_t mask);
void set_map_int_mask(int channel, const uint32_t mask);
void set_timer_int_clear(const uint32_t data);
void set_mappable_int(uint8_t mask, bool state); void set_mappable_int(uint8_t mask, bool state);
uint8_t get_pit_reg(uint32_t offset) { return m_pit->read(offset); }
void set_pit_reg(uint32_t offset, uint8_t data) { return m_pit->write(offset, data); }
protected: protected:
ioc2_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); ioc2_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
@ -245,6 +237,9 @@ public:
ioc2_full_house_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); ioc2_full_house_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
uint8_t int2_r(offs_t offset);
void int2_w(offs_t offset, uint8_t data);
protected: protected:
uint8_t get_system_id() override { return 0x11; } uint8_t get_system_id() override { return 0x11; }
}; };