mirror of
https://github.com/holub/mame
synced 2025-07-04 17:38:08 +03:00
sun4: Simplified DMA implementation. [Ryan Holtz]
This commit is contained in:
therealmogminer@gmail.com
parent
114aa294cd
commit
2ac8863d14
@ -554,8 +554,7 @@ public:
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static const device_timer_id TIMER_0 = 0;
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static const device_timer_id TIMER_1 = 1;
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static const device_timer_id TIMER_DMA = 2;
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static const device_timer_id TIMER_RESET = 3;
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static const device_timer_id TIMER_RESET = 2;
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DECLARE_READ32_MEMBER( sun4_mmu_r );
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DECLARE_WRITE32_MEMBER( sun4_mmu_w );
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@ -611,8 +610,9 @@ protected:
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uint32_t m_buserr[4];
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uint32_t m_counter[4];
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uint32_t m_dma[4];
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bool m_dma_tc_read;
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uint32_t m_dma_pack_register;
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int m_scsi_irq;
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int m_scsi_drq;
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private:
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uint32_t *m_ram_ptr;
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@ -629,7 +629,6 @@ private:
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int m_arch;
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emu_timer *m_c0_timer, *m_c1_timer;
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emu_timer *m_dma_timer;
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emu_timer *m_reset_timer;
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uint32_t read_insn_data(uint8_t asi, address_space &space, uint32_t offset, uint32_t mem_mask);
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@ -637,10 +636,10 @@ private:
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uint32_t read_insn_data_4c(uint8_t asi, address_space &space, uint32_t offset, uint32_t mem_mask);
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void write_insn_data_4c(uint8_t asi, address_space &space, uint32_t offset, uint32_t data, uint32_t mem_mask);
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void dma_set_int_pend(int state);
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void dma_update_irq();
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void dma_tick();
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void dma_setup_timer(bool continuing);
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void dma_check_interrupts();
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void dma_transfer();
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void dma_transfer_write();
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void dma_transfer_read();
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void start_timer(int num);
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@ -1340,7 +1339,8 @@ void sun4_state::machine_reset()
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m_irq_reg = 0;
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m_scc1_int = m_scc2_int = 0;
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m_scsi_irq = 0;
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m_scsi_drq = 0;
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m_dma_tc_read = false;
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m_dma_pack_register = 0;
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memset(m_counter, 0, sizeof(m_counter));
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memset(m_dma, 0, sizeof(m_dma));
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@ -1371,10 +1371,6 @@ void sun4_state::machine_start()
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// allocate timer for system reset
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m_reset_timer = timer_alloc(TIMER_RESET);
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m_reset_timer->adjust(attotime::never);
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// allocate timer for DMA controller
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m_dma_timer = timer_alloc(TIMER_DMA);
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m_dma_timer->adjust(attotime::never);
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}
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READ32_MEMBER( sun4_state::ram_r )
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@ -1575,10 +1571,6 @@ void sun4_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
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}
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break;
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case TIMER_DMA:
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dma_tick();
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break;
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case TIMER_RESET:
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m_reset_timer->adjust(attotime::never);
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m_maincpu->set_input_line(SPARC_RESET, CLEAR_LINE);
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@ -1665,22 +1657,15 @@ WRITE32_MEMBER( sun4_state::timer_w )
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}
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}
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void sun4_state::dma_set_int_pend(int state)
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void sun4_state::dma_check_interrupts()
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{
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if (!state)
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{
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m_dma[DMA_CTRL] &= ~DMA_INT_PEND;
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}
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else
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{
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bool tc_interrupt = (m_dma[DMA_CTRL] & DMA_TC) != 0 && !m_dma_tc_read;
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bool scsi_interrupt = m_scsi_irq != 0;
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m_dma[DMA_CTRL] &= ~DMA_INT_PEND;
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if (tc_interrupt || scsi_interrupt)
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m_dma[DMA_CTRL] |= DMA_INT_PEND;
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}
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dma_update_irq();
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}
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void sun4_state:: dma_update_irq()
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{
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int irq_or_err_pending = (m_dma[DMA_CTRL] & (DMA_INT_PEND | DMA_ERR_PEND)) ? 1 : 0;
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int irq_enabled = (m_dma[DMA_CTRL] & DMA_INT_EN) ? 1 : 0;
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if (irq_or_err_pending && irq_enabled)
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@ -1693,152 +1678,108 @@ void sun4_state:: dma_update_irq()
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}
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}
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void sun4_state::dma_tick()
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void sun4_state::dma_transfer_write()
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{
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uint32_t transfer_size = (m_dma[DMA_BYTE_COUNT] > PAGE_SIZE ? PAGE_SIZE : m_dma[DMA_BYTE_COUNT]);
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logerror("DMAing from device to RAM\n");
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address_space &space = m_maincpu->space(AS_PROGRAM);
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if (m_dma[DMA_CTRL] & DMA_WRITE)
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uint8_t pack_cnt = (m_dma[DMA_CTRL] & DMA_PACK_CNT) >> DMA_PACK_CNT_SHIFT;
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while (m_dma[DMA_CTRL] & DMA_REQ_PEND)
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{
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uint32_t data = 0;
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uint32_t byte_cnt = 3;
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uint32_t mem_mask = 0;
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while (transfer_size > 0)
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int bit_index = (3 - pack_cnt) * 8;
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uint8_t dma_value = m_scsi->dma_r();
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logerror("Read from device: %02x\n", dma_value);
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m_dma_pack_register |= dma_value << bit_index;
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if ((m_dma[DMA_CTRL] & DMA_EN_CNT) != 0)
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m_dma[DMA_BYTE_COUNT]--;
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pack_cnt++;
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if (pack_cnt == 4)
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{
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uint8_t value = m_scsi->dma_r();
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data |= value << (byte_cnt * 8);
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mem_mask |= 0xff << (byte_cnt * 8);
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transfer_size--;
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if (byte_cnt == 0)
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logerror("Writing pack register %08x\n", m_dma_pack_register);
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if (m_arch == ARCH_SUN4C)
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{
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if (m_arch == ARCH_SUN4C)
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{
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write_insn_data_4c(11, space, m_dma[DMA_ADDR] >> 2, data, mem_mask);
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}
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else
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{
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write_insn_data(11, space, m_dma[DMA_ADDR] >> 2, data, mem_mask);
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}
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m_dma[DMA_ADDR] += 4;
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m_dma[DMA_BYTE_COUNT] -= 4;
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byte_cnt = 3;
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data = 0;
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mem_mask = 0;
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write_insn_data_4c(11, space, m_dma[DMA_ADDR] >> 2, m_dma_pack_register, ~0);
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}
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else
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{
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byte_cnt--;
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write_insn_data(11, space, m_dma[DMA_ADDR] >> 2, m_dma_pack_register, ~0);
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}
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}
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if (byte_cnt != 0)
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pack_cnt = 0;
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m_dma_pack_register = 0;
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}
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}
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m_dma[DMA_CTRL] &= ~DMA_PACK_CNT;
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m_dma[DMA_CTRL] |= pack_cnt << DMA_PACK_CNT_SHIFT;
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}
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void sun4_state::dma_transfer_read()
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{
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logerror("DMAing from RAM to device\n");
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address_space &space = m_maincpu->space(AS_PROGRAM);
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bool word_cached = false;
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uint32_t current_word = 0;
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while (m_dma[DMA_CTRL] & DMA_REQ_PEND)
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{
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if (!word_cached)
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{
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if (m_arch == ARCH_SUN4C)
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{
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write_insn_data_4c(11, space, m_dma[DMA_ADDR] >> 2, data, mem_mask);
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current_word = read_insn_data_4c(11, space, m_dma[DMA_ADDR] >> 2, ~0);
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}
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else
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{
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write_insn_data(11, space, m_dma[DMA_ADDR] >> 2, data, mem_mask);
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}
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m_dma[DMA_ADDR] += byte_cnt;
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m_dma[DMA_BYTE_COUNT] -= byte_cnt;
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}
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}
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else
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{
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uint32_t byte_cnt = 3;
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uint32_t mem_mask = 0;
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while (transfer_size > 0)
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{
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mem_mask |= 0xff << (byte_cnt * 8);
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transfer_size--;
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if (byte_cnt == 0)
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{
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uint32_t data = 0;
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if (m_arch == ARCH_SUN4C)
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{
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data = read_insn_data_4c(11, space, m_dma[DMA_ADDR] >> 2, mem_mask);
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}
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else
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{
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data = read_insn_data(11, space, m_dma[DMA_ADDR] >> 2, mem_mask);
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}
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for (int i = 24; i >= 0; i -= 8)
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{
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m_scsi->dma_w((data >> i) & 0xff);
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m_dma[DMA_BYTE_COUNT]--;
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}
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byte_cnt = 3;
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mem_mask = 0;
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}
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else
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{
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byte_cnt--;
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current_word = read_insn_data(11, space, m_dma[DMA_ADDR] >> 2, ~0);
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}
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logerror("Current word: %08x\n", current_word);
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}
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if (byte_cnt != 0)
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{
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byte_cnt++;
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uint32_t data = 0;
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if (m_arch == ARCH_SUN4C)
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{
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data = read_insn_data_4c(11, space, m_dma[DMA_ADDR] >> 2, mem_mask);
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}
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else
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{
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data = read_insn_data(11, space, m_dma[DMA_ADDR] >> 2, mem_mask);
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}
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int bit_index = (3 - (m_dma[DMA_ADDR] & 3)) * 8;
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uint8_t dma_value(current_word >> bit_index);
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logerror("Write to device: %02x\n", dma_value);
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m_scsi->dma_w(dma_value);
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uint32_t initial_cnt = byte_cnt;
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for (int i = 0; i < 4 - initial_cnt; i++)
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{
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uint8_t byte_val = (data >> (byte_cnt * 8)) & 0xff;
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m_scsi->dma_w(byte_val);
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m_dma[DMA_ADDR]++;
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if ((m_dma[DMA_CTRL] & DMA_EN_CNT) != 0)
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m_dma[DMA_BYTE_COUNT]--;
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m_dma[DMA_BYTE_COUNT]--;
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byte_cnt--;
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}
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}
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}
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if (m_dma[DMA_BYTE_COUNT] == 0)
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{
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m_dma[DMA_CTRL] |= DMA_TC;
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dma_set_int_pend(1);
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m_dma_timer->adjust(attotime::never);
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}
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else
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{
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dma_setup_timer(true);
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if ((m_dma[DMA_ADDR] & 3) == 3)
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word_cached = false;
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}
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}
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void sun4_state::dma_setup_timer(bool continuing)
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void sun4_state::dma_transfer()
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{
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const uint32_t remaining_bytes = m_dma[DMA_BYTE_COUNT];
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const uint64_t latency = (continuing ? 0 : 40);
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const uint64_t transfer_size = (remaining_bytes < PAGE_SIZE ? remaining_bytes : PAGE_SIZE);
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const uint64_t transfer_duration = ((transfer_size + 15) / 16) * 8; // 16 byte groupings, 8 clock cycles per group
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const uint64_t total_ticks = latency + transfer_duration;
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m_dma_timer->adjust(attotime::from_ticks(total_ticks, DMA_XTAL));
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if (!continuing)
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if (m_dma[DMA_CTRL] & DMA_WRITE)
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{
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m_dma[DMA_CTRL] &= DMA_TC;
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dma_transfer_write();
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}
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else
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{
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dma_transfer_read();
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}
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if (m_dma[DMA_BYTE_COUNT] == 0 && (m_dma[DMA_CTRL] & DMA_EN_CNT) != 0)
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{
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m_dma[DMA_CTRL] |= DMA_TC;
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m_dma_tc_read = false;
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dma_check_interrupts();
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}
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}
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READ32_MEMBER( sun4_state::dma_r )
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{
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if (offset == DMA_CTRL && (m_dma[DMA_CTRL] & DMA_TC) != 0)
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{
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m_dma_tc_read = true;
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dma_check_interrupts();
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}
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return m_dma[offset];
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}
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@ -1849,33 +1790,40 @@ WRITE32_MEMBER( sun4_state::dma_w )
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case DMA_CTRL:
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{
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// clear write-only bits
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logerror("dma_w: ctrl: %08x\n", data);
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uint32_t old_ctrl = m_dma[DMA_CTRL];
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m_dma[DMA_CTRL] &= (DMA_READ_ONLY | DMA_READ_WRITE);
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m_dma[DMA_CTRL] &= (DMA_WRITE_ONLY | DMA_READ_WRITE);
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m_dma[DMA_CTRL] |= (data & (DMA_WRITE_ONLY | DMA_READ_WRITE));
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if (data & DMA_FLUSH)
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uint32_t diff = old_ctrl ^ m_dma[DMA_CTRL];
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if (diff & DMA_FLUSH)
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{
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m_dma[DMA_CTRL] &= ~DMA_PACK_CNT;
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m_dma[DMA_CTRL] &= ~DMA_ERR_PEND;
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m_dma[DMA_CTRL] &= ~DMA_TC;
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if (!m_scsi_irq)
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{
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dma_set_int_pend(0);
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}
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dma_check_interrupts();
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}
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if (data & DMA_EN_DMA && !(old_ctrl & DMA_EN_DMA))
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if (diff & DMA_EN_DMA)
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{
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dma_setup_timer(false);
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if ((data & DMA_EN_DMA) != 0 && (m_dma[DMA_CTRL] & DMA_REQ_PEND) != 0)
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{
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dma_transfer();
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}
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}
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break;
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}
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case DMA_ADDR:
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logerror("dma_w: addr: %08x\n", data);
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m_dma[offset] = data;
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break;
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case DMA_BYTE_COUNT:
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logerror("dma_w: byte_count: %08x\n", data);
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m_dma[offset] = data;
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break;
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@ -1886,23 +1834,24 @@ WRITE32_MEMBER( sun4_state::dma_w )
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WRITE_LINE_MEMBER( sun4_state::scsi_irq )
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{
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if (!(m_dma[DMA_CTRL] & DMA_TC))
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{
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dma_set_int_pend(state);
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}
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m_scsi_irq = state;
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dma_check_interrupts();
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}
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WRITE_LINE_MEMBER( sun4_state::scsi_drq )
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{
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logerror("scsi_drq %d\n", state);
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m_dma[DMA_CTRL] &= ~DMA_REQ_PEND;
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if (state)
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{
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logerror("scsi_drq, DMA pending\n");
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m_dma[DMA_CTRL] |= DMA_REQ_PEND;
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if (m_dma[DMA_CTRL] & DMA_EN_DMA)
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{
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dma_setup_timer(false);
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logerror("DMA enabled, starting dma\n");
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dma_transfer();
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}
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}
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m_scsi_drq = state;
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}
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// indicate 4/60 SCSI/DMA/Ethernet card exists
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