diff --git a/src/devices/machine/z80scc.cpp b/src/devices/machine/z80scc.cpp
index 1a90f30b3ae..019275d00ee 100644
--- a/src/devices/machine/z80scc.cpp
+++ b/src/devices/machine/z80scc.cpp
@@ -85,7 +85,9 @@ DONE (x) (p=partly)         NMOS         CMOS       ESCC      EMSCC
 #define LOGSETUP(x) {} LOGPRINT(x)
 #define LOGINT(x)   {} LOGPRINT(x)
 #define LOGTX(x)    {} LOGPRINT(x)
-#define LOGRCV(x)   {}
+#define LOGRCV(x)   {} 
+#define LOGCTS(x)   {} LOGPRINT(x)
+#define LOGDCD(x)   {} LOGPRINT(x)
 #if VERBOSE == 2
 #define logerror printf
 #endif
@@ -821,8 +823,8 @@ z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, d
 		m_rx_break(0),
 		m_rx_rr0_latch(0),
 		m_rxd(0),
-		m_cts(0),
-		m_dcd(0),
+		m_cts(1),
+		m_dcd(1),
 		m_tx_clock(0),
 		m_dtr(0),
 		m_rts(0),
@@ -1319,12 +1321,14 @@ uint8_t z80scc_channel::do_sccreg_rr2()
 	{
 		int i = 0;
 
+		LOGINT((" - Channel B so we might need to update the vector modification\n"));
 		// loop over all interrupt sources
 		for (auto & elem : m_uart->m_int_state)
 		{
 			// find the first channel with an interrupt requested
 			if (elem & Z80_DAISY_INT)
 			{
+				LOGINT((" - Checking an INT source %d\n", i));
 				m_rr2 = m_uart->modify_vector(m_rr2, i < 3 ? z80scc_device::CHANNEL_A : z80scc_device::CHANNEL_B, m_uart->m_int_source[i] & 3);
 				if ((m_uart->m_variant & (SET_ESCC | SET_CMOS)) && (m_uart->m_wr9 & WR9_BIT_IACK))
 				{
@@ -1491,8 +1495,8 @@ uint8_t z80scc_channel::do_sccreg_rr14()
 uint8_t z80scc_channel::do_sccreg_rr15()
 {
 	LOGR(("%s\n", FUNCNAME));
-	logerror("%s() not implemented feature\n", FUNCNAME);
-	return m_wr15 & 0xf5; // Mask out the used bits
+
+	return m_wr15 & 0xfa; // Mask out the used bits
 }
 
 //-------------------------------------------------
@@ -2422,14 +2426,21 @@ WRITE_LINE_MEMBER( z80scc_channel::cts_w )
 	{
 		// enable transmitter if in auto enables mode
 		if (!state)
+		{
+			LOGCTS((" - CTS active\n"));
 			if (m_wr3 & WR3_AUTO_ENABLES)
+			{
+				LOGCTS((" - TX auto enabled\n"));
 				m_wr5 |= WR5_TX_ENABLE;
+			}
+		}
 
 		// set clear to send
 		m_cts = state;
 
 		if (!m_rx_rr0_latch)
 		{
+			LOGCTS((" - RR0 not latched so updating RR0 with CTS state\n"));
 			if (!m_cts)
 				m_rr0 |= RR0_CTS;
 			else
@@ -2444,9 +2455,11 @@ WRITE_LINE_MEMBER( z80scc_channel::cts_w )
 			if ((m_wr1 & WR1_EXT_INT_ENABLE) && (m_wr15 & WR15_CTS))
 			{
 				// trigger interrupt
+				LOGCTS((" - Trigger CTS interrupt\n"));
 				m_uart->trigger_interrupt(m_index, INT_EXTERNAL);
 
 				// latch read register 0
+				LOGCTS((" - Latches RR0\n"));
 				m_rx_rr0_latch = 1;
 			}
 		}
@@ -2465,9 +2478,11 @@ WRITE_LINE_MEMBER( z80scc_channel::dcd_w )
 	{
 		if (!state) 
 		{
+			LOGDCD((" - DCD active\n"));
 			// enable receiver if in auto enables mode
 			if (m_wr3 & WR3_AUTO_ENABLES)
 			{
+				LOGCTS((" - RX auto enabled\n"));
 				m_wr3 |= WR3_RX_ENABLE;
 #if START_BIT_HUNT
 				m_rcv_mode = RCV_SEEKING;
@@ -2485,6 +2500,7 @@ of transitions on the /DCD pin while another External/Status interrupt condition
 reset, this bit merely reports the current, unlatched state of the /DCD pin.*/
 		if (!m_rx_rr0_latch)
 		{
+			LOGDCD((" - RR0 not latched so updating RR0 with DCD state\n"));
 			if (m_dcd)
 				m_rr0 |= RR0_DCD;
 			else
@@ -2500,9 +2516,11 @@ reset, this bit merely reports the current, unlatched state of the /DCD pin.*/
 			if ((m_wr1 & WR1_EXT_INT_ENABLE) && (m_wr15 & WR15_DCD))
 			{
 				// trigger interrupt
+				LOGDCD((" - Trigger DCD interrupt\n"));
 				m_uart->trigger_interrupt(m_index, INT_EXTERNAL);
 
 				// latch read register 0
+				LOGDCD((" - Latches RR0\n"));
 				m_rx_rr0_latch = 1;
 			}
 		}
diff --git a/src/mame/drivers/mac128.cpp b/src/mame/drivers/mac128.cpp
index 1bed0ade61c..cffed939ca2 100755
--- a/src/mame/drivers/mac128.cpp
+++ b/src/mame/drivers/mac128.cpp
@@ -1502,6 +1502,21 @@ ROM_START( utrn1024 )
 	ROM_LOAD16_BYTE( "macplus_mem_l.e7", 0x000001, 0x010000, CRC(fb766270) SHA1(679f529fbfc05f9cc98924c53457d2996dfcb1a7) )
 ROM_END
 
+/*
+ SCC init macplus.rom
+ * Channel B and A init - reset command and vector differs
+ * 09 <- 40/80 Master Interrup Control: channel B/A reset
+ * 04 <- 4c Clocks: x16 mode, 2 stop bits, no parity
+ * 02 <- 00 Interrupt vector (just for chan B)
+ * 03 <- c0 Receiver: 8 bit data, auto enables, Rx disabled
+ * 0f <- 08 External/Status Control: DCD ints enabled
+ * 00 <- 10 Reset External/status interrupts
+ * 00 <- 10 Reset External/status interrupts
+ * 01 <- 01 Enable External Interrupts
+ * Above init first for channel B and then for channel A
+ * 09 <- 0a Master Interrup Control: No vector and Interrupts enabled!
+*/
+
 ROM_START( mac512ke )
 	ROM_REGION16_BE(0x100000, "bootrom", 0)
 	ROM_LOAD16_WORD( "macplus.rom",  0x00000, 0x20000, CRC(b2102e8e) SHA1(7d2f808a045aa3a1b242764f0e2c7d13e288bf1f))