mirror of
https://github.com/holub/mame
synced 2025-04-21 16:01:56 +03:00
i82371sb.cpp: various changes, windows 98 recognizes the ide busmaster controller in pcipc driver
- corrections to pci configuration space maps - remove useless redefinitions of command_w/r in ide device - placeholders for nmi, stpclk and extsmi lines of isa bridge - correctly support 8 bit writes to idetim registers
This commit is contained in:
yz70s
parent
628dc0d363
commit
2bdab107da
@ -12,13 +12,17 @@ DEFINE_DEVICE_TYPE(I82371SB_ISA, i82371sb_isa_device, "i82371sb_isa", "Intel 823
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void i82371sb_isa_device::config_map(address_map &map)
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{
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pci_device::config_map(map);
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map(0x06, 0x07).rw(FUNC(i82371sb_isa_device::status_r), FUNC(i82371sb_isa_device::status_w));
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map(0x10, 0x4b).noprw();
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map(0x4c, 0x4c).rw(FUNC(i82371sb_isa_device::iort_r), FUNC(i82371sb_isa_device::iort_w));
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map(0x4e, 0x4f).rw(FUNC(i82371sb_isa_device::xbcs_r), FUNC(i82371sb_isa_device::xbcs_w));
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map(0x60, 0x63).rw(FUNC(i82371sb_isa_device::pirqrc_r), FUNC(i82371sb_isa_device::pirqrc_w));
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map(0x68, 0x68).rw(FUNC(i82371sb_isa_device::tom_r), FUNC(i82371sb_isa_device::tom_w));
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map(0x69, 0x69).rw(FUNC(i82371sb_isa_device::tom_r), FUNC(i82371sb_isa_device::tom_w));
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map(0x6a, 0x6b).rw(FUNC(i82371sb_isa_device::mstat_r), FUNC(i82371sb_isa_device::mstat_w));
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map(0x70, 0x71).rw(FUNC(i82371sb_isa_device::mbirq01_r), FUNC(i82371sb_isa_device::mbirq01_w));
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map(0x76, 0x77).rw(FUNC(i82371sb_isa_device::mbdma_r), FUNC(i82371sb_isa_device::mbdma_w));
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map(0x78, 0x79).rw(FUNC(i82371sb_isa_device::pcsc_r), FUNC(i82371sb_isa_device::pcsc_w));
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map(0x80, 0x80).rw(FUNC(i82371sb_isa_device::apicbase_r), FUNC(i82371sb_isa_device::apicbase_w));
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map(0x82, 0x82).rw(FUNC(i82371sb_isa_device::dlc_r), FUNC(i82371sb_isa_device::dlc_w));
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map(0xa0, 0xa0).rw(FUNC(i82371sb_isa_device::smicntl_r), FUNC(i82371sb_isa_device::smicntl_w));
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map(0xa2, 0xa3).rw(FUNC(i82371sb_isa_device::smien_r), FUNC(i82371sb_isa_device::smien_w));
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@ -40,6 +44,7 @@ void i82371sb_isa_device::internal_io_map(address_map &map)
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map(0x00b2, 0x00b3).rw(FUNC(i82371sb_isa_device::read_apmcapms), FUNC(i82371sb_isa_device::write_apmcapms));
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map(0x00c0, 0x00df).rw(FUNC(i82371sb_isa_device::at_dma8237_2_r), FUNC(i82371sb_isa_device::at_dma8237_2_w));
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map(0x04d0, 0x04d1).rw(FUNC(i82371sb_isa_device::eisa_irq_read), FUNC(i82371sb_isa_device::eisa_irq_write));
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map(0x0cf9, 0x0cf9).rw(FUNC(i82371sb_isa_device::reset_control_r), FUNC(i82371sb_isa_device::reset_control_w));
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map(0x00e0, 0x00ef).noprw();
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}
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@ -130,6 +135,8 @@ void i82371sb_isa_device::device_add_mconfig(machine_config &config)
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i82371sb_isa_device::i82371sb_isa_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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pci_device(mconfig, I82371SB_ISA, tag, owner, clock),
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m_smi_callback(*this),
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m_nmi_callback(*this),
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m_stpclk_callback(*this),
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m_boot_state_hook(*this),
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m_maincpu(*this, ":maincpu"),
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m_pic8259_master(*this, "pic8259_master"),
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@ -148,6 +155,8 @@ void i82371sb_isa_device::device_start()
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{
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pci_device::device_start();
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m_smi_callback.resolve();
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m_nmi_callback.resolve_safe();
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m_stpclk_callback.resolve_safe();
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m_boot_state_hook.resolve();
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}
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@ -155,6 +164,7 @@ void i82371sb_isa_device::device_reset()
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{
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pci_device::device_reset();
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status = 0x0280;
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iort = 0x4d;
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xbcs = 0x0003;
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memset(pirqrc, 0x80, sizeof(pirqrc));
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@ -175,6 +185,7 @@ void i82371sb_isa_device::device_reset()
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smireq = 0x0000;
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ctlmtr = 0x00;
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cthmtr = 0x00;
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reset_control = 0;
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m_at_spkrdata = 0;
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m_pit_out2 = 1;
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@ -198,6 +209,12 @@ void i82371sb_isa_device::nop_w(uint8_t data)
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{
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}
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void i82371sb_isa_device::status_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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// bits 11-13 are clear on write
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status = status & ~(data & (0x3800 & mem_mask));
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}
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uint8_t i82371sb_isa_device::iort_r()
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{
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return iort;
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@ -286,6 +303,17 @@ void i82371sb_isa_device::mbdma_w(offs_t offset, uint8_t data)
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logerror("mbdma[%d] = %02x\n", offset, mbdma);
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}
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uint16_t i82371sb_isa_device::pcsc_r()
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{
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return pcsc;
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}
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void i82371sb_isa_device::pcsc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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COMBINE_DATA(&pcsc);
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logerror("pcsc = %04x\n", pcsc);
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}
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uint8_t i82371sb_isa_device::apicbase_r()
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{
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return apicbase;
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@ -783,9 +811,15 @@ WRITE_LINE_MEMBER( i82371sb_isa_device::pc_mirq1_w )
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WRITE_LINE_MEMBER( i82371sb_isa_device::pc_ferr_w )
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{
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if (!(xbcs & 32))
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return;
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m_pic8259_slave->ir5_w(state);
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}
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WRITE_LINE_MEMBER(i82371sb_isa_device::pc_extsmi_w)
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{
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}
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WRITE_LINE_MEMBER( i82371sb_isa_device::pc_irq1_w ) { m_pic8259_master->ir1_w(state); }
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WRITE_LINE_MEMBER( i82371sb_isa_device::pc_irq3_w ) { m_pic8259_master->ir3_w(state); }
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WRITE_LINE_MEMBER( i82371sb_isa_device::pc_irq4_w ) { m_pic8259_master->ir4_w(state); }
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@ -878,6 +912,18 @@ void i82371sb_isa_device::write_apmcapms(offs_t offset, uint8_t data)
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}
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else
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apms = data;
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logerror("write apmcapms %d %02x\n", offset, data);
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}
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uint8_t i82371sb_isa_device::reset_control_r(offs_t offset)
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{
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return reset_control;
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}
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void i82371sb_isa_device::reset_control_w(offs_t offset, uint8_t data)
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{
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reset_control = data;
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logerror("reset_control = %02x\n", reset_control);
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}
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void i82371sb_isa_device::update_smireq_line()
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@ -898,8 +944,11 @@ DEFINE_DEVICE_TYPE(I82371SB_IDE, i82371sb_ide_device, "i82371sb_ide", "Intel 823
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void i82371sb_ide_device::config_map(address_map &map)
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{
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pci_device::config_map(map);
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map(0x04, 0x05).rw(FUNC(i82371sb_ide_device::command_r), FUNC(i82371sb_ide_device::command_w));
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map(0x06, 0x07).rw(FUNC(i82371sb_ide_device::status_r), FUNC(i82371sb_ide_device::status_w));
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map(0x0d, 0x0d).rw(FUNC(i82371sb_ide_device::latency_timer_r), FUNC(i82371sb_ide_device::latency_timer_w));
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map(0x10, 0x1f).noprw();
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map(0x20, 0x23).rw(FUNC(i82371sb_ide_device::bmiba_r), FUNC(i82371sb_ide_device::bmiba_w));
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map(0x24, 0x3b).noprw();
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map(0x40, 0x41).rw(FUNC(i82371sb_ide_device::idetim_primary_r), FUNC(i82371sb_ide_device::idetim_primary_w));
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map(0x42, 0x43).rw(FUNC(i82371sb_ide_device::idetim_secondary_r), FUNC(i82371sb_ide_device::idetim_secondary_w));
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map(0x44, 0x44).rw(FUNC(i82371sb_ide_device::sidetim_r), FUNC(i82371sb_ide_device::sidetim_w));
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@ -926,7 +975,7 @@ void i82371sb_ide_device::device_add_mconfig(machine_config &config)
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i82371sb_ide_device::i82371sb_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pci_device(mconfig, I82371SB_IDE, tag, owner, clock)
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, command(2)
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, latency_timer(0)
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, bmiba(1)
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, idetim_primary(0)
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, idetim_secondary(0)
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@ -941,6 +990,10 @@ i82371sb_ide_device::i82371sb_ide_device(const machine_config &mconfig, const ch
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void i82371sb_ide_device::device_start()
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{
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pci_device::device_start();
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status = 0x0280;
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command = 2;
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command_mask = 5;
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m_irq_pri_callback.resolve();
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m_irq_sec_callback.resolve();
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}
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@ -976,17 +1029,22 @@ WRITE_LINE_MEMBER(i82371sb_ide_device::secondary_int)
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m_irq_sec_callback(state);
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}
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uint16_t i82371sb_ide_device::command_r()
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void i82371sb_ide_device::status_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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return command;
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// bits 11-13 are clear on write
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status = status & ~(data & (0x3800 & mem_mask));
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logerror("status = %04x\n", status);
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}
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void i82371sb_ide_device::command_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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uint8_t i82371sb_ide_device::latency_timer_r()
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{
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mem_mask &= 5;
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COMBINE_DATA(&command);
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if (mem_mask & 1)
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remap_cb();
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return latency_timer;
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}
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void i82371sb_ide_device::latency_timer_w(uint8_t data)
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{
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latency_timer = data;
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logerror("latency_timer = %02x\n", latency_timer);
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}
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uint32_t i82371sb_ide_device::bmiba_r()
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@ -998,6 +1056,7 @@ void i82371sb_ide_device::bmiba_w(offs_t offset, uint32_t data, uint32_t mem_mas
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{
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mem_mask &= 0xfff0;
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COMBINE_DATA(&bmiba);
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logerror("bmiba = %04x\n", bmiba);
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if (command & 1)
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remap_cb();
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}
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@ -1007,8 +1066,10 @@ uint16_t i82371sb_ide_device::idetim_primary_r()
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return idetim_primary;
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}
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void i82371sb_ide_device::idetim_primary_w(uint16_t data)
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void i82371sb_ide_device::idetim_primary_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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COMBINE_DATA(&idetim_primary);
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logerror("idetim_primary = %04x\n", idetim_primary);
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}
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uint16_t i82371sb_ide_device::idetim_secondary_r()
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@ -1016,8 +1077,10 @@ uint16_t i82371sb_ide_device::idetim_secondary_r()
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return idetim_secondary;
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}
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void i82371sb_ide_device::idetim_secondary_w(uint16_t data)
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void i82371sb_ide_device::idetim_secondary_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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COMBINE_DATA(&idetim_secondary);
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logerror("idetim_secondary = %04x\n", idetim_secondary);
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}
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uint8_t i82371sb_ide_device::sidetim_r()
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@ -1027,6 +1090,8 @@ uint8_t i82371sb_ide_device::sidetim_r()
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void i82371sb_ide_device::sidetim_w(uint8_t data)
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{
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sidetim = data;
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logerror("sidetim = %02x\n", sidetim);
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}
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uint32_t i82371sb_ide_device::ide1_read32_cs0_r(offs_t offset, uint32_t mem_mask)
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@ -29,6 +29,8 @@ public:
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i82371sb_isa_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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auto smi() { return m_smi_callback.bind(); }
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auto nmi() { return m_nmi_callback.bind(); }
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auto stpclk() { return m_stpclk_callback.bind(); }
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auto boot_state_hook() { return m_boot_state_hook.bind(); }
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DECLARE_WRITE_LINE_MEMBER(pc_pirqa_w);
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@ -38,6 +40,7 @@ public:
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DECLARE_WRITE_LINE_MEMBER(pc_mirq0_w);
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DECLARE_WRITE_LINE_MEMBER(pc_mirq1_w);
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DECLARE_WRITE_LINE_MEMBER(pc_ferr_w);
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DECLARE_WRITE_LINE_MEMBER(pc_extsmi_w);
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DECLARE_WRITE_LINE_MEMBER(pc_irq1_w);
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DECLARE_WRITE_LINE_MEMBER(pc_irq3_w);
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@ -106,6 +109,7 @@ private:
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void boot_state_w(uint8_t data);
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void nop_w(uint8_t data);
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void status_w(offs_t offset, uint16_t data, uint16_t mem_mask);
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uint8_t iort_r();
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void iort_w(uint8_t data);
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uint16_t xbcs_r();
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@ -120,6 +124,8 @@ private:
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void mbirq01_w(offs_t offset, uint8_t data);
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uint8_t mbdma_r(offs_t offset);
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void mbdma_w(offs_t offset, uint8_t data);
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uint16_t pcsc_r();
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void pcsc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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uint8_t apicbase_r();
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void apicbase_w(uint8_t data);
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uint8_t dlc_r();
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@ -151,10 +157,14 @@ private:
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void eisa_irq_write(offs_t offset, uint8_t data);
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uint8_t read_apmcapms(offs_t offset);
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void write_apmcapms(offs_t offset, uint8_t data);
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uint8_t reset_control_r(offs_t offset);
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void reset_control_w(offs_t offset, uint8_t data);
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void update_smireq_line();
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devcb_write_line m_smi_callback;
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devcb_write_line m_nmi_callback;
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devcb_write_line m_stpclk_callback;
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devcb_write8 m_boot_state_hook;
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uint32_t see;
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@ -162,6 +172,7 @@ private:
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uint8_t apmc, apms;
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uint8_t iort, pirqrc[4], tom, mbirq0, mbirq1, mbdma[2], apicbase;
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uint8_t dlc, smicntl, ftmr, ctlmtr, cthmtr;
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uint8_t reset_control;
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void map_bios(address_space *memory_space, uint32_t start, uint32_t end);
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@ -220,14 +231,15 @@ protected:
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DECLARE_WRITE_LINE_MEMBER(secondary_int);
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private:
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uint16_t command_r();
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void command_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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void status_w(offs_t offset, uint16_t data, uint16_t mem_mask);
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virtual uint8_t latency_timer_r() override;
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void latency_timer_w(uint8_t data);
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uint32_t bmiba_r();
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void bmiba_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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uint16_t idetim_primary_r();
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void idetim_primary_w(uint16_t data);
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void idetim_primary_w(offs_t offset, uint16_t data, uint16_t mem_mask);
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uint16_t idetim_secondary_r();
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void idetim_secondary_w(uint16_t data);
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void idetim_secondary_w(offs_t offset, uint16_t data, uint16_t mem_mask);
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uint8_t sidetim_r();
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void sidetim_w(uint8_t data);
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@ -242,7 +254,7 @@ private:
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void internal_io_map(address_map &map);
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uint16_t command;
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uint8_t latency_timer;
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uint32_t bmiba;
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int idetim_primary, idetim_secondary;
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int sidetim;
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