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adsp2100: Code cleanup

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- Use BIT helpers for unpacking and disassembling opcodes
- Use count_leading_zeros_32 for "detect exponent" operations rather than shift loops
- Convert comments to C++ single line style
- Convert some constant macros to unscoped enums
- Deobfuscate bit manipulation in the "mode control" instruction
This commit is contained in:
AJR 2023-08-31 14:14:20 -04:00
parent da8dba05ba
commit 2c8ff802b2
5 changed files with 774 additions and 799 deletions
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292
src/devices/cpu/adsp2100/2100dasm.cpp
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@ -180,24 +180,24 @@ const char *const adsp21xx_disassembler::constants[] =
};
void adsp21xx_disassembler::alumac(std::ostream &stream, int dest, int op)
void adsp21xx_disassembler::alumac(std::ostream &stream, int dest, uint32_t op)
{
int opindex = (op >> 13) & 31;
int opindex = BIT(op, 13, 5);
const char *xop, *yop, *dst, *opstring;
if (opindex & 16)
if (BIT(opindex, 4))
{
xop = alu_xop[(op >> 8) & 7];
yop = alu_yop[(op >> 11) & 3];
xop = alu_xop[BIT(op, 8, 3)];
yop = alu_yop[BIT(op, 11, 2)];
dst = alu_dst[dest];
}
else
{
xop = mac_xop[(op >> 8) & 7];
yop = mac_yop[(op >> 11) & 3];
xop = mac_xop[BIT(op, 8, 3)];
yop = mac_yop[BIT(op, 11, 2)];
dst = mac_dst[dest];
}
opstring = alumac_op[opindex][((op >> 11) & 3) == 3];
opstring = alumac_op[opindex][BIT(op, 11, 2) == 3];
if (opstring[0] == '!')
util::stream_format(stream, opstring + 1, dst, yop, xop);
else
@ -205,24 +205,24 @@ void adsp21xx_disassembler::alumac(std::ostream &stream, int dest, int op)
}
void adsp21xx_disassembler::aluconst(std::ostream &stream, int dest, int op)
void adsp21xx_disassembler::aluconst(std::ostream &stream, int dest, uint32_t op)
{
int opindex = (op >> 13) & 31;
int opindex = BIT(op, 13, 5);
const char *xop, *dst, *cval, *opstring;
if (opindex & 16)
if (BIT(opindex, 4))
{
xop = alu_xop[(op >> 8) & 7];
cval = constants[((op >> 5) & 0x07) | ((op >> 8) & 0x18)];
xop = alu_xop[BIT(op, 8, 3)];
cval = constants[BIT(op, 5, 3) | BIT(op, 11, 2) << 3];
dst = alu_dst[dest];
}
else
{
xop = mac_xop[(op >> 8) & 7];
xop = mac_xop[BIT(op, 8, 3)];
cval = xop;
dst = mac_dst[dest];
}
opstring = alumac_op[opindex][((op >> 11) & 3) == 3];
opstring = alumac_op[opindex][BIT(op, 11, 2) == 3];
if (opstring[0] == '!')
util::stream_format(stream, opstring + 1, dst, cval, xop);
else
@ -232,50 +232,50 @@ void adsp21xx_disassembler::aluconst(std::ostream &stream, int dest, int op)
offs_t adsp21xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
{
unsigned int op = opcodes.r32(pc);
uint32_t op = opcodes.r32(pc);
unsigned dasmflags = 0;
int temp;
switch ((op >> 16) & 0xff)
switch (BIT(op, 16, 8))
{
case 0x00:
/* 00000000 00000000 00000000 NOP */
// 00000000 00000000 00000000 NOP
stream << "NOP";
break;
case 0x01:
/* 00000000 0xxxxxxx xxxxxxxx dst = IO(x) */
/* 00000000 1xxxxxxx xxxxxxxx IO(x) = dst */
/* ADSP-218x only */
if ((op & 0x008000) == 0x000000)
util::stream_format(stream, "%s = IO($%X)", reg_grp[0][op & 15], (op >> 4) & 0x7ff);
// 00000000 0xxxxxxx xxxxxxxx dst = IO(x)
// 00000000 1xxxxxxx xxxxxxxx IO(x) = dst
// ADSP-218x only
if (!BIT(op, 15))
util::stream_format(stream, "%s = IO($%X)", reg_grp[0][BIT(op, 0, 4)], BIT(op, 4, 11));
else
util::stream_format(stream, "IO($%X) = %s", (op >> 4) & 0x7ff, reg_grp[0][op & 15]);
util::stream_format(stream, "IO($%X) = %s", BIT(op, 4, 11), reg_grp[0][BIT(op, 0, 4)]);
break;
case 0x02:
/* 00000010 0000xxxx xxxxxxxx modify flag out */
if ((op & 0x00f000) == 0x000000)
// 00000010 0000xxxx xxxxxxxx modify flag out
if (BIT(op, 12, 4) == 0)
{
util::stream_format(stream, "%s", condition[op & 15]);
util::stream_format(stream, flag_change[(op >> 4) & 3], "FLAG_OUT");
util::stream_format(stream, flag_change[(op >> 6) & 3], "FL0");
util::stream_format(stream, flag_change[(op >> 8) & 3], "FL1");
util::stream_format(stream, flag_change[(op >> 10) & 3], "FL2");
util::stream_format(stream, "%s", condition[BIT(op, 0, 4)]);
util::stream_format(stream, flag_change[BIT(op, 4, 2)], "FLAG_OUT");
util::stream_format(stream, flag_change[BIT(op, 6, 2)], "FL0");
util::stream_format(stream, flag_change[BIT(op, 8, 2)], "FL1");
util::stream_format(stream, flag_change[BIT(op, 10, 2)], "FL2");
}
/* 00000010 10000000 00000000 idle */
/* 00000010 10000000 0000xxxx idle (n) */
else if ((op & 0x00fff0) == 0x008000)
// 00000010 10000000 00000000 idle
// 00000010 10000000 0000xxxx idle (n)
else if (BIT(op, 4, 12) == 0x800)
{
}
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x03:
/* 00000011 xxxxxxxx xxxxxxxx call or jump on flag in */
if (op & 2)
// 00000011 xxxxxxxx xxxxxxxx call or jump on flag in
if (BIT(op, 1))
util::stream_format(stream, "%s", "IF FLAG_IN ");
else
util::stream_format(stream, "%s", "IF NOT FLAG_IN ");
if (op & 1)
if (BIT(op, 0))
{
util::stream_format(stream, "%s", "CALL ");
dasmflags = STEP_OVER | STEP_COND;
@ -285,256 +285,256 @@ offs_t adsp21xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const
util::stream_format(stream, "%s", "JUMP ");
dasmflags = STEP_COND;
}
temp = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000);
temp = BIT(op, 4, 12) | BIT(op, 2, 2) << 12;
util::stream_format(stream, "$%04X", temp);
break;
case 0x04:
/* 00000100 00000000 000xxxxx stack control */
if ((op & 0x00ffe0) == 0x000000)
// 00000100 00000000 000xxxxx stack control
if (BIT(op, 5, 11) == 0)
{
if (op & 0x000010)
if (BIT(op, 4))
{
util::stream_format(stream, "%s", "POP PC ");
dasmflags = STEP_OUT;
}
if (op & 0x000008) util::stream_format(stream, "%s", "POP LOOP ");
if (op & 0x000004) util::stream_format(stream, "%s", "POP CNTR ");
if ((op & 0x000003) == 0x000002) util::stream_format(stream, "%s", "PUSH STAT ");
else if ((op & 0x000003) == 0x000003) util::stream_format(stream, "%s", "POP STAT ");
if (BIT(op, 3)) util::stream_format(stream, "%s", "POP LOOP ");
if (BIT(op, 2)) util::stream_format(stream, "%s", "POP CNTR ");
if (BIT(op, 0, 2) == 2) util::stream_format(stream, "%s", "PUSH STAT ");
else if (BIT(op, 0, 2) == 3) util::stream_format(stream, "%s", "POP STAT ");
}
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x05:
/* 00000101 00000000 00000000 saturate MR */
if ((op & 0x00ffff) == 0x000000)
// 00000101 00000000 00000000 saturate MR
if (BIT(op, 0, 16) == 0)
util::stream_format(stream, "%s", "IF MV SAT MR");
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x06:
/* 00000110 000xxxxx 00000000 DIVS */
// 00000110 000xxxxx 00000000 DIVS
if ((op & 0x00e0ff) == 0x000000)
util::stream_format(stream, "DIVS %s,%s", alu_yop[(op >> 11) & 3], alu_xop[(op >> 8) & 7]);
util::stream_format(stream, "DIVS %s,%s", alu_yop[BIT(op, 11, 2)], alu_xop[BIT(op, 8, 3)]);
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x07:
/* 00000111 00010xxx 00000000 DIVQ */
// 00000111 00010xxx 00000000 DIVQ
if ((op & 0x00f8ff) == 0x001000)
util::stream_format(stream, "DIVQ %s", alu_xop[(op >> 8) & 7]);
util::stream_format(stream, "DIVQ %s", alu_xop[BIT(op, 8, 3)]);
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x08:
/* 00001000 00000000 0000xxxx reserved */
// 00001000 00000000 0000xxxx reserved
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x09:
/* 00001001 00000000 000xxxxx modify address register */
if ((op & 0x00ffe0) == 0x000000)
// 00001001 00000000 000xxxxx modify address register
if (BIT(op, 5, 11) == 0)
{
temp = (op >> 2) & 4;
util::stream_format(stream, "MODIFY (I%d,M%d)", temp + ((op >> 2) & 3), temp + (op & 3));
temp = BIT(op, 2, 3);
util::stream_format(stream, "MODIFY (I%d,M%d)", temp, (temp & 4) + BIT(op, 0, 2));
}
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x0a:
/* 00001010 00000000 0000xxxx conditional return */
if ((op & 0x00ffe0) == 0x000000)
// 00001010 00000000 000xxxxx conditional return
if (BIT(op, 5, 11) == 0)
{
util::stream_format(stream, "%s", condition[op & 15]);
if (op & 0x000010)
util::stream_format(stream, "%s", condition[BIT(op, 0, 4)]);
if (BIT(op, 4))
util::stream_format(stream, "%s", "RTI");
else
util::stream_format(stream, "%s", "RTS");
dasmflags = STEP_OUT;
if ((op & 15) != 15)
if (BIT(op, 0, 4) != 15)
dasmflags |= STEP_COND;
}
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x0b:
/* 00001011 00000000 xx00xxxx conditional jump (indirect address) */
if ((op & 0x00ff00) == 0x000000)
// 00001011 00000000 xx00xxxx conditional jump (indirect address)
if (BIT(op, 8, 8) == 0)
{
util::stream_format(stream, "%s", condition[op & 15]);
if (op & 0x000010)
util::stream_format(stream, "%s", condition[BIT(op, 0, 4)]);
if (BIT(op, 4))
{
util::stream_format(stream, "CALL (I%d)", 4 + ((op >> 6) & 3));
util::stream_format(stream, "CALL (I%d)", 4 + BIT(op, 6, 2));
dasmflags = STEP_OVER;
}
else
util::stream_format(stream, "JUMP (I%d)", 4 + ((op >> 6) & 3));
if ((op & 15) != 15)
util::stream_format(stream, "JUMP (I%d)", 4 + BIT(op, 6, 2));
if (BIT(op, 0, 4) != 15)
dasmflags |= STEP_COND;
}
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x0c:
/* 00001100 xxxxxxxx xxxxxxxx mode control */
util::stream_format(stream, mode_change[(op >> 4) & 3], "SEC_REG");
util::stream_format(stream, mode_change[(op >> 6) & 3], "BIT_REV");
util::stream_format(stream, mode_change[(op >> 8) & 3], "AV_LATCH");
util::stream_format(stream, mode_change[(op >> 10) & 3], "AR_SAT");
util::stream_format(stream, mode_change[(op >> 12) & 3], "M_MODE");
util::stream_format(stream, mode_change[(op >> 14) & 3], "TIMER");
util::stream_format(stream, mode_change[(op >> 2) & 3], "G_MODE");
// 00001100 xxxxxxxx xxxxxxxx mode control
util::stream_format(stream, mode_change[BIT(op, 4, 2)], "SEC_REG");
util::stream_format(stream, mode_change[BIT(op, 6, 2)], "BIT_REV");
util::stream_format(stream, mode_change[BIT(op, 8, 2)], "AV_LATCH");
util::stream_format(stream, mode_change[BIT(op, 10, 2)], "AR_SAT");
util::stream_format(stream, mode_change[BIT(op, 12, 2)], "M_MODE");
util::stream_format(stream, mode_change[BIT(op, 14, 2)], "TIMER");
util::stream_format(stream, mode_change[BIT(op, 2, 2)], "G_MODE");
break;
case 0x0d:
/* 00001101 0000xxxx xxxxxxxx internal data move */
if ((op & 0x00f000) == 0x000000)
util::stream_format(stream, "%s = %s", reg_grp[(op >> 10) & 3][(op >> 4) & 15], reg_grp[(op >> 8) & 3][op & 15]);
// 00001101 0000xxxx xxxxxxxx internal data move
if (BIT(op, 12, 4) == 0)
util::stream_format(stream, "%s = %s", reg_grp[BIT(op, 10, 2)][BIT(op, 4, 4)], reg_grp[BIT(op, 8, 3)][BIT(op, 0, 4)]);
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x0e:
/* 00001110 0xxxxxxx xxxxxxxx conditional shift */
// 00001110 0xxxxxxx xxxxxxxx conditional shift
if ((op & 0x0080f0) == 0x000000)
{
util::stream_format(stream, "%s", condition[op & 15]);
util::stream_format(stream, shift_op[(op >> 11) & 15], shift_xop[(op >> 8) & 7]);
util::stream_format(stream, "%s", condition[BIT(op, 0, 4)]);
util::stream_format(stream, shift_op[BIT(op, 11, 4)], shift_xop[BIT(op, 8, 3)]);
}
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x0f:
/* 00001111 0xxxxxxx xxxxxxxx shift immediate */
if ((op & 0x008000) == 0x000000)
util::stream_format(stream, shift_by_op[(op >> 11) & 15], shift_xop[(op >> 8) & 7], (signed char)op);
// 00001111 0xxxxxxx xxxxxxxx shift immediate
if (!BIT(op, 15))
util::stream_format(stream, shift_by_op[BIT(op, 11, 4)], shift_xop[BIT(op, 8, 3)], (signed char)op);
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x10:
/* 00010000 0xxxxxxx xxxxxxxx shift with internal data register move */
if ((op & 0x008000) == 0x000000)
// 00010000 0xxxxxxx xxxxxxxx shift with internal data register move
if (!BIT(op, 15))
{
util::stream_format(stream, shift_op[(op >> 11) & 15], shift_xop[(op >> 8) & 7]);
util::stream_format(stream, ", %s = %s", reg_grp[0][(op >> 4) & 15], reg_grp[0][op & 15]);
util::stream_format(stream, shift_op[BIT(op, 11, 4)], shift_xop[BIT(op, 8, 3)]);
util::stream_format(stream, ", %s = %s", reg_grp[0][BIT(op, 4, 4)], reg_grp[0][BIT(op, 0, 4)]);
}
else
util::stream_format(stream, "??? (%06X)", op);
break;
case 0x11:
/* 00010001 0xxxxxxx xxxxxxxx shift with pgm memory read/write */
util::stream_format(stream, shift_op[(op >> 11) & 15], shift_xop[(op >> 8) & 7]);
if (op & 0x008000)
util::stream_format(stream, ", PM(I%d,M%d) = %s", 4 + ((op >> 2) & 3), 4 + (op & 3), reg_grp[0][(op >> 4) & 15]);
// 00010001 0xxxxxxx xxxxxxxx shift with pgm memory read/write
util::stream_format(stream, shift_op[BIT(op, 11, 4)], shift_xop[BIT(op, 8, 3)]);
if (BIT(op, 15))
util::stream_format(stream, ", PM(I%d,M%d) = %s", 4 + BIT(op, 2, 2), 4 + BIT(op, 0, 2), reg_grp[0][BIT(op, 4, 4)]);
else
util::stream_format(stream, ", %s = PM(I%d,M%d)", reg_grp[0][(op >> 4) & 15], 4 + ((op >> 2) & 3), 4 + (op & 3));
util::stream_format(stream, ", %s = PM(I%d,M%d)", reg_grp[0][BIT(op, 4, 4)], 4 + BIT(op, 2, 2), 4 + BIT(op, 0, 2));
break;
case 0x12: case 0x13:
/* 0001001x 0xxxxxxx xxxxxxxx shift with data memory read/write */
util::stream_format(stream, shift_op[(op >> 11) & 15], shift_xop[(op >> 8) & 7]);
temp = (op >> 14) & 4;
if (op & 0x008000)
util::stream_format(stream, ", DM(I%d,M%d) = %s", temp + ((op >> 2) & 3), temp + (op & 3), reg_grp[0][(op >> 4) & 15]);
// 0001001x 0xxxxxxx xxxxxxxx shift with data memory read/write
util::stream_format(stream, shift_op[BIT(op, 11, 4)], shift_xop[BIT(op, 8, 3)]);
temp = BIT(op, 16) ? 4 : 0;
if (BIT(op, 15))
util::stream_format(stream, ", DM(I%d,M%d) = %s", temp + BIT(op, 2, 2), temp + BIT(op, 0, 2), reg_grp[0][BIT(op, 4, 4)]);
else
util::stream_format(stream, ", %s = DM(I%d,M%d)", reg_grp[0][(op >> 4) & 15], temp + ((op >> 2) & 3), temp + (op & 3));
util::stream_format(stream, ", %s = DM(I%d,M%d)", reg_grp[0][BIT(op, 4, 4)], temp + BIT(op, 2, 2), temp + BIT(op, 0, 2));
break;
case 0x14: case 0x15: case 0x16: case 0x17:
/* 000101xx xxxxxxxx xxxxxxxx do until */
util::stream_format(stream, "DO $%04X UNTIL %s", (op >> 4) & 0x3fff, do_condition[op & 15]);
// 000101xx xxxxxxxx xxxxxxxx do until
util::stream_format(stream, "DO $%04X UNTIL %s", BIT(op, 4, 14), do_condition[BIT(op, 0, 4)]);
break;
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
/* 00011xxx xxxxxxxx xxxxxxxx conditional jump (immediate addr) */
if (op & 0x040000)
// 00011xxx xxxxxxxx xxxxxxxx conditional jump (immediate addr)
if (BIT(op, 18))
{
util::stream_format(stream, "%sCALL $%04X", condition[op & 15], (op >> 4) & 0x3fff);
util::stream_format(stream, "%sCALL $%04X", condition[BIT(op, 0, 4)], BIT(op, 4, 14));
dasmflags = STEP_OVER;
}
else
util::stream_format(stream, "%sJUMP $%04X", condition[op & 15], (op >> 4) & 0x3fff);
if ((op & 15) != 15)
util::stream_format(stream, "%sJUMP $%04X", condition[BIT(op, 0, 4)], BIT(op, 4, 14));
if (BIT(op, 0, 4) != 15)
dasmflags |= STEP_COND;
break;
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
/* 00100xxx xxxxxxxx xxxxxxxx conditional ALU/MAC */
util::stream_format(stream, "%s", condition[op & 15]);
if (!(op & 0x10))
alumac(stream, (op >> 18) & 1, op);
// 00100xxx xxxxxxxx xxxxxxxx conditional ALU/MAC
util::stream_format(stream, "%s", condition[BIT(op, 0, 4)]);
if (!BIT(op, 4))
alumac(stream, BIT(op, 18), op);
else
{
/* ADSP-218x only */
aluconst(stream, (op >> 18) & 1, op);
// ADSP-218x only
aluconst(stream, BIT(op, 18), op);
}
break;
case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
/* 00101xxx xxxxxxxx xxxxxxxx ALU/MAC with internal data register move */
// 00101xxx xxxxxxxx xxxxxxxx ALU/MAC with internal data register move
if ((op & 0x0600ff) == 0x0200aa)
{
/* ADSP-218x only */
// ADSP-218x only
alumac(stream, 2, op);
}
else
{
if ((op & 0x03e000) != 0)
if (BIT(op, 13, 5) != 0)
{
alumac(stream, (op >> 18) & 1, op);
alumac(stream, BIT(op, 18), op);
util::stream_format(stream, ", ");
}
util::stream_format(stream, "%s = %s", reg_grp[0][(op >> 4) & 15], reg_grp[0][op & 15]);
util::stream_format(stream, "%s = %s", reg_grp[0][BIT(op, 4, 4)], reg_grp[0][BIT(op, 0, 4)]);
}
break;
case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
/* 0011xxxx xxxxxxxx xxxxxxxx load non-data register immediate */
util::stream_format(stream, "%s = $%04X", reg_grp[(op >> 18) & 3][op & 15], (op >> 4) & 0x3fff);
// 0011xxxx xxxxxxxx xxxxxxxx load non-data register immediate
util::stream_format(stream, "%s = $%04X", reg_grp[BIT(op, 18, 2)][BIT(op, 0, 4)], BIT(op, 4, 14));
break;
case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
/* 0100xxxx xxxxxxxx xxxxxxxx load data register immediate */
util::stream_format(stream, "%s = $%04X", reg_grp[0][op & 15], (op >> 4) & 0xffff);
// 0100xxxx xxxxxxxx xxxxxxxx load data register immediate
util::stream_format(stream, "%s = $%04X", reg_grp[0][BIT(op, 0, 4)], BIT(op, 4, 14));
break;
case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
/* 0101xxxx xxxxxxxx xxxxxxxx ALU/MAC with pgm memory read/write */
if ((op & 0x03e000) != 0)
// 0101xxxx xxxxxxxx xxxxxxxx ALU/MAC with pgm memory read/write
if (BIT(op, 13, 5) != 0)
{
alumac(stream, (op >> 18) & 1, op);
alumac(stream, BIT(op, 18), op);
util::stream_format(stream, ", ");
}
if (op & 0x080000)
util::stream_format(stream, "PM(I%d,M%d) = %s", 4 + ((op >> 2) & 3), 4 + (op & 3), reg_grp[0][(op >> 4) & 15]);
if (BIT(op, 19))
util::stream_format(stream, "PM(I%d,M%d) = %s", 4 + BIT(op, 2, 2), 4 + BIT(op, 0, 2), reg_grp[0][BIT(op, 4, 4)]);
else
util::stream_format(stream, "%s = PM(I%d,M%d)", reg_grp[0][(op >> 4) & 15], 4 + ((op >> 2) & 3), 4 + (op & 3));
util::stream_format(stream, "%s = PM(I%d,M%d)", reg_grp[0][BIT(op, 4, 4)], 4 + BIT(op, 2, 2), 4 + BIT(op, 0, 2));
break;
case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
/* 011xxxxx xxxxxxxx xxxxxxxx ALU/MAC with data memory read/write */
if ((op & 0x03e000) != 0)
// 011xxxxx xxxxxxxx xxxxxxxx ALU/MAC with data memory read/write
if (BIT(op, 13, 5) != 0)
{
alumac(stream, (op >> 18) & 1, op);
alumac(stream, BIT(op, 18), op);
util::stream_format(stream, ", ");
}
temp = (op >> 18) & 4;
if (op & 0x080000)
util::stream_format(stream, "DM(I%d,M%d) = %s", temp + ((op >> 2) & 3), temp + (op & 3), reg_grp[0][(op >> 4) & 15]);
temp = BIT(op, 20) ? 4 : 0;
if (BIT(op, 19))
util::stream_format(stream, "DM(I%d,M%d) = %s", temp + BIT(op, 2, 2), temp + BIT(op, 0, 2), reg_grp[0][BIT(op, 4, 4)]);
else
util::stream_format(stream, "%s = DM(I%d,M%d)", reg_grp[0][(op >> 4) & 15], temp + ((op >> 2) & 3), temp + (op & 3));
util::stream_format(stream, "%s = DM(I%d,M%d)", reg_grp[0][BIT(op, 4, 4)], temp + BIT(op, 2, 2), temp + BIT(op, 0, 2));
break;
case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
/* 100xxxxx xxxxxxxx xxxxxxxx read/write data memory (immediate addr) */
if (op & 0x100000)
util::stream_format(stream, "DM($%04X) = %s", (op >> 4) & 0x3fff, reg_grp[(op >> 18) & 3][op & 15]);
// 100xxxxx xxxxxxxx xxxxxxxx read/write data memory (immediate addr)
if (BIT(op, 20))
util::stream_format(stream, "DM($%04X) = %s", BIT(op, 4, 14), reg_grp[BIT(op, 18, 2)][BIT(op, 0, 4)]);
else
util::stream_format(stream, "%s = DM($%04X)", reg_grp[(op >> 18) & 3][op & 15], (op >> 4) & 0x3fff);
util::stream_format(stream, "%s = DM($%04X)", reg_grp[BIT(op, 18, 2)][BIT(op, 0, 4)], BIT(op, 4, 14));
break;
case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
/* 101xxxxx xxxxxxxx xxxxxxxx data memory write (immediate) */
temp = (op >> 18) & 4;
util::stream_format(stream, "DM(I%d,M%d) = $%04X", temp + ((op >> 2) & 3), temp + (op & 3), (op >> 4) & 0xffff);
// 101xxxxx xxxxxxxx xxxxxxxx data memory write (immediate)
temp = BIT(op, 20) ? 4 : 0;
util::stream_format(stream, "DM(I%d,M%d) = $%04X", temp + BIT(op, 2, 2), temp + BIT(op, 0, 2), BIT(op, 4, 16));
break;
case 0xc0: case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf:
@ -544,14 +544,14 @@ offs_t adsp21xx_disassembler::disassemble(std::ostream &stream, offs_t pc, const
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
/* 11xxxxxx xxxxxxxx xxxxxxxx ALU/MAC with data & pgm memory read */
if ((op & 0x03e000) != 0)
// 11xxxxxx xxxxxxxx xxxxxxxx ALU/MAC with data & pgm memory read
if (BIT(op, 13, 5) != 0)
{
alumac(stream, 0, op);
util::stream_format(stream, ", ");
}
util::stream_format(stream, "%s = DM(I%d,M%d), %s = PM(I%d,M%d)", dual_xreg[(op >> 18) & 3], (op >> 2) & 3, op & 3,
dual_yreg[(op >> 20) & 3], 4 + ((op >> 6) & 3), 4 + ((op >> 4) & 3));
util::stream_format(stream, "%s = DM(I%d,M%d), %s = PM(I%d,M%d)", dual_xreg[BIT(op, 18, 2)], BIT(op, 2, 2), BIT(op, 0, 2),
dual_yreg[BIT(op, 20, 2)], 4 + BIT(op, 6, 2), 4 + BIT(op, 4, 2));
break;
}

4
src/devices/cpu/adsp2100/2100dasm.h
View File

@ -35,8 +35,8 @@ private:
static const char *const shift_by_op[];
static const char *const constants[];
void alumac(std::ostream &stream, int dest, int op);
void aluconst(std::ostream &stream, int dest, int op);
void alumac(std::ostream &stream, int dest, uint32_t op);
void aluconst(std::ostream &stream, int dest, uint32_t op);
};

989
src/devices/cpu/adsp2100/2100ops.hxx
View File

File diff suppressed because it is too large Load Diff

266
src/devices/cpu/adsp2100/adsp2100.cpp
View File

@ -1241,7 +1241,7 @@ void adsp21xx_device::execute_run()
// parse the instruction
uint32_t temp;
switch ((op >> 16) & 0xff)
switch (BIT(op, 16, 8))
{
case 0x00:
// 00000000 00000000 00000000 NOP
@ -1252,68 +1252,56 @@ void adsp21xx_device::execute_run()
// ADSP-218x only
if (m_chip_type >= CHIP_TYPE_ADSP2181)
{
if ((op & 0x008000) == 0x000000)
write_reg0(op & 15, io_read((op >> 4) & 0x7ff));
if (!BIT(op, 15))
write_reg0(BIT(op, 0, 4), io_read(BIT(op, 4, 11)));
else
io_write((op >> 4) & 0x7ff, read_reg0(op & 15));
io_write(BIT(op, 4, 11), read_reg0(BIT(op, 0, 4)));
}
break;
case 0x02:
// 00000010 0000xxxx xxxxxxxx modify flag out
// 00000010 10000000 00000000 idle
// 00000010 10000000 0000xxxx idle (n)
if (op & 0x008000)
if (BIT(op, 15))
{
m_idle = 1;
m_icount = 0;
}
else
{
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
if (op & 0x020) m_flagout = 0;
if (op & 0x010) m_flagout ^= 1;
if (BIT(op, 5)) m_flagout = 0;
if (BIT(op, 4)) m_flagout ^= 1;
if (m_chip_type >= CHIP_TYPE_ADSP2101)
{
if (op & 0x080) m_fl0 = 0;
if (op & 0x040) m_fl0 ^= 1;
if (op & 0x200) m_fl1 = 0;
if (op & 0x100) m_fl1 ^= 1;
if (op & 0x800) m_fl2 = 0;
if (op & 0x400) m_fl2 ^= 1;
if (BIT(op, 7)) m_fl0 = 0;
if (BIT(op, 6)) m_fl0 ^= 1;
if (BIT(op, 9)) m_fl1 = 0;
if (BIT(op, 8)) m_fl1 ^= 1;
if (BIT(op, 11)) m_fl2 = 0;
if (BIT(op, 10)) m_fl2 ^= 1;
}
}
}
break;
case 0x03:
// 00000011 xxxxxxxx xxxxxxxx call or jump on flag in
if (op & 0x000002)
if (BIT(op, 1) ? m_flagin : !m_flagin)
{
if (m_flagin)
{
if (op & 0x000001)
pc_stack_push();
m_pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000);
}
}
else
{
if (!m_flagin)
{
if (op & 0x000001)
pc_stack_push();
m_pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000);
}
if (BIT(op, 0))
pc_stack_push();
m_pc = BIT(op, 4, 12) | BIT(op, 2, 2) << 12;
}
break;
case 0x04:
// 00000100 00000000 000xxxxx stack control
if (op & 0x000010) pc_stack_pop_val();
if (op & 0x000008) loop_stack_pop();
if (op & 0x000004) cntr_stack_pop();
if (op & 0x000002)
if (BIT(op, 4)) pc_stack_pop_val();
if (BIT(op, 3)) loop_stack_pop();
if (BIT(op, 2)) cntr_stack_pop();
if (BIT(op, 1))
{
if (op & 0x000001) stat_stack_pop();
if (BIT(op, 0)) stat_stack_pop();
else stat_stack_push();
}
break;
@ -1330,8 +1318,8 @@ void adsp21xx_device::execute_run()
case 0x06:
// 00000110 000xxxxx 00000000 DIVS
{
int xop = (op >> 8) & 7;
int yop = (op >> 11) & 3;
int xop = BIT(op, 8, 3);
int yop = BIT(op, 11, 2);
xop = ALU_GETXREG_UNSIGNED(xop);
yop = ALU_GETYREG_UNSIGNED(yop);
@ -1345,7 +1333,7 @@ void adsp21xx_device::execute_run()
case 0x07:
// 00000111 00010xxx 00000000 DIVQ
{
int xop = (op >> 8) & 7;
int xop = BIT(op, 8, 3);
int res;
xop = ALU_GETXREG_UNSIGNED(xop);
@ -1366,68 +1354,68 @@ void adsp21xx_device::execute_run()
break;
case 0x09:
// 00001001 00000000 000xxxxx modify address register
temp = (op >> 2) & 4;
modify_address(temp + ((op >> 2) & 3), temp + (op & 3));
temp = BIT(op, 2, 3);
modify_address(temp, (temp & 4) | (op & 3));
break;
case 0x0a:
// 00001010 00000000 000xxxxx conditional return
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
pc_stack_pop();
// RTI case
if (op & 0x000010)
if (BIT(op, 4))
stat_stack_pop();
}
break;
case 0x0b:
// 00001011 00000000 xxxxxxxx conditional jump (indirect address)
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
if (op & 0x000010)
if (BIT(op, 4))
pc_stack_push();
m_pc = m_i[4 + ((op >> 6) & 3)] & 0x3fff;
m_pc = m_i[4 + BIT(op, 6, 2)] & 0x3fff;
}
break;
case 0x0c:
// 00001100 xxxxxxxx xxxxxxxx mode control
if (m_chip_type >= CHIP_TYPE_ADSP2101)
{
if (op & 0x000008) m_mstat = (m_mstat & ~MSTAT_GOMODE) | ((op << 5) & MSTAT_GOMODE);
if (op & 0x002000) m_mstat = (m_mstat & ~MSTAT_INTEGER) | ((op >> 8) & MSTAT_INTEGER);
if (op & 0x008000) m_mstat = (m_mstat & ~MSTAT_TIMER) | ((op >> 9) & MSTAT_TIMER);
if (BIT(op, 3)) m_mstat = BIT(op, 2) ? (m_mstat | MSTAT_GOMODE) : (m_mstat & ~MSTAT_GOMODE);
if (BIT(op, 13)) m_mstat = BIT(op, 12) ? (m_mstat | MSTAT_INTEGER) : (m_mstat & ~MSTAT_INTEGER);
if (BIT(op, 15)) m_mstat = BIT(op, 14) ? (m_mstat | MSTAT_TIMER) : (m_mstat & ~MSTAT_TIMER);
}
if (op & 0x000020) m_mstat = (m_mstat & ~MSTAT_BANK) | ((op >> 4) & MSTAT_BANK);
if (op & 0x000080) m_mstat = (m_mstat & ~MSTAT_REVERSE) | ((op >> 5) & MSTAT_REVERSE);
if (op & 0x000200) m_mstat = (m_mstat & ~MSTAT_STICKYV) | ((op >> 6) & MSTAT_STICKYV);
if (op & 0x000800) m_mstat = (m_mstat & ~MSTAT_SATURATE) | ((op >> 7) & MSTAT_SATURATE);
if (BIT(op, 5)) m_mstat = BIT(op, 4) ? (m_mstat | MSTAT_BANK) : (m_mstat & ~MSTAT_BANK);
if (BIT(op, 7)) m_mstat = BIT(op, 6) ? (m_mstat | MSTAT_REVERSE) : (m_mstat & ~MSTAT_REVERSE);
if (BIT(op, 9)) m_mstat = BIT(op, 8) ? (m_mstat | MSTAT_STICKYV) : (m_mstat & ~MSTAT_STICKYV);
if (BIT(op, 11)) m_mstat = BIT(op, 10) ? (m_mstat | MSTAT_SATURATE) : (m_mstat & ~MSTAT_SATURATE);
update_mstat();
break;
case 0x0d:
// 00001101 0000xxxx xxxxxxxx internal data move
switch ((op >> 8) & 15)
switch (BIT(op, 8, 4))
{
case 0x00: write_reg0((op >> 4) & 15, read_reg0(op & 15)); break;
case 0x01: write_reg0((op >> 4) & 15, read_reg1(op & 15)); break;
case 0x02: write_reg0((op >> 4) & 15, read_reg2(op & 15)); break;
case 0x03: write_reg0((op >> 4) & 15, read_reg3(op & 15)); break;
case 0x04: write_reg1((op >> 4) & 15, read_reg0(op & 15)); break;
case 0x05: write_reg1((op >> 4) & 15, read_reg1(op & 15)); break;
case 0x06: write_reg1((op >> 4) & 15, read_reg2(op & 15)); break;
case 0x07: write_reg1((op >> 4) & 15, read_reg3(op & 15)); break;
case 0x08: write_reg2((op >> 4) & 15, read_reg0(op & 15)); break;
case 0x09: write_reg2((op >> 4) & 15, read_reg1(op & 15)); break;
case 0x0a: write_reg2((op >> 4) & 15, read_reg2(op & 15)); break;
case 0x0b: write_reg2((op >> 4) & 15, read_reg3(op & 15)); break;
case 0x0c: write_reg3((op >> 4) & 15, read_reg0(op & 15)); break;
case 0x0d: write_reg3((op >> 4) & 15, read_reg1(op & 15)); break;
case 0x0e: write_reg3((op >> 4) & 15, read_reg2(op & 15)); break;
case 0x0f: write_reg3((op >> 4) & 15, read_reg3(op & 15)); break;
case 0x00: write_reg0(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break;
case 0x01: write_reg0(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break;
case 0x02: write_reg0(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break;
case 0x03: write_reg0(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break;
case 0x04: write_reg1(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break;
case 0x05: write_reg1(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break;
case 0x06: write_reg1(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break;
case 0x07: write_reg1(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break;
case 0x08: write_reg2(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break;
case 0x09: write_reg2(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break;
case 0x0a: write_reg2(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break;
case 0x0b: write_reg2(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break;
case 0x0c: write_reg3(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break;
case 0x0d: write_reg3(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break;
case 0x0e: write_reg3(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break;
case 0x0f: write_reg3(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break;
}
break;
case 0x0e:
// 00001110 0xxxxxxx xxxxxxxx conditional shift
if (condition(op & 15)) shift_op(op);
if (condition(BIT(op, 0, 4))) shift_op(op);
break;
case 0x0f:
// 00001111 0xxxxxxx xxxxxxxx shift immediate
@ -1436,46 +1424,46 @@ void adsp21xx_device::execute_run()
case 0x10:
// 00010000 0xxxxxxx xxxxxxxx shift with internal data register move
shift_op(op);
temp = read_reg0(op & 15);
write_reg0((op >> 4) & 15, temp);
temp = read_reg0(BIT(op, 0, 4));
write_reg0(BIT(op, 4, 4), temp);
break;
case 0x11:
// 00010001 xxxxxxxx xxxxxxxx shift with pgm memory read/write
if (op & 0x8000)
if (BIT(op, 15))
{
pgm_write_dag2(op, read_reg0((op >> 4) & 15));
pgm_write_dag2(op, read_reg0(BIT(op, 4, 4)));
shift_op(op);
}
else
{
shift_op(op);
write_reg0((op >> 4) & 15, pgm_read_dag2(op));
write_reg0(BIT(op, 4, 4), pgm_read_dag2(op));
}
break;
case 0x12:
// 00010010 xxxxxxxx xxxxxxxx shift with data memory read/write DAG1
if (op & 0x8000)
if (BIT(op, 15))
{
data_write_dag1(op, read_reg0((op >> 4) & 15));
data_write_dag1(op, read_reg0(BIT(op, 4, 4)));
shift_op(op);
}
else
{
shift_op(op);
write_reg0((op >> 4) & 15, data_read_dag1(op));
write_reg0(BIT(op, 4, 4), data_read_dag1(op));
}
break;
case 0x13:
// 00010011 xxxxxxxx xxxxxxxx shift with data memory read/write DAG2
if (op & 0x8000)
if (BIT(op, 15))
{
data_write_dag2(op, read_reg0((op >> 4) & 15));
data_write_dag2(op, read_reg0(BIT(op, 4, 4)));
shift_op(op);
}
else
{
shift_op(op);
write_reg0((op >> 4) & 15, data_read_dag2(op));
write_reg0(BIT(op, 4, 4), data_read_dag2(op));
}
break;
case 0x14: case 0x15: case 0x16: case 0x17:
@ -1485,9 +1473,9 @@ void adsp21xx_device::execute_run()
break;
case 0x18: case 0x19: case 0x1a: case 0x1b:
// 000110xx xxxxxxxx xxxxxxxx conditional jump (immediate addr)
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
m_pc = (op >> 4) & 0x3fff;
m_pc = BIT(op, 4, 14);
// check for a busy loop
if (m_pc == m_ppc)
m_icount = 0;
@ -1495,15 +1483,15 @@ void adsp21xx_device::execute_run()
break;
case 0x1c: case 0x1d: case 0x1e: case 0x1f:
// 000111xx xxxxxxxx xxxxxxxx conditional call (immediate addr)
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
pc_stack_push();
m_pc = (op >> 4) & 0x3fff;
m_pc = BIT(op, 4, 14);
}
break;
case 0x20: case 0x21:
// 0010000x xxxxxxxx xxxxxxxx conditional MAC to MR
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
mac_op_mr_xop(op);
@ -1513,9 +1501,9 @@ void adsp21xx_device::execute_run()
break;
case 0x22: case 0x23:
// 0010001x xxxxxxxx xxxxxxxx conditional ALU to AR
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
if (m_chip_type >= CHIP_TYPE_ADSP2181 && BIT(op, 4))
alu_op_ar_const(op);
else
alu_op_ar(op);
@ -1523,7 +1511,7 @@ void adsp21xx_device::execute_run()
break;
case 0x24: case 0x25:
// 0010010x xxxxxxxx xxxxxxxx conditional MAC to MF
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
mac_op_mf_xop(op);
@ -1533,9 +1521,9 @@ void adsp21xx_device::execute_run()
break;
case 0x26: case 0x27:
// 0010011x xxxxxxxx xxxxxxxx conditional ALU to AF
if (condition(op & 15))
if (condition(BIT(op, 0, 4)))
{
if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
if (m_chip_type >= CHIP_TYPE_ADSP2181 && BIT(op, 4))
alu_op_af_const(op);
else
alu_op_af(op);
@ -1543,215 +1531,215 @@ void adsp21xx_device::execute_run()
break;
case 0x28: case 0x29:
// 0010100x xxxxxxxx xxxxxxxx MAC to MR with internal data register move
temp = read_reg0(op & 15);
temp = read_reg0(BIT(op, 0, 4));
mac_op_mr(op);
write_reg0((op >> 4) & 15, temp);
write_reg0(BIT(op, 4, 4), temp);
break;
case 0x2a: case 0x2b:
// 0010101x xxxxxxxx xxxxxxxx ALU to AR with internal data register move
if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0000ff) == 0x0000aa)
if (m_chip_type >= CHIP_TYPE_ADSP2181 && BIT(op, 0, 8) == 0xaa)
alu_op_none(op);
else
{
temp = read_reg0(op & 15);
temp = read_reg0(BIT(op, 0, 4));
alu_op_ar(op);
write_reg0((op >> 4) & 15, temp);
write_reg0(BIT(op, 4, 4), temp);
}
break;
case 0x2c: case 0x2d:
// 0010110x xxxxxxxx xxxxxxxx MAC to MF with internal data register move
temp = read_reg0(op & 15);
temp = read_reg0(BIT(op, 0, 4));
mac_op_mf(op);
write_reg0((op >> 4) & 15, temp);
write_reg0(BIT(op, 4, 4), temp);
break;
case 0x2e: case 0x2f:
// 0010111x xxxxxxxx xxxxxxxx ALU to AF with internal data register move
temp = read_reg0(op & 15);
temp = read_reg0(BIT(op, 0, 4));
alu_op_af(op);
write_reg0((op >> 4) & 15, temp);
write_reg0(BIT(op, 4, 4), temp);
break;
case 0x30: case 0x31: case 0x32: case 0x33:
// 001100xx xxxxxxxx xxxxxxxx load non-data register immediate (group 0)
write_reg0(op & 15, (int32_t)(op << 14) >> 18);
write_reg0(BIT(op, 0, 4), util::sext(op >> 4, 14));
break;
case 0x34: case 0x35: case 0x36: case 0x37:
// 001101xx xxxxxxxx xxxxxxxx load non-data register immediate (group 1)
write_reg1(op & 15, (int32_t)(op << 14) >> 18);
write_reg1(BIT(op, 0, 4), util::sext(op >> 4, 14));
break;
case 0x38: case 0x39: case 0x3a: case 0x3b:
// 001110xx xxxxxxxx xxxxxxxx load non-data register immediate (group 2)
write_reg2(op & 15, (int32_t)(op << 14) >> 18);
write_reg2(BIT(op, 0, 4), util::sext(op >> 4, 14));
break;
case 0x3c: case 0x3d: case 0x3e: case 0x3f:
// 001111xx xxxxxxxx xxxxxxxx load non-data register immediate (group 3)
write_reg3(op & 15, (int32_t)(op << 14) >> 18);
write_reg3(BIT(op, 0, 4), util::sext(op >> 4, 14));
break;
case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
// 0100xxxx xxxxxxxx xxxxxxxx load data register immediate
write_reg0(op & 15, (op >> 4) & 0xffff);
write_reg0(BIT(op, 0, 4), BIT(op, 4, 16));
break;
case 0x50: case 0x51:
// 0101000x xxxxxxxx xxxxxxxx MAC to MR with pgm memory read
mac_op_mr(op);
write_reg0((op >> 4) & 15, pgm_read_dag2(op));
write_reg0(BIT(op, 4, 4), pgm_read_dag2(op));
break;
case 0x52: case 0x53:
// 0101001x xxxxxxxx xxxxxxxx ALU to AR with pgm memory read
alu_op_ar(op);
write_reg0((op >> 4) & 15, pgm_read_dag2(op));
write_reg0(BIT(op, 4, 4), pgm_read_dag2(op));
break;
case 0x54: case 0x55:
// 0101010x xxxxxxxx xxxxxxxx MAC to MF with pgm memory read
mac_op_mf(op);
write_reg0((op >> 4) & 15, pgm_read_dag2(op));
write_reg0(BIT(op, 4, 4), pgm_read_dag2(op));
break;
case 0x56: case 0x57:
// 0101011x xxxxxxxx xxxxxxxx ALU to AF with pgm memory read
alu_op_af(op);
write_reg0((op >> 4) & 15, pgm_read_dag2(op));
write_reg0(BIT(op, 4, 4), pgm_read_dag2(op));
break;
case 0x58: case 0x59:
// 0101100x xxxxxxxx xxxxxxxx MAC to MR with pgm memory write
pgm_write_dag2(op, read_reg0((op >> 4) & 15));
pgm_write_dag2(op, read_reg0(BIT(op, 4, 4)));
mac_op_mr(op);
break;
case 0x5a: case 0x5b:
// 0101101x xxxxxxxx xxxxxxxx ALU to AR with pgm memory write
pgm_write_dag2(op, read_reg0((op >> 4) & 15));
pgm_write_dag2(op, read_reg0(BIT(op, 4, 4)));
alu_op_ar(op);
break;
case 0x5c: case 0x5d:
// 0101110x xxxxxxxx xxxxxxxx ALU to MR with pgm memory write
pgm_write_dag2(op, read_reg0((op >> 4) & 15));
pgm_write_dag2(op, read_reg0(BIT(op, 4, 4)));
mac_op_mf(op);
break;
case 0x5e: case 0x5f:
// 0101111x xxxxxxxx xxxxxxxx ALU to MF with pgm memory write
pgm_write_dag2(op, read_reg0((op >> 4) & 15));
pgm_write_dag2(op, read_reg0(BIT(op, 4, 4)));
alu_op_af(op);
break;
case 0x60: case 0x61:
// 0110000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG1
mac_op_mr(op);
write_reg0((op >> 4) & 15, data_read_dag1(op));
write_reg0(BIT(op, 4, 4), data_read_dag1(op));
break;
case 0x62: case 0x63:
// 0110001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG1
alu_op_ar(op);
write_reg0((op >> 4) & 15, data_read_dag1(op));
write_reg0(BIT(op, 4, 4), data_read_dag1(op));
break;
case 0x64: case 0x65:
// 0110010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG1
mac_op_mf(op);
write_reg0((op >> 4) & 15, data_read_dag1(op));
write_reg0(BIT(op, 4, 4), data_read_dag1(op));
break;
case 0x66: case 0x67:
// 0110011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG1
alu_op_af(op);
write_reg0((op >> 4) & 15, data_read_dag1(op));
write_reg0(BIT(op, 4, 4), data_read_dag1(op));
break;
case 0x68: case 0x69:
// 0110100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG1
data_write_dag1(op, read_reg0((op >> 4) & 15));
data_write_dag1(op, read_reg0(BIT(op, 4, 4)));
mac_op_mr(op);
break;
case 0x6a: case 0x6b:
// 0110101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG1
data_write_dag1(op, read_reg0((op >> 4) & 15));
data_write_dag1(op, read_reg0(BIT(op, 4, 4)));
alu_op_ar(op);
break;
case 0x6c: case 0x6d:
// 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG1
data_write_dag1(op, read_reg0((op >> 4) & 15));
data_write_dag1(op, read_reg0(BIT(op, 4, 4)));
mac_op_mf(op);
break;
case 0x6e: case 0x6f:
// 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG1
data_write_dag1(op, read_reg0((op >> 4) & 15));
data_write_dag1(op, read_reg0(BIT(op, 4, 4)));
alu_op_af(op);
break;
case 0x70: case 0x71:
// 0111000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG2
mac_op_mr(op);
write_reg0((op >> 4) & 15, data_read_dag2(op));
write_reg0(BIT(op, 4, 4), data_read_dag2(op));
break;
case 0x72: case 0x73:
// 0111001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG2
alu_op_ar(op);
write_reg0((op >> 4) & 15, data_read_dag2(op));
write_reg0(BIT(op, 4, 4), data_read_dag2(op));
break;
case 0x74: case 0x75:
// 0111010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG2
mac_op_mf(op);
write_reg0((op >> 4) & 15, data_read_dag2(op));
write_reg0(BIT(op, 4, 4), data_read_dag2(op));
break;
case 0x76: case 0x77:
// 0111011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG2
alu_op_af(op);
write_reg0((op >> 4) & 15, data_read_dag2(op));
write_reg0(BIT(op, 4, 4), data_read_dag2(op));
break;
case 0x78: case 0x79:
// 0111100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG2
data_write_dag2(op, read_reg0((op >> 4) & 15));
data_write_dag2(op, read_reg0(BIT(op, 4, 4)));
mac_op_mr(op);
break;
case 0x7a: case 0x7b:
// 0111101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG2
data_write_dag2(op, read_reg0((op >> 4) & 15));
data_write_dag2(op, read_reg0(BIT(op, 4, 4)));
alu_op_ar(op);
break;
case 0x7c: case 0x7d:
// 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG2
data_write_dag2(op, read_reg0((op >> 4) & 15));
data_write_dag2(op, read_reg0(BIT(op, 4, 4)));
mac_op_mf(op);
break;
case 0x7e: case 0x7f:
// 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG2
data_write_dag2(op, read_reg0((op >> 4) & 15));
data_write_dag2(op, read_reg0(BIT(op, 4, 4)));
alu_op_af(op);
break;
case 0x80: case 0x81: case 0x82: case 0x83:
// 100000xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 0
write_reg0(op & 15, data_read((op >> 4) & 0x3fff));
write_reg0(BIT(op, 0, 4), data_read(BIT(op, 4, 14)));
break;
case 0x84: case 0x85: case 0x86: case 0x87:
// 100001xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 1
write_reg1(op & 15, data_read((op >> 4) & 0x3fff));
write_reg1(BIT(op, 0, 4), data_read(BIT(op, 4, 14)));
break;
case 0x88: case 0x89: case 0x8a: case 0x8b:
// 100010xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 2
write_reg2(op & 15, data_read((op >> 4) & 0x3fff));
write_reg2(BIT(op, 0, 4), data_read(BIT(op, 4, 14)));
break;
case 0x8c: case 0x8d: case 0x8e: case 0x8f:
// 100011xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 3
write_reg3(op & 15, data_read((op >> 4) & 0x3fff));
write_reg3(BIT(op, 0, 4), data_read(BIT(op, 4, 14)));
break;
case 0x90: case 0x91: case 0x92: case 0x93:
// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 0
data_write((op >> 4) & 0x3fff, read_reg0(op & 15));
data_write(BIT(op, 4, 14), read_reg0(BIT(op, 0, 4)));
break;
case 0x94: case 0x95: case 0x96: case 0x97:
// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 1
data_write((op >> 4) & 0x3fff, read_reg1(op & 15));
data_write(BIT(op, 4, 14), read_reg1(BIT(op, 0, 4)));
break;
case 0x98: case 0x99: case 0x9a: case 0x9b:
// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 2
data_write((op >> 4) & 0x3fff, read_reg2(op & 15));
data_write(BIT(op, 4, 14), read_reg2(BIT(op, 0, 4)));
break;
case 0x9c: case 0x9d: case 0x9e: case 0x9f:
// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 3
data_write((op >> 4) & 0x3fff, read_reg3(op & 15));
data_write(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4)));
break;
case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
// 1010xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG1
data_write_dag1(op, (op >> 4) & 0xffff);
data_write_dag1(op, BIT(op, 4, 16));
break;
case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
// 1011xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG2
data_write_dag2(op, (op >> 4) & 0xffff);
data_write_dag2(op, BIT(op, 4, 16));
break;
case 0xc0: case 0xc1:
// 1100000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY0

22
src/devices/cpu/adsp2100/adsp2100.h
View File

@ -256,17 +256,17 @@ protected:
inline uint32_t data_read_dag2(uint32_t op);
inline void pgm_write_dag2(uint32_t op, int32_t val);
inline uint32_t pgm_read_dag2(uint32_t op);
void alu_op_ar(int op);
void alu_op_ar_const(int op);
void alu_op_af(int op);
void alu_op_af_const(int op);
void alu_op_none(int op);
void mac_op_mr(int op);
void mac_op_mr_xop(int op);
void mac_op_mf(int op);
void mac_op_mf_xop(int op);
void shift_op(int op);
void shift_op_imm(int op);
void alu_op_ar(uint32_t op);
void alu_op_ar_const(uint32_t op);
void alu_op_af(uint32_t op);
void alu_op_af_const(uint32_t op);
void alu_op_none(uint32_t op);
void mac_op_mr(uint32_t op);
void mac_op_mr_xop(uint32_t op);
void mac_op_mf(uint32_t op);
void mac_op_mf_xop(uint32_t op);
void shift_op(uint32_t op);
void shift_op_imm(uint32_t op);
// memory access
inline uint16_t data_read(uint32_t addr);