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Switched m6809 and hd6309 to new memory functions

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* cleaned up some macros
* aligned code a bit more
* interrupts now checked in cpu_execute instead of set_context
This commit is contained in:
Couriersud 2008-11-19 19:27:04 +00:00
parent 47c75a8ef4
commit 2cd2454c39
6 changed files with 380 additions and 400 deletions
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120
src/emu/cpu/hd6309/6309ops.c
View File

@ -36,7 +36,7 @@ OP_HANDLER( illegal )
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(0xfff0);
PCD = RM16(m68_state, 0xfff0);
CHANGE_PC;
}
@ -247,8 +247,8 @@ OP_HANDLER( sync )
/* This doesn't require the corresponding interrupt to be enabled: if it */
/* is disabled, execution continues with the next instruction. */
m68_state->int_state |= M6809_SYNC; /* HJB 990227 */
CHECK_IRQ_LINES(m68_state);
/* if M6809_SYNC has not been cleared by CHECK_IRQ_LINES(m68_state),
check_irq_lines(m68_state);
/* if M6809_SYNC has not been cleared by check_irq_lines(m68_state),
* stop execution until the interrupt lines change. */
if( m68_state->int_state & M6809_SYNC )
if (m68_state->icount > 0) m68_state->icount = 0;
@ -312,7 +312,7 @@ OP_HANDLER( orcc )
UINT8 t;
IMMBYTE(t);
CC |= t;
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
}
/* $1B ILLEGAL */
@ -323,7 +323,7 @@ OP_HANDLER( andcc )
UINT8 t;
IMMBYTE(t);
CC &= t;
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
}
/* $1D SEX inherent -**-- */
@ -1185,7 +1185,7 @@ OP_HANDLER( puls )
if( t&0x80 ) { PULLWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { CHECK_IRQ_LINES(m68_state); }
if( t&0x01 ) { check_irq_lines(m68_state); }
}
/* $1039 PULSW inherent ----- */
@ -1230,7 +1230,7 @@ OP_HANDLER( pulu )
if( t&0x80 ) { PULUWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { CHECK_IRQ_LINES(m68_state); }
if( t&0x01 ) { check_irq_lines(m68_state); }
}
/* $38 ILLEGAL */
@ -1272,7 +1272,7 @@ OP_HANDLER( rti )
}
PULLWORD(PCD);
CHANGE_PC;
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
}
/* $3C CWAI inherent ----1 */
@ -1301,7 +1301,7 @@ OP_HANDLER( cwai )
PUSHBYTE(A);
PUSHBYTE(CC);
m68_state->int_state |= M6809_CWAI; /* HJB 990228 */
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
if( m68_state->int_state & M6809_CWAI )
if( m68_state->icount > 0 )
m68_state->icount = 0;
@ -1336,7 +1336,7 @@ OP_HANDLER( swi )
PUSHBYTE(A);
PUSHBYTE(CC);
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(0xfffa);
PCD=RM16(m68_state, 0xfffa);
CHANGE_PC;
}
@ -1507,7 +1507,7 @@ OP_HANDLER( swi2 )
PUSHBYTE(B);
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(0xfff4);
PCD = RM16(m68_state, 0xfff4);
CHANGE_PC;
}
@ -1528,7 +1528,7 @@ OP_HANDLER( swi3 )
PUSHBYTE(B);
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(0xfff2);
PCD = RM16(m68_state, 0xfff2);
CHANGE_PC;
}
@ -3044,7 +3044,7 @@ OP_HANDLER( stx_di )
CLR_NZV;
SET_NZ16(X);
DIRECT;
WM16(EAD,&pX);
WM16(m68_state, EAD,&pX);
}
/* $10dd STQ direct -**0- */
@ -3055,7 +3055,7 @@ OP_HANDLER( stq_di )
q.w.h = D;
q.w.l = W;
DIRECT;
WM32(EAD,&q);
WM32(m68_state, EAD,&q);
CLR_NZV;
SET_N8(A);
SET_Z(q.d);
@ -3067,7 +3067,7 @@ OP_HANDLER( sty_di )
CLR_NZV;
SET_NZ16(Y);
DIRECT;
WM16(EAD,&pY);
WM16(m68_state, EAD,&pY);
}
/* $a0 SUBA indexed ?**** */
@ -3111,7 +3111,7 @@ OP_HANDLER( subd_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = D;
r = d - b.d;
CLR_NZVC;
@ -3125,7 +3125,7 @@ OP_HANDLER( subw_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = W;
r = d - b.d;
CLR_NZVC;
@ -3139,7 +3139,7 @@ OP_HANDLER( cmpw_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = W;
r = d - b.d;
CLR_NZVC;
@ -3152,7 +3152,7 @@ OP_HANDLER( cmpd_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = D;
r = d - b.d;
CLR_NZVC;
@ -3165,7 +3165,7 @@ OP_HANDLER( cmpu_ix )
UINT32 r;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
r = U - b.d;
CLR_NZVC;
SET_FLAGS16(U,b.d,r);
@ -3258,7 +3258,7 @@ OP_HANDLER( cmpx_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = X;
r = d - b.d;
CLR_NZVC;
@ -3271,7 +3271,7 @@ OP_HANDLER( cmpy_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = Y;
r = d - b.d;
CLR_NZVC;
@ -3284,7 +3284,7 @@ OP_HANDLER( cmps_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = S;
r = d - b.d;
CLR_NZVC;
@ -3304,7 +3304,7 @@ OP_HANDLER( jsr_ix )
OP_HANDLER( ldx_ix )
{
fetch_effective_address(m68_state);
X=RM16(EAD);
X=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(X);
}
@ -3316,7 +3316,7 @@ OP_HANDLER( muld_ix )
UINT16 t;
fetch_effective_address(m68_state);
t=RM16(EAD);
t=RM16(m68_state, EAD);
q.d = (INT16) D * (INT16)t;
D = q.w.h;
@ -3375,7 +3375,7 @@ OP_HANDLER( divq_ix )
INT32 v;
fetch_effective_address(m68_state);
t.w.l=RM16(EAD);
t.w.l=RM16(m68_state, EAD);
q.w.h = D;
q.w.l = W;
@ -3421,7 +3421,7 @@ OP_HANDLER( ldq_ix )
PAIR q;
fetch_effective_address(m68_state);
q.d=RM32(EAD);
q.d=RM32(m68_state, EAD);
D = q.w.h;
W = q.w.l;
CLR_NZV;
@ -3433,7 +3433,7 @@ OP_HANDLER( ldq_ix )
OP_HANDLER( ldy_ix )
{
fetch_effective_address(m68_state);
Y=RM16(EAD);
Y=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(Y);
}
@ -3444,7 +3444,7 @@ OP_HANDLER( stx_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(X);
WM16(EAD,&pX);
WM16(m68_state, EAD,&pX);
}
/* $10ed STQ indexed -**0- */
@ -3455,7 +3455,7 @@ OP_HANDLER( stq_ix )
q.w.h = D;
q.w.l = W;
fetch_effective_address(m68_state);
WM32(EAD,&q);
WM32(m68_state, EAD,&q);
CLR_NZV;
SET_N8(A);
SET_Z(q.d);
@ -3467,7 +3467,7 @@ OP_HANDLER( sty_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(Y);
WM16(EAD,&pY);
WM16(m68_state, EAD,&pY);
}
/* $b0 SUBA extended ?**** */
@ -3826,7 +3826,7 @@ OP_HANDLER( stx_ex )
CLR_NZV;
SET_NZ16(X);
EXTENDED;
WM16(EAD,&pX);
WM16(m68_state, EAD,&pX);
}
/* $10fd STQ extended -**0- */
@ -3837,7 +3837,7 @@ OP_HANDLER( stq_ex )
q.w.h = D;
q.w.l = W;
EXTENDED;
WM32(EAD,&q);
WM32(m68_state, EAD,&q);
CLR_NZV;
SET_N8(A);
SET_Z(q.d);
@ -3849,7 +3849,7 @@ OP_HANDLER( sty_ex )
CLR_NZV;
SET_NZ16(Y);
EXTENDED;
WM16(EAD,&pY);
WM16(m68_state, EAD,&pY);
}
/* $c0 SUBB immediate ?**** */
@ -4526,7 +4526,7 @@ OP_HANDLER( std_di )
CLR_NZV;
SET_NZ16(D);
DIRECT;
WM16(EAD,&pD);
WM16(m68_state, EAD,&pD);
}
/* $1097 STW direct -**0- */
@ -4535,7 +4535,7 @@ OP_HANDLER( stw_di )
CLR_NZV;
SET_NZ16(W);
DIRECT;
WM16(EAD,&pW);
WM16(m68_state, EAD,&pW);
}
/* $dE LDU (LDS) direct -**0- */
@ -4561,7 +4561,7 @@ OP_HANDLER( stu_di )
CLR_NZV;
SET_NZ16(U);
DIRECT;
WM16(EAD,&pU);
WM16(m68_state, EAD,&pU);
}
/* $10dF STS direct -**0- */
@ -4570,7 +4570,7 @@ OP_HANDLER( sts_di )
CLR_NZV;
SET_NZ16(S);
DIRECT;
WM16(EAD,&pS);
WM16(m68_state, EAD,&pS);
}
/* $e0 SUBB indexed ?**** */
@ -4659,7 +4659,7 @@ OP_HANDLER( sbcd_ix )
{
UINT32 t,r;
fetch_effective_address(m68_state);
t = RM16(EAD);
t = RM16(m68_state, EAD);
r = D - t - (CC & CC_C);
CLR_NZVC;
SET_FLAGS16(D,t,r);
@ -4672,7 +4672,7 @@ OP_HANDLER( addd_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = D;
r = d + b.d;
CLR_NZVC;
@ -4686,7 +4686,7 @@ OP_HANDLER( addw_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = W;
r = d + b.d;
CLR_NZVC;
@ -4733,7 +4733,7 @@ OP_HANDLER( andb_ix )
OP_HANDLER( andd_ix )
{
fetch_effective_address(m68_state);
D &= RM16(EAD);
D &= RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(D);
}
@ -4753,7 +4753,7 @@ OP_HANDLER( bitd_ix )
{
UINT16 r;
fetch_effective_address(m68_state);
r = D & RM16(EAD);
r = D & RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(r);
}
@ -4825,7 +4825,7 @@ OP_HANDLER( eorb_ix )
OP_HANDLER( eord_ix )
{
fetch_effective_address(m68_state);
D ^= RM16(EAD);
D ^= RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(D);
}
@ -4849,7 +4849,7 @@ OP_HANDLER( adcd_ix )
UINT32 r;
PAIR t;
fetch_effective_address(m68_state);
t.d = RM16(EAD);
t.d = RM16(m68_state, EAD);
r = D + t.d + (CC & CC_C);
CLR_NZVC;
SET_FLAGS16(D,t.d,r);
@ -4869,7 +4869,7 @@ OP_HANDLER( orb_ix )
OP_HANDLER( ord_ix )
{
fetch_effective_address(m68_state);
D |= RM16(EAD);
D |= RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(D);
}
@ -4891,7 +4891,7 @@ OP_HANDLER( addb_ix )
OP_HANDLER( ldd_ix )
{
fetch_effective_address(m68_state);
D=RM16(EAD);
D=RM16(m68_state, EAD);
CLR_NZV; SET_NZ16(D);
}
@ -4899,7 +4899,7 @@ OP_HANDLER( ldd_ix )
OP_HANDLER( ldw_ix )
{
fetch_effective_address(m68_state);
W=RM16(EAD);
W=RM16(m68_state, EAD);
CLR_NZV; SET_NZ16(W);
}
@ -4909,7 +4909,7 @@ OP_HANDLER( std_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(D);
WM16(EAD,&pD);
WM16(m68_state, EAD,&pD);
}
/* $10a7 STW indexed -**0- */
@ -4918,14 +4918,14 @@ OP_HANDLER( stw_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(W);
WM16(EAD,&pW);
WM16(m68_state, EAD,&pW);
}
/* $eE LDU (LDS) indexed -**0- */
OP_HANDLER( ldu_ix )
{
fetch_effective_address(m68_state);
U=RM16(EAD);
U=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(U);
}
@ -4934,7 +4934,7 @@ OP_HANDLER( ldu_ix )
OP_HANDLER( lds_ix )
{
fetch_effective_address(m68_state);
S=RM16(EAD);
S=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(S);
m68_state->int_state |= M6809_LDS;
@ -4946,7 +4946,7 @@ OP_HANDLER( stu_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(U);
WM16(EAD,&pU);
WM16(m68_state, EAD,&pU);
}
/* $10eF STS indexed -**0- */
@ -4955,7 +4955,7 @@ OP_HANDLER( sts_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(S);
WM16(EAD,&pS);
WM16(m68_state, EAD,&pS);
}
/* $f0 SUBB extended ?**** */
@ -5285,7 +5285,7 @@ OP_HANDLER( std_ex )
CLR_NZV;
SET_NZ16(D);
EXTENDED;
WM16(EAD,&pD);
WM16(m68_state, EAD,&pD);
}
/* $10b7 STW extended -**0- */
@ -5294,7 +5294,7 @@ OP_HANDLER( stw_ex )
CLR_NZV;
SET_NZ16(W);
EXTENDED;
WM16(EAD,&pW);
WM16(m68_state, EAD,&pW);
}
/* $fE LDU (LDS) extended -**0- */
@ -5320,7 +5320,7 @@ OP_HANDLER( stu_ex )
CLR_NZV;
SET_NZ16(U);
EXTENDED;
WM16(EAD,&pU);
WM16(m68_state, EAD,&pU);
}
/* $10fF STS extended -**0- */
@ -5329,7 +5329,7 @@ OP_HANDLER( sts_ex )
CLR_NZV;
SET_NZ16(S);
EXTENDED;
WM16(EAD,&pS);
WM16(m68_state, EAD,&pS);
}
/* $10xx opcodes */
@ -5479,7 +5479,7 @@ OP_HANDLER( pref10 )
#endif /* BIG_SWITCH */
m68_state->icount -= cycle_counts_page01[ireg2];
m68_state->icount -= m68_state->cycle_counts_page01[ireg2];
}
/* $11xx opcodes */
@ -5592,6 +5592,6 @@ OP_HANDLER( pref11 )
(*hd6309_page11[ireg2])(m68_state);
#endif /* BIG_SWITCH */
m68_state->icount -= cycle_counts_page11[ireg2];
m68_state->icount -= m68_state->cycle_counts_page11[ireg2];
}

250
src/emu/cpu/hd6309/hd6309.c
View File

@ -102,52 +102,57 @@
*****************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "hd6309.h"
#define BIG_SWITCH 0
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
#define BIG_SWITCH 0
/* 6309 Registers */
typedef struct _m68_state_t m68_state_t;
struct _m68_state_t
{
PAIR pc; /* Program counter */
PAIR ppc; /* Previous program counter */
PAIR d; /* Accumlator d and w (ab = d, ef = w, abef = q) */
PAIR w;
PAIR d; /* Accumulator a and b */
PAIR w; /* Accumlator e and f */
/* abef = q */
PAIR dp; /* Direct Page register (page in MSB) */
PAIR u, s; /* Stack pointers */
PAIR x, y; /* Index registers */
PAIR v; /* New 6309 register */
UINT8 cc;
PAIR v; /* New 6309 register */
UINT8 md; /* Special mode register */
UINT8 ireg; /* First opcode */
UINT8 irq_state[2];
int extra_cycles; /* cycles used up by interrupts */
cpu_irq_callback irq_callback;
const device_config *device;
int icount;
PAIR ea; /* effective address */
/* Memory spaces */
const address_space *program;
UINT8 int_state; /* SYNC and CWAI flags */
UINT8 nmi_state;
UINT8 dummy_byte;
UINT8 *regTable[4];
UINT8 const *cycle_counts_page0;
UINT8 const *cycle_counts_page01;
UINT8 const *cycle_counts_page11;
UINT8 const *index_cycle;
};
static void CHECK_IRQ_LINES( m68_state_t *m68_state );
static void check_irq_lines( m68_state_t *m68_state );
static void IIError(m68_state_t *m68_state);
static void DZError(m68_state_t *m68_state);
@ -217,11 +222,29 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
#define M6809_SYNC 16 /* set when SYNC is waiting for an interrupt */
#define M6809_LDS 32 /* set when LDS occured at least once */
/* these are re-defined in m68_state->h TO RAM, ROM or functions in cpuintrf.c */
#define RM(mAddr) HD6309_RDMEM(mAddr)
#define WM(mAddr,Value) HD6309_WRMEM(mAddr,Value)
#define ROP(mAddr) HD6309_RDOP(mAddr)
#define ROP_ARG(mAddr) HD6309_RDOP_ARG(mAddr)
/****************************************************************************/
/* Read a byte from given memory location */
/****************************************************************************/
#define RM(Addr) ((unsigned)memory_read_byte_8be(m68_state->program, Addr))
/****************************************************************************/
/* Write a byte to given memory location */
/****************************************************************************/
#define WM(Addr,Value) (memory_write_byte_8be(m68_state->program, Addr,Value))
/****************************************************************************/
/* Z80_RDOP() is identical to Z80_RDMEM() except it is used for reading */
/* opcodes. In case of system with memory mapped I/O, this function can be */
/* used to greatly speed up emulation */
/****************************************************************************/
#define ROP(Addr) ((unsigned)memory_decrypted_read_byte(m68_state->program, Addr))
/****************************************************************************/
/* Z80_RDOP_ARG() is identical to Z80_RDOP() except it is used for reading */
/* opcode arguments. This difference can be used to support systems that */
/* use different encoding mechanisms for opcodes and opcode arguments */
/****************************************************************************/
#define ROP_ARG(Addr) ((unsigned)memory_raw_read_byte(m68_state->program, Addr))
/* macros to access memory */
#define IMMBYTE(b) b = ROP_ARG(PCD); PC++
@ -264,11 +287,6 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
#define SET_FLAGS8I(a) {CC|=flags8i[(a)&0xff];}
#define SET_FLAGS8D(a) {CC|=flags8d[(a)&0xff];}
static UINT8 const *cycle_counts_page0;
static UINT8 const *cycle_counts_page01;
static UINT8 const *cycle_counts_page11;
static UINT8 const *index_cycle;
/* combos */
#define SET_NZ8(a) {SET_N8(a);SET_Z(a);}
#define SET_NZ16(a) {SET_N16(a);SET_Z(a);}
@ -316,12 +334,12 @@ static UINT8 const *index_cycle;
/* macros for convenience */
#define DIRBYTE(b) {DIRECT;b=RM(EAD);}
#define DIRWORD(w) {DIRECT;w.d=RM16(EAD);}
#define DIRWORD(w) {DIRECT;w.d=RM16(m68_state, EAD);}
#define EXTBYTE(b) {EXTENDED;b=RM(EAD);}
#define EXTWORD(w) {EXTENDED;w.d=RM16(EAD);}
#define EXTWORD(w) {EXTENDED;w.d=RM16(m68_state, EAD);}
#define DIRLONG(lng) {DIRECT;lng.w.h=RM16(EAD);lng.w.l=RM16(EAD+2);}
#define EXTLONG(lng) {EXTENDED;lng.w.h=RM16(EAD);lng.w.l=RM16(EAD+2);}
#define DIRLONG(lng) {DIRECT;lng.w.h=RM16(m68_state, EAD);lng.w.l=RM16(m68_state, EAD+2);}
#define EXTLONG(lng) {EXTENDED;lng.w.h=RM16(m68_state, EAD);lng.w.l=RM16(m68_state, EAD+2);}
/* includes the static function prototypes and other tables */
#include "6309tbl.c"
@ -349,13 +367,15 @@ static UINT8 const *index_cycle;
} \
}
INLINE UINT32 RM16( UINT32 Addr )
/* macros for setting/getting registers in TFR/EXG instructions */
INLINE UINT32 RM16(m68_state_t *m68_state, UINT32 Addr )
{
UINT32 result = RM(Addr) << 8;
return result | RM((Addr+1)&0xffff);
}
INLINE UINT32 RM32( UINT32 Addr )
INLINE UINT32 RM32(m68_state_t *m68_state, UINT32 Addr )
{
UINT32 result = RM(Addr) << 24;
result += RM(Addr+1) << 16;
@ -364,13 +384,13 @@ INLINE UINT32 RM32( UINT32 Addr )
return result;
}
INLINE void WM16( UINT32 Addr, PAIR *p )
INLINE void WM16(m68_state_t *m68_state, UINT32 Addr, PAIR *p )
{
WM( Addr, p->b.h );
WM( (Addr+1)&0xffff, p->b.l );
}
INLINE void WM32( UINT32 Addr, PAIR *p )
INLINE void WM32(m68_state_t *m68_state, UINT32 Addr, PAIR *p )
{
WM( Addr, p->b.h3 );
WM( (Addr+1)&0xffff, p->b.h2 );
@ -382,21 +402,21 @@ static void UpdateState(m68_state_t *m68_state)
{
if ( m68_state->md & MD_EM )
{
cycle_counts_page0 = ccounts_page0_na;
cycle_counts_page01 = ccounts_page01_na;
cycle_counts_page11 = ccounts_page11_na;
index_cycle = index_cycle_na;
m68_state->cycle_counts_page0 = ccounts_page0_na;
m68_state->cycle_counts_page01 = ccounts_page01_na;
m68_state->cycle_counts_page11 = ccounts_page11_na;
m68_state->index_cycle = index_cycle_na;
}
else
{
cycle_counts_page0 = ccounts_page0_em;
cycle_counts_page01 = ccounts_page01_em;
cycle_counts_page11 = ccounts_page11_em;
index_cycle = index_cycle_em;
m68_state->cycle_counts_page0 = ccounts_page0_em;
m68_state->cycle_counts_page01 = ccounts_page01_em;
m68_state->cycle_counts_page11 = ccounts_page11_em;
m68_state->index_cycle = index_cycle_em;
}
}
static void CHECK_IRQ_LINES( m68_state_t *m68_state )
static void check_irq_lines( m68_state_t *m68_state )
{
if( m68_state->irq_state[HD6309_IRQ_LINE] != CLEAR_LINE ||
m68_state->irq_state[HD6309_FIRQ_LINE] != CLEAR_LINE )
@ -440,7 +460,7 @@ static void CHECK_IRQ_LINES( m68_state_t *m68_state )
}
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(0xfff6);
PCD=RM16(m68_state, 0xfff6);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, HD6309_FIRQ_LINE);
}
@ -474,7 +494,7 @@ static void CHECK_IRQ_LINES( m68_state_t *m68_state )
m68_state->extra_cycles += 19; /* subtract +19 cycles */
}
CC |= CC_II; /* inhibit IRQ */
PCD=RM16(0xfff8);
PCD=RM16(m68_state, 0xfff8);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, HD6309_IRQ_LINE);
}
@ -485,7 +505,6 @@ static void CHECK_IRQ_LINES( m68_state_t *m68_state )
/****************************************************************************
* Get all registers in given buffer
****************************************************************************/
static CPU_GET_CONTEXT( hd6309 )
{
}
@ -495,12 +514,6 @@ static CPU_GET_CONTEXT( hd6309 )
****************************************************************************/
static CPU_SET_CONTEXT( hd6309 )
{
m68_state_t *m68_state = src;
CHANGE_PC;
CHECK_IRQ_LINES(m68_state);
UpdateState(m68_state);
}
static STATE_POSTLOAD( hd6309_postload )
@ -521,7 +534,9 @@ static CPU_INIT( hd6309 )
m68_state->irq_callback = irqcallback;
m68_state->device = device;
m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
/* setup regtable */
m68_state->regTable[0] = &(CC);
@ -555,8 +570,7 @@ static CPU_RESET( hd6309 )
m68_state->int_state = 0;
m68_state->nmi_state = CLEAR_LINE;
m68_state->irq_state[0] = CLEAR_LINE;
/*FIXME: BUG ?*/
m68_state->irq_state[0] = CLEAR_LINE;
m68_state->irq_state[1] = CLEAR_LINE;
DPD = 0; /* Reset direct page register */
@ -564,7 +578,7 @@ static CPU_RESET( hd6309 )
CC |= CC_II; /* IRQ disabled */
CC |= CC_IF; /* FIRQ disabled */
PCD = RM16(0xfffe);
PCD = RM16(m68_state, 0xfffe);
CHANGE_PC;
UpdateState(m68_state);
}
@ -617,7 +631,7 @@ static void set_irq_line(m68_state_t *m68_state, int irqline, int state)
m68_state->extra_cycles += 19; /* subtract +19 cycles next time */
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD = RM16(0xfffc);
PCD = RM16(m68_state, 0xfffc);
CHANGE_PC;
}
else if (irqline < 2)
@ -625,7 +639,7 @@ static void set_irq_line(m68_state_t *m68_state, int irqline, int state)
LOG(("HD6309#%d set_irq_line %d, %d (PC=%4.4X)\n", cpunum_get_active(), irqline, state, pPC.d));
m68_state->irq_state[irqline] = state;
if (state == CLEAR_LINE) return;
CHECK_IRQ_LINES(m68_state);
check_irq_lines(m68_state);
}
}
@ -642,6 +656,8 @@ static CPU_EXECUTE( hd6309 ) /* NS 970908 */
m68_state->icount = cycles - m68_state->extra_cycles;
m68_state->extra_cycles = 0;
check_irq_lines(m68_state);
if (m68_state->int_state & (M6809_CWAI | M6809_SYNC))
{
debugger_instruction_hook(device->machine, PCD);
@ -921,7 +937,7 @@ static CPU_EXECUTE( hd6309 ) /* NS 970908 */
(*hd6309_main[m68_state->ireg])(m68_state);
#endif /* BIG_SWITCH */
m68_state->icount -= cycle_counts_page0[m68_state->ireg];
m68_state->icount -= m68_state->cycle_counts_page0[m68_state->ireg];
} while( m68_state->icount > 0 );
@ -1092,22 +1108,22 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0x8e: EA=X+W; break;
case 0x8f: EA=W; break;
case 0x90: EA=W; EAD=RM16(EAD); break;
case 0x91: EA=X; X+=2; EAD=RM16(EAD); break;
case 0x90: EA=W; EAD=RM16(m68_state, EAD); break;
case 0x91: EA=X; X+=2; EAD=RM16(m68_state, EAD); break;
case 0x92: IIError(m68_state); break;
case 0x93: X-=2; EA=X; EAD=RM16(EAD); break;
case 0x94: EA=X; EAD=RM16(EAD); break;
case 0x95: EA=X+SIGNED(B); EAD=RM16(EAD); break;
case 0x96: EA=X+SIGNED(A); EAD=RM16(EAD); break;
case 0x97: EA=X+SIGNED(E); EAD=RM16(EAD); break;
case 0x98: IMMBYTE(EA); EA=X+SIGNED(EA); EAD=RM16(EAD); break;
case 0x99: IMMWORD(EAP); EA+=X; EAD=RM16(EAD); break;
case 0x9a: EA=X+SIGNED(F); EAD=RM16(EAD); break;
case 0x9b: EA=X+D; EAD=RM16(EAD); break;
case 0x9c: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0x9d: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0x9e: EA=X+W; EAD=RM16(EAD); break;
case 0x9f: IMMWORD(EAP); EAD=RM16(EAD); break;
case 0x93: X-=2; EA=X; EAD=RM16(m68_state, EAD); break;
case 0x94: EA=X; EAD=RM16(m68_state, EAD); break;
case 0x95: EA=X+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0x96: EA=X+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0x97: EA=X+SIGNED(E); EAD=RM16(m68_state, EAD); break;
case 0x98: IMMBYTE(EA); EA=X+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0x99: IMMWORD(EAP); EA+=X; EAD=RM16(m68_state, EAD); break;
case 0x9a: EA=X+SIGNED(F); EAD=RM16(m68_state, EAD); break;
case 0x9b: EA=X+D; EAD=RM16(m68_state, EAD); break;
case 0x9c: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0x9d: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0x9e: EA=X+W; EAD=RM16(m68_state, EAD); break;
case 0x9f: IMMWORD(EAP); EAD=RM16(m68_state, EAD); break;
case 0xa0: EA=Y; Y++; break;
case 0xa1: EA=Y; Y+=2; break;
@ -1126,21 +1142,21 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0xae: EA=Y+W; break;
case 0xaf: IMMWORD(EAP); EA+=W; break;
case 0xb0: IMMWORD(EAP); EA+=W; EAD=RM16(EAD); break;
case 0xb1: EA=Y; Y+=2; EAD=RM16(EAD); break;
case 0xb0: IMMWORD(EAP); EA+=W; EAD=RM16(m68_state, EAD); break;
case 0xb1: EA=Y; Y+=2; EAD=RM16(m68_state, EAD); break;
case 0xb2: IIError(m68_state); break;
case 0xb3: Y-=2; EA=Y; EAD=RM16(EAD); break;
case 0xb4: EA=Y; EAD=RM16(EAD); break;
case 0xb5: EA=Y+SIGNED(B); EAD=RM16(EAD); break;
case 0xb6: EA=Y+SIGNED(A); EAD=RM16(EAD); break;
case 0xb7: EA=Y+SIGNED(E); EAD=RM16(EAD); break;
case 0xb8: IMMBYTE(EA); EA=Y+SIGNED(EA); EAD=RM16(EAD); break;
case 0xb9: IMMWORD(EAP); EA+=Y; EAD=RM16(EAD); break;
case 0xba: EA=Y+SIGNED(F); EAD=RM16(EAD); break;
case 0xbb: EA=Y+D; EAD=RM16(EAD); break;
case 0xbc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0xbd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0xbe: EA=Y+W; EAD=RM16(EAD); break;
case 0xb3: Y-=2; EA=Y; EAD=RM16(m68_state, EAD); break;
case 0xb4: EA=Y; EAD=RM16(m68_state, EAD); break;
case 0xb5: EA=Y+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0xb6: EA=Y+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0xb7: EA=Y+SIGNED(E); EAD=RM16(m68_state, EAD); break;
case 0xb8: IMMBYTE(EA); EA=Y+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xb9: IMMWORD(EAP); EA+=Y; EAD=RM16(m68_state, EAD); break;
case 0xba: EA=Y+SIGNED(F); EAD=RM16(m68_state, EAD); break;
case 0xbb: EA=Y+D; EAD=RM16(m68_state, EAD); break;
case 0xbc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xbd: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0xbe: EA=Y+W; EAD=RM16(m68_state, EAD); break;
case 0xbf: IIError(m68_state); break;
case 0xc0: EA=U; U++; break;
@ -1160,21 +1176,21 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0xce: EA=U+W; break;
case 0xcf: EA=W; W+=2; break;
case 0xd0: EA=W; W+=2; EAD=RM16(EAD); break;
case 0xd1: EA=U; U+=2; EAD=RM16(EAD); break;
case 0xd0: EA=W; W+=2; EAD=RM16(m68_state, EAD); break;
case 0xd1: EA=U; U+=2; EAD=RM16(m68_state, EAD); break;
case 0xd2: IIError(m68_state); break;
case 0xd3: U-=2; EA=U; EAD=RM16(EAD); break;
case 0xd4: EA=U; EAD=RM16(EAD); break;
case 0xd5: EA=U+SIGNED(B); EAD=RM16(EAD); break;
case 0xd6: EA=U+SIGNED(A); EAD=RM16(EAD); break;
case 0xd7: EA=U+SIGNED(E); EAD=RM16(EAD); break;
case 0xd8: IMMBYTE(EA); EA=U+SIGNED(EA); EAD=RM16(EAD); break;
case 0xd9: IMMWORD(EAP); EA+=U; EAD=RM16(EAD); break;
case 0xda: EA=U+SIGNED(F); EAD=RM16(EAD); break;
case 0xdb: EA=U+D; EAD=RM16(EAD); break;
case 0xdc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0xdd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0xde: EA=U+W; EAD=RM16(EAD); break;
case 0xd3: U-=2; EA=U; EAD=RM16(m68_state, EAD); break;
case 0xd4: EA=U; EAD=RM16(m68_state, EAD); break;
case 0xd5: EA=U+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0xd6: EA=U+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0xd7: EA=U+SIGNED(E); EAD=RM16(m68_state, EAD); break;
case 0xd8: IMMBYTE(EA); EA=U+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xd9: IMMWORD(EAP); EA+=U; EAD=RM16(m68_state, EAD); break;
case 0xda: EA=U+SIGNED(F); EAD=RM16(m68_state, EAD); break;
case 0xdb: EA=U+D; EAD=RM16(m68_state, EAD); break;
case 0xdc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xdd: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0xde: EA=U+W; EAD=RM16(m68_state, EAD); break;
case 0xdf: IIError(m68_state); break;
case 0xe0: EA=S; S++; break;
@ -1194,25 +1210,25 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0xee: EA=S+W; break;
case 0xef: W-=2; EA=W; break;
case 0xf0: W-=2; EA=W; EAD=RM16(EAD); break;
case 0xf1: EA=S; S+=2; EAD=RM16(EAD); break;
case 0xf0: W-=2; EA=W; EAD=RM16(m68_state, EAD); break;
case 0xf1: EA=S; S+=2; EAD=RM16(m68_state, EAD); break;
case 0xf2: IIError(m68_state); break;
case 0xf3: S-=2; EA=S; EAD=RM16(EAD); break;
case 0xf4: EA=S; EAD=RM16(EAD); break;
case 0xf5: EA=S+SIGNED(B); EAD=RM16(EAD); break;
case 0xf6: EA=S+SIGNED(A); EAD=RM16(EAD); break;
case 0xf7: EA=S+SIGNED(E); EAD=RM16(EAD); break;
case 0xf8: IMMBYTE(EA); EA=S+SIGNED(EA); EAD=RM16(EAD); break;
case 0xf9: IMMWORD(EAP); EA+=S; EAD=RM16(EAD); break;
case 0xfa: EA=S+SIGNED(F); EAD=RM16(EAD); break;
case 0xfb: EA=S+D; EAD=RM16(EAD); break;
case 0xfc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0xfd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0xfe: EA=S+W; EAD=RM16(EAD); break;
case 0xf3: S-=2; EA=S; EAD=RM16(m68_state, EAD); break;
case 0xf4: EA=S; EAD=RM16(m68_state, EAD); break;
case 0xf5: EA=S+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0xf6: EA=S+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0xf7: EA=S+SIGNED(E); EAD=RM16(m68_state, EAD); break;
case 0xf8: IMMBYTE(EA); EA=S+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xf9: IMMWORD(EAP); EA+=S; EAD=RM16(m68_state, EAD); break;
case 0xfa: EA=S+SIGNED(F); EAD=RM16(m68_state, EAD); break;
case 0xfb: EA=S+D; EAD=RM16(m68_state, EAD); break;
case 0xfc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xfd: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0xfe: EA=S+W; EAD=RM16(m68_state, EAD); break;
case 0xff: IIError(m68_state); break;
}
m68_state->icount -= index_cycle[postbyte];
m68_state->icount -= m68_state->index_cycle[postbyte];
}
@ -1235,7 +1251,7 @@ static CPU_SET_INFO( hd6309 )
case CPUINFO_INT_REGISTER + HD6309_PC: PC = info->i; CHANGE_PC; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + HD6309_S: S = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_CC: CC = info->i; CHECK_IRQ_LINES(m68_state); break;
case CPUINFO_INT_REGISTER + HD6309_CC: CC = info->i; check_irq_lines(m68_state); break;
case CPUINFO_INT_REGISTER + HD6309_MD: MD = info->i; UpdateState(m68_state); break;
case CPUINFO_INT_REGISTER + HD6309_U: U = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_A: A = info->i; break;
@ -1257,7 +1273,7 @@ static CPU_SET_INFO( hd6309 )
CPU_GET_INFO( hd6309 )
{
m68_state_t *m68_state = device ? device->token : NULL;
m68_state_t *m68_state = (device != NULL) ? device->token : NULL;
switch (state)
{

31
src/emu/cpu/hd6309/hd6309.h
View File

@ -20,37 +20,6 @@ enum
/* PUBLIC FUNCTIONS */
CPU_GET_INFO( hd6309 );
/****************************************************************************/
/* Read a byte from given memory location */
/****************************************************************************/
/* ASG 971005 -- changed to program_read_byte_8/cpu_writemem16 */
#define HD6309_RDMEM(Addr) ((unsigned)program_read_byte_8be(Addr))
/****************************************************************************/
/* Write a byte to given memory location */
/****************************************************************************/
#define HD6309_WRMEM(Addr,Value) (program_write_byte_8be(Addr,Value))
/****************************************************************************/
/* Z80_RDOP() is identical to Z80_RDMEM() except it is used for reading */
/* opcodes. In case of system with memory mapped I/O, this function can be */
/* used to greatly speed up emulation */
/****************************************************************************/
#define HD6309_RDOP(Addr) ((unsigned)program_decrypted_read_byte(Addr))
/****************************************************************************/
/* Z80_RDOP_ARG() is identical to Z80_RDOP() except it is used for reading */
/* opcode arguments. This difference can be used to support systems that */
/* use different encoding mechanisms for opcodes and opcode arguments */
/****************************************************************************/
#define HD6309_RDOP_ARG(Addr) ((unsigned)program_raw_read_byte(Addr))
#ifndef FALSE
# define FALSE 0
#endif
#ifndef TRUE
# define TRUE (!FALSE)
#endif
CPU_DISASSEMBLE( hd6309 );

100
src/emu/cpu/m6809/6809ops.c
View File

@ -14,15 +14,16 @@ HNZVC
#define OP_HANDLER(_name) INLINE void _name (m68_state_t *m68_state)
#ifdef NEW
static void illegal )
#else
OP_HANDLER( illegal )
#endif
{
logerror("M6809: illegal opcode at %04x\n",PC);
}
static void IIError(m68_state_t *m68_state)
{
illegal(m68_state); // Vector to Trap handler
}
/* $00 NEG direct ?**** */
OP_HANDLER( neg_di )
{
@ -179,8 +180,8 @@ OP_HANDLER( sync )
/* This doesn't require the corresponding interrupt to be enabled: if it */
/* is disabled, execution continues with the next instruction. */
m68_state->int_state |= M6809_SYNC; /* HJB 990227 */
CHECK_IRQ_LINES(m68_state);
/* if M6809_SYNC has not been cleared by CHECK_IRQ_LINES(m68_state),
check_irq_lines(m68_state);
/* if M6809_SYNC has not been cleared by check_irq_lines(m68_state),
* stop execution until the interrupt lines change. */
if( m68_state->int_state & M6809_SYNC )
if (m68_state->icount > 0) m68_state->icount = 0;
@ -234,7 +235,7 @@ OP_HANDLER( orcc )
UINT8 t;
IMMBYTE(t);
CC |= t;
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
}
/* $1B ILLEGAL */
@ -245,7 +246,7 @@ OP_HANDLER( andcc )
UINT8 t;
IMMBYTE(t);
CC &= t;
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
}
/* $1D SEX inherent -**-- */
@ -624,7 +625,7 @@ OP_HANDLER( puls )
if( t&0x80 ) { PULLWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { CHECK_IRQ_LINES(m68_state); }
if( t&0x01 ) { check_irq_lines(m68_state); }
}
/* $36 PSHU inherent ----- */
@ -657,7 +658,7 @@ OP_HANDLER( pulu )
if( t&0x80 ) { PULUWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { CHECK_IRQ_LINES(m68_state); }
if( t&0x01 ) { check_irq_lines(m68_state); }
}
/* $38 ILLEGAL */
@ -693,7 +694,7 @@ OP_HANDLER( rti )
}
PULLWORD(PCD);
CHANGE_PC;
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
}
/* $3C CWAI inherent ----1 */
@ -717,7 +718,7 @@ OP_HANDLER( cwai )
PUSHBYTE(A);
PUSHBYTE(CC);
m68_state->int_state |= M6809_CWAI; /* HJB 990228 */
CHECK_IRQ_LINES(m68_state); /* HJB 990116 */
check_irq_lines(m68_state); /* HJB 990116 */
if( m68_state->int_state & M6809_CWAI )
if( m68_state->icount > 0 )
m68_state->icount = 0;
@ -747,7 +748,7 @@ OP_HANDLER( swi )
PUSHBYTE(A);
PUSHBYTE(CC);
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(0xfffa);
PCD=RM16(m68_state, 0xfffa);
CHANGE_PC;
}
@ -763,7 +764,7 @@ OP_HANDLER( swi2 )
PUSHBYTE(B);
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(0xfff4);
PCD = RM16(m68_state, 0xfff4);
CHANGE_PC;
}
@ -779,7 +780,7 @@ OP_HANDLER( swi3 )
PUSHBYTE(B);
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(0xfff2);
PCD = RM16(m68_state, 0xfff2);
CHANGE_PC;
}
@ -1480,7 +1481,7 @@ OP_HANDLER( stx_im )
CLR_NZV;
SET_NZ16(X);
IMM16;
WM16(EAD,&pX);
WM16(m68_state, EAD,&pX);
}
/* is this a legal instruction? */
@ -1490,7 +1491,7 @@ OP_HANDLER( sty_im )
CLR_NZV;
SET_NZ16(Y);
IMM16;
WM16(EAD,&pY);
WM16(m68_state, EAD,&pY);
}
/* $90 SUBA direct ?**** */
@ -1710,7 +1711,7 @@ OP_HANDLER( stx_di )
CLR_NZV;
SET_NZ16(X);
DIRECT;
WM16(EAD,&pX);
WM16(m68_state, EAD,&pX);
}
/* $109F STY direct -**0- */
@ -1719,7 +1720,7 @@ OP_HANDLER( sty_di )
CLR_NZV;
SET_NZ16(Y);
DIRECT;
WM16(EAD,&pY);
WM16(m68_state, EAD,&pY);
}
/* $a0 SUBA indexed ?**** */
@ -1763,7 +1764,7 @@ OP_HANDLER( subd_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = D;
r = d - b.d;
CLR_NZVC;
@ -1777,7 +1778,7 @@ OP_HANDLER( cmpd_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = D;
r = d - b.d;
CLR_NZVC;
@ -1790,7 +1791,7 @@ OP_HANDLER( cmpu_ix )
UINT32 r;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
r = U - b.d;
CLR_NZVC;
SET_FLAGS16(U,b.d,r);
@ -1883,7 +1884,7 @@ OP_HANDLER( cmpx_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = X;
r = d - b.d;
CLR_NZVC;
@ -1896,7 +1897,7 @@ OP_HANDLER( cmpy_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = Y;
r = d - b.d;
CLR_NZVC;
@ -1909,7 +1910,7 @@ OP_HANDLER( cmps_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = S;
r = d - b.d;
CLR_NZVC;
@ -1929,7 +1930,7 @@ OP_HANDLER( jsr_ix )
OP_HANDLER( ldx_ix )
{
fetch_effective_address(m68_state);
X=RM16(EAD);
X=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(X);
}
@ -1938,7 +1939,7 @@ OP_HANDLER( ldx_ix )
OP_HANDLER( ldy_ix )
{
fetch_effective_address(m68_state);
Y=RM16(EAD);
Y=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(Y);
}
@ -1949,7 +1950,7 @@ OP_HANDLER( stx_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(X);
WM16(EAD,&pX);
WM16(m68_state, EAD,&pX);
}
/* $10aF STY indexed -**0- */
@ -1958,7 +1959,7 @@ OP_HANDLER( sty_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(Y);
WM16(EAD,&pY);
WM16(m68_state, EAD,&pY);
}
/* $b0 SUBA extended ?**** */
@ -2177,7 +2178,7 @@ OP_HANDLER( stx_ex )
CLR_NZV;
SET_NZ16(X);
EXTENDED;
WM16(EAD,&pX);
WM16(m68_state, EAD,&pX);
}
/* $10bF STY extended -**0- */
@ -2186,7 +2187,7 @@ OP_HANDLER( sty_ex )
CLR_NZV;
SET_NZ16(Y);
EXTENDED;
WM16(EAD,&pY);
WM16(m68_state, EAD,&pY);
}
/* $c0 SUBB immediate ?**** */
@ -2330,7 +2331,7 @@ OP_HANDLER( std_im )
CLR_NZV;
SET_NZ16(D);
IMM16;
WM16(EAD,&pD);
WM16(m68_state, EAD,&pD);
}
/* $cE LDU (LDS) immediate -**0- */
@ -2357,7 +2358,7 @@ OP_HANDLER( stu_im )
CLR_NZV;
SET_NZ16(U);
IMM16;
WM16(EAD,&pU);
WM16(m68_state, EAD,&pU);
}
/* is this a legal instruction? */
@ -2367,7 +2368,7 @@ OP_HANDLER( sts_im )
CLR_NZV;
SET_NZ16(S);
IMM16;
WM16(EAD,&pS);
WM16(m68_state, EAD,&pS);
}
/* $d0 SUBB direct ?**** */
@ -2510,7 +2511,7 @@ OP_HANDLER( std_di )
CLR_NZV;
SET_NZ16(D);
DIRECT;
WM16(EAD,&pD);
WM16(m68_state, EAD,&pD);
}
/* $dE LDU (LDS) direct -**0- */
@ -2536,7 +2537,7 @@ OP_HANDLER( stu_di )
CLR_NZV;
SET_NZ16(U);
DIRECT;
WM16(EAD,&pU);
WM16(m68_state, EAD,&pU);
}
/* $10dF STS direct -**0- */
@ -2545,7 +2546,7 @@ OP_HANDLER( sts_di )
CLR_NZV;
SET_NZ16(S);
DIRECT;
WM16(EAD,&pS);
WM16(m68_state, EAD,&pS);
}
/* $e0 SUBB indexed ?**** */
@ -2589,7 +2590,7 @@ OP_HANDLER( addd_ix )
UINT32 r,d;
PAIR b;
fetch_effective_address(m68_state);
b.d=RM16(EAD);
b.d=RM16(m68_state, EAD);
d = D;
r = d + b.d;
CLR_NZVC;
@ -2682,7 +2683,7 @@ OP_HANDLER( addb_ix )
OP_HANDLER( ldd_ix )
{
fetch_effective_address(m68_state);
D=RM16(EAD);
D=RM16(m68_state, EAD);
CLR_NZV; SET_NZ16(D);
}
@ -2692,14 +2693,14 @@ OP_HANDLER( std_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(D);
WM16(EAD,&pD);
WM16(m68_state, EAD,&pD);
}
/* $eE LDU (LDS) indexed -**0- */
OP_HANDLER( ldu_ix )
{
fetch_effective_address(m68_state);
U=RM16(EAD);
U=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(U);
}
@ -2708,7 +2709,7 @@ OP_HANDLER( ldu_ix )
OP_HANDLER( lds_ix )
{
fetch_effective_address(m68_state);
S=RM16(EAD);
S=RM16(m68_state, EAD);
CLR_NZV;
SET_NZ16(S);
m68_state->int_state |= M6809_LDS;
@ -2720,7 +2721,7 @@ OP_HANDLER( stu_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(U);
WM16(EAD,&pU);
WM16(m68_state, EAD,&pU);
}
/* $10eF STS indexed -**0- */
@ -2729,7 +2730,7 @@ OP_HANDLER( sts_ix )
fetch_effective_address(m68_state);
CLR_NZV;
SET_NZ16(S);
WM16(EAD,&pS);
WM16(m68_state, EAD,&pS);
}
/* $f0 SUBB extended ?**** */
@ -2872,7 +2873,7 @@ OP_HANDLER( std_ex )
CLR_NZV;
SET_NZ16(D);
EXTENDED;
WM16(EAD,&pD);
WM16(m68_state, EAD,&pD);
}
/* $fE LDU (LDS) extended -**0- */
@ -2898,7 +2899,7 @@ OP_HANDLER( stu_ex )
CLR_NZV;
SET_NZ16(U);
EXTENDED;
WM16(EAD,&pU);
WM16(m68_state, EAD,&pU);
}
/* $10fF STS extended -**0- */
@ -2907,7 +2908,7 @@ OP_HANDLER( sts_ex )
CLR_NZV;
SET_NZ16(S);
EXTENDED;
WM16(EAD,&pS);
WM16(m68_state, EAD,&pS);
}
/* $10xx opcodes */
@ -2967,7 +2968,7 @@ OP_HANDLER( pref10 )
case 0xfe: lds_ex(m68_state); m68_state->icount-=7; break;
case 0xff: sts_ex(m68_state); m68_state->icount-=7; break;
default: illegal(m68_state); break;
default: IIError(m68_state); break;
}
}
@ -2992,8 +2993,7 @@ OP_HANDLER( pref11 )
case 0xb3: cmpu_ex(m68_state); m68_state->icount-=8; break;
case 0xbc: cmps_ex(m68_state); m68_state->icount-=8; break;
default: illegal(m68_state); break;
default: IIError(m68_state); break;
}
}

247
src/emu/cpu/m6809/m6809.c
View File

@ -70,6 +70,8 @@
*****************************************************************************/
#define NO_LEGACY_MEMORY_HANDLERS 1
#include "debugger.h"
#include "m6809.h"
@ -95,16 +97,26 @@ struct _m68_state_t
UINT8 cc;
UINT8 ireg; /* First opcode */
UINT8 irq_state[2];
int extra_cycles; /* cycles used up by interrupts */
cpu_irq_callback irq_callback;
const device_config *device;
const m6809_config *config;
int icount;
PAIR ea; /* effective address */
const m6809_config *config;
/* Memory spaces */
const address_space *program;
UINT8 int_state; /* SYNC and CWAI flags */
UINT8 nmi_state;
};
static void check_irq_lines( m68_state_t *m68_state );
static void IIError(m68_state_t *m68_state);
INLINE void fetch_effective_address( m68_state_t *m68_state );
/* flag bits in the cc register */
#define CC_C 0x01 /* Carry */
#define CC_V 0x02 /* Overflow */
@ -151,11 +163,30 @@ struct _m68_state_t
#define M6809_SYNC 16 /* set when SYNC is waiting for an interrupt */
#define M6809_LDS 32 /* set when LDS occured at least once */
/* these are re-defined in m68_state->h TO RAM, ROM or functions in cpuintrf.c */
#define RM(Addr) M6809_RDMEM(Addr)
#define WM(Addr,Value) M6809_WRMEM(Addr,Value)
#define ROP(Addr) M6809_RDOP(Addr)
#define ROP_ARG(Addr) M6809_RDOP_ARG(Addr)
/****************************************************************************/
/* Read a byte from given memory location */
/****************************************************************************/
#define RM(Addr) ((unsigned)memory_read_byte_8be(m68_state->program, Addr))
/****************************************************************************/
/* Write a byte to given memory location */
/****************************************************************************/
#define WM(Addr,Value) (memory_write_byte_8be(m68_state->program, Addr,Value))
/****************************************************************************/
/* Z80_RDOP() is identical to Z80_RDMEM() except it is used for reading */
/* opcodes. In case of system with memory mapped I/O, this function can be */
/* used to greatly speed up emulation */
/****************************************************************************/
#define ROP(Addr) ((unsigned)memory_decrypted_read_byte(m68_state->program, Addr))
/****************************************************************************/
/* Z80_RDOP_ARG() is identical to Z80_RDOP() except it is used for reading */
/* opcode arguments. This difference can be used to support systems that */
/* use different encoding mechanisms for opcodes and opcode arguments */
/****************************************************************************/
#define ROP_ARG(Addr) ((unsigned)memory_raw_read_byte(m68_state->program, Addr))
/* macros to access memory */
#define IMMBYTE(b) b = ROP_ARG(PCD); PC++
@ -229,9 +260,9 @@ struct _m68_state_t
/* macros for convenience */
#define DIRBYTE(b) {DIRECT;b=RM(EAD);}
#define DIRWORD(w) {DIRECT;w.d=RM16(EAD);}
#define DIRWORD(w) {DIRECT;w.d=RM16(m68_state, EAD);}
#define EXTBYTE(b) {EXTENDED;b=RM(EAD);}
#define EXTWORD(w) {EXTENDED;w.d=RM16(EAD);}
#define EXTWORD(w) {EXTENDED;w.d=RM16(m68_state, EAD);}
/* macros for branch instructions */
#define BRANCH(f) { \
@ -257,15 +288,13 @@ struct _m68_state_t
/* macros for setting/getting registers in TFR/EXG instructions */
INLINE void fetch_effective_address( m68_state_t *m68_state );
INLINE UINT32 RM16( UINT32 Addr )
INLINE UINT32 RM16(m68_state_t *m68_state, UINT32 Addr )
{
UINT32 result = RM(Addr) << 8;
return result | RM((Addr+1)&0xffff);
}
INLINE void WM16( UINT32 Addr, PAIR *p )
INLINE void WM16( m68_state_t *m68_state, UINT32 Addr, PAIR *p )
{
WM( Addr, p->b.h );
WM( (Addr+1)&0xffff, p->b.l );
@ -276,7 +305,7 @@ static void UpdateState(m68_state_t *m68_state)
/* compatibility with 6309 */
}
static void CHECK_IRQ_LINES(m68_state_t *m68_state)
static void check_irq_lines(m68_state_t *m68_state)
{
if( m68_state->irq_state[M6809_IRQ_LINE] != CLEAR_LINE ||
m68_state->irq_state[M6809_FIRQ_LINE] != CLEAR_LINE )
@ -298,7 +327,7 @@ static void CHECK_IRQ_LINES(m68_state_t *m68_state)
m68_state->extra_cycles += 10; /* subtract +10 cycles */
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(0xfff6);
PCD=RM16(m68_state, 0xfff6);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, M6809_FIRQ_LINE);
}
@ -326,7 +355,7 @@ static void CHECK_IRQ_LINES(m68_state_t *m68_state)
m68_state->extra_cycles += 19; /* subtract +19 cycles */
}
CC |= CC_II; /* inhibit IRQ */
PCD=RM16(0xfff8);
PCD=RM16(m68_state, 0xfff8);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, M6809_IRQ_LINE);
}
@ -337,7 +366,6 @@ static void CHECK_IRQ_LINES(m68_state_t *m68_state)
/****************************************************************************
* Get all registers in given buffer
****************************************************************************/
static CPU_GET_CONTEXT( m6809 )
{
}
@ -347,12 +375,6 @@ static CPU_GET_CONTEXT( m6809 )
****************************************************************************/
static CPU_SET_CONTEXT( m6809 )
{
m68_state_t *m68_state = src;
CHANGE_PC;
CHECK_IRQ_LINES(m68_state);
UpdateState(m68_state);
}
@ -374,6 +396,10 @@ static CPU_INIT( m6809 )
m68_state->irq_callback = irqcallback;
m68_state->device = device;
m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
/* setup regtable */
state_save_register_item("m6809", device->tag, 0, PC);
state_save_register_item("m6809", device->tag, 0, PPC);
state_save_register_item("m6809", device->tag, 0, D);
@ -403,10 +429,10 @@ static CPU_RESET( m6809 )
DPD = 0; /* Reset direct page register */
CC |= CC_II; /* IRQ disabled */
CC |= CC_IF; /* FIRQ disabled */
CC |= CC_II; /* IRQ disabled */
CC |= CC_IF; /* FIRQ disabled */
PCD = RM16(0xfffe);
PCD = RM16(m68_state, 0xfffe);
CHANGE_PC;
UpdateState(m68_state);
}
@ -452,7 +478,7 @@ static void set_irq_line(m68_state_t *m68_state, int irqline, int state)
m68_state->extra_cycles += 19; /* subtract +19 cycles next time */
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD = RM16(0xfffc);
PCD = RM16(m68_state, 0xfffc);
CHANGE_PC;
}
else if (irqline < 2)
@ -460,7 +486,7 @@ static void set_irq_line(m68_state_t *m68_state, int irqline, int state)
LOG(("M6809#%d set_irq_line %d, %d\n", cpunum_get_active(), irqline, state));
m68_state->irq_state[irqline] = state;
if (state == CLEAR_LINE) return;
CHECK_IRQ_LINES(m68_state);
check_irq_lines(m68_state);
}
}
@ -469,7 +495,6 @@ static void set_irq_line(m68_state_t *m68_state, int irqline, int state)
****************************************************************************/
#include "6809tbl.c"
/* includes the actual opcode implementations */
#include "6809ops.c"
/* execute instructions on this CPU until icount expires */
@ -480,6 +505,8 @@ static CPU_EXECUTE( m6809 ) /* NS 970908 */
m68_state->icount = cycles - m68_state->extra_cycles;
m68_state->extra_cycles = 0;
check_irq_lines(m68_state);
if (m68_state->int_state & (M6809_CWAI | M6809_SYNC))
{
debugger_instruction_hook(device->machine, PCD);
@ -500,16 +527,16 @@ static CPU_EXECUTE( m6809 ) /* NS 970908 */
{
case 0x00: neg_di(m68_state); break;
case 0x01: neg_di(m68_state); break; /* undocumented */
case 0x02: illegal(m68_state); break;
case 0x02: IIError(m68_state); break;
case 0x03: com_di(m68_state); break;
case 0x04: lsr_di(m68_state); break;
case 0x05: illegal(m68_state); break;
case 0x05: IIError(m68_state); break;
case 0x06: ror_di(m68_state); break;
case 0x07: asr_di(m68_state); break;
case 0x08: asl_di(m68_state); break;
case 0x09: rol_di(m68_state); break;
case 0x0a: dec_di(m68_state); break;
case 0x0b: illegal(m68_state); break;
case 0x0b: IIError(m68_state); break;
case 0x0c: inc_di(m68_state); break;
case 0x0d: tst_di(m68_state); break;
case 0x0e: jmp_di(m68_state); break;
@ -518,14 +545,14 @@ static CPU_EXECUTE( m6809 ) /* NS 970908 */
case 0x11: pref11(m68_state); break;
case 0x12: nop(m68_state); break;
case 0x13: sync(m68_state); break;
case 0x14: illegal(m68_state); break;
case 0x15: illegal(m68_state); break;
case 0x14: IIError(m68_state); break;
case 0x15: IIError(m68_state); break;
case 0x16: lbra(m68_state); break;
case 0x17: lbsr(m68_state); break;
case 0x18: illegal(m68_state); break;
case 0x18: IIError(m68_state); break;
case 0x19: daa(m68_state); break;
case 0x1a: orcc(m68_state); break;
case 0x1b: illegal(m68_state); break;
case 0x1b: IIError(m68_state); break;
case 0x1c: andcc(m68_state); break;
case 0x1d: sex(m68_state); break;
case 0x1e: exg(m68_state); break;
@ -554,74 +581,74 @@ static CPU_EXECUTE( m6809 ) /* NS 970908 */
case 0x35: puls(m68_state); break;
case 0x36: pshu(m68_state); break;
case 0x37: pulu(m68_state); break;
case 0x38: illegal(m68_state); break;
case 0x38: IIError(m68_state); break;
case 0x39: rts(m68_state); break;
case 0x3a: abx(m68_state); break;
case 0x3b: rti(m68_state); break;
case 0x3c: cwai(m68_state); break;
case 0x3d: mul(m68_state); break;
case 0x3e: illegal(m68_state); break;
case 0x3e: IIError(m68_state); break;
case 0x3f: swi(m68_state); break;
case 0x40: nega(m68_state); break;
case 0x41: illegal(m68_state); break;
case 0x42: illegal(m68_state); break;
case 0x41: IIError(m68_state); break;
case 0x42: IIError(m68_state); break;
case 0x43: coma(m68_state); break;
case 0x44: lsra(m68_state); break;
case 0x45: illegal(m68_state); break;
case 0x45: IIError(m68_state); break;
case 0x46: rora(m68_state); break;
case 0x47: asra(m68_state); break;
case 0x48: asla(m68_state); break;
case 0x49: rola(m68_state); break;
case 0x4a: deca(m68_state); break;
case 0x4b: illegal(m68_state); break;
case 0x4b: IIError(m68_state); break;
case 0x4c: inca(m68_state); break;
case 0x4d: tsta(m68_state); break;
case 0x4e: illegal(m68_state); break;
case 0x4e: IIError(m68_state); break;
case 0x4f: clra(m68_state); break;
case 0x50: negb(m68_state); break;
case 0x51: illegal(m68_state); break;
case 0x52: illegal(m68_state); break;
case 0x51: IIError(m68_state); break;
case 0x52: IIError(m68_state); break;
case 0x53: comb(m68_state); break;
case 0x54: lsrb(m68_state); break;
case 0x55: illegal(m68_state); break;
case 0x55: IIError(m68_state); break;
case 0x56: rorb(m68_state); break;
case 0x57: asrb(m68_state); break;
case 0x58: aslb(m68_state); break;
case 0x59: rolb(m68_state); break;
case 0x5a: decb(m68_state); break;
case 0x5b: illegal(m68_state); break;
case 0x5b: IIError(m68_state); break;
case 0x5c: incb(m68_state); break;
case 0x5d: tstb(m68_state); break;
case 0x5e: illegal(m68_state); break;
case 0x5e: IIError(m68_state); break;
case 0x5f: clrb(m68_state); break;
case 0x60: neg_ix(m68_state); break;
case 0x61: illegal(m68_state); break;
case 0x62: illegal(m68_state); break;
case 0x61: IIError(m68_state); break;
case 0x62: IIError(m68_state); break;
case 0x63: com_ix(m68_state); break;
case 0x64: lsr_ix(m68_state); break;
case 0x65: illegal(m68_state); break;
case 0x65: IIError(m68_state); break;
case 0x66: ror_ix(m68_state); break;
case 0x67: asr_ix(m68_state); break;
case 0x68: asl_ix(m68_state); break;
case 0x69: rol_ix(m68_state); break;
case 0x6a: dec_ix(m68_state); break;
case 0x6b: illegal(m68_state); break;
case 0x6b: IIError(m68_state); break;
case 0x6c: inc_ix(m68_state); break;
case 0x6d: tst_ix(m68_state); break;
case 0x6e: jmp_ix(m68_state); break;
case 0x6f: clr_ix(m68_state); break;
case 0x70: neg_ex(m68_state); break;
case 0x71: illegal(m68_state); break;
case 0x72: illegal(m68_state); break;
case 0x71: IIError(m68_state); break;
case 0x72: IIError(m68_state); break;
case 0x73: com_ex(m68_state); break;
case 0x74: lsr_ex(m68_state); break;
case 0x75: illegal(m68_state); break;
case 0x75: IIError(m68_state); break;
case 0x76: ror_ex(m68_state); break;
case 0x77: asr_ex(m68_state); break;
case 0x78: asl_ex(m68_state); break;
case 0x79: rol_ex(m68_state); break;
case 0x7a: dec_ex(m68_state); break;
case 0x7b: illegal(m68_state); break;
case 0x7b: IIError(m68_state); break;
case 0x7c: inc_ex(m68_state); break;
case 0x7d: tst_ex(m68_state); break;
case 0x7e: jmp_ex(m68_state); break;
@ -757,7 +784,7 @@ static CPU_EXECUTE( m6809 ) /* NS 970908 */
}
#else
(*m6809_main[m68_state->ireg])(m68_state);
#endif
#endif /* BIG_SWITCH */
m68_state->icount -= cycles1[m68_state->ireg];
} while( m68_state->icount > 0 );
@ -922,29 +949,29 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0x87: EA=0; break; /* ILLEGAL*/
case 0x88: IMMBYTE(EA); EA=X+SIGNED(EA); break; /* this is a hack to make Vectrex work. It should be m68_state->icount-=1. Dunno where the cycle was lost :( */
case 0x89: IMMWORD(EAP); EA+=X; break;
case 0x8a: EA=0; break; /* ILLEGAL*/
case 0x8a: EA=0; break; /* IIError*/
case 0x8b: EA=X+D; break;
case 0x8c: IMMBYTE(EA); EA=PC+SIGNED(EA); break;
case 0x8d: IMMWORD(EAP); EA+=PC; break;
case 0x8e: EA=0; break; /* ILLEGAL*/
case 0x8f: IMMWORD(EAP); break;
case 0x90: EA=X; X++; EAD=RM16(EAD); break; /* Indirect ,R+ not in my specs */
case 0x91: EA=X; X+=2; EAD=RM16(EAD); break;
case 0x92: X--; EA=X; EAD=RM16(EAD); break;
case 0x93: X-=2; EA=X; EAD=RM16(EAD); break;
case 0x94: EA=X; EAD=RM16(EAD); break;
case 0x95: EA=X+SIGNED(B); EAD=RM16(EAD); break;
case 0x96: EA=X+SIGNED(A); EAD=RM16(EAD); break;
case 0x90: EA=X; X++; EAD=RM16(m68_state, EAD); break; /* Indirect ,R+ not in my specs */
case 0x91: EA=X; X+=2; EAD=RM16(m68_state, EAD); break;
case 0x92: X--; EA=X; EAD=RM16(m68_state, EAD); break;
case 0x93: X-=2; EA=X; EAD=RM16(m68_state, EAD); break;
case 0x94: EA=X; EAD=RM16(m68_state, EAD); break;
case 0x95: EA=X+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0x96: EA=X+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0x97: EA=0; break; /* ILLEGAL*/
case 0x98: IMMBYTE(EA); EA=X+SIGNED(EA); EAD=RM16(EAD); break;
case 0x99: IMMWORD(EAP); EA+=X; EAD=RM16(EAD); break;
case 0x98: IMMBYTE(EA); EA=X+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0x99: IMMWORD(EAP); EA+=X; EAD=RM16(m68_state, EAD); break;
case 0x9a: EA=0; break; /* ILLEGAL*/
case 0x9b: EA=X+D; EAD=RM16(EAD); break;
case 0x9c: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0x9d: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0x9b: EA=X+D; EAD=RM16(m68_state, EAD); break;
case 0x9c: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0x9d: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0x9e: EA=0; break; /* ILLEGAL*/
case 0x9f: IMMWORD(EAP); EAD=RM16(EAD); break;
case 0x9f: IMMWORD(EAP); EAD=RM16(m68_state, EAD); break;
case 0xa0: EA=Y; Y++; break;
case 0xa1: EA=Y; Y+=2; break;
@ -963,22 +990,22 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0xae: EA=0; break; /* ILLEGAL*/
case 0xaf: IMMWORD(EAP); break;
case 0xb0: EA=Y; Y++; EAD=RM16(EAD); break;
case 0xb1: EA=Y; Y+=2; EAD=RM16(EAD); break;
case 0xb2: Y--; EA=Y; EAD=RM16(EAD); break;
case 0xb3: Y-=2; EA=Y; EAD=RM16(EAD); break;
case 0xb4: EA=Y; EAD=RM16(EAD); break;
case 0xb5: EA=Y+SIGNED(B); EAD=RM16(EAD); break;
case 0xb6: EA=Y+SIGNED(A); EAD=RM16(EAD); break;
case 0xb0: EA=Y; Y++; EAD=RM16(m68_state, EAD); break;
case 0xb1: EA=Y; Y+=2; EAD=RM16(m68_state, EAD); break;
case 0xb2: Y--; EA=Y; EAD=RM16(m68_state, EAD); break;
case 0xb3: Y-=2; EA=Y; EAD=RM16(m68_state, EAD); break;
case 0xb4: EA=Y; EAD=RM16(m68_state, EAD); break;
case 0xb5: EA=Y+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0xb6: EA=Y+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0xb7: EA=0; break; /* ILLEGAL*/
case 0xb8: IMMBYTE(EA); EA=Y+SIGNED(EA); EAD=RM16(EAD); break;
case 0xb9: IMMWORD(EAP); EA+=Y; EAD=RM16(EAD); break;
case 0xb8: IMMBYTE(EA); EA=Y+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xb9: IMMWORD(EAP); EA+=Y; EAD=RM16(m68_state, EAD); break;
case 0xba: EA=0; break; /* ILLEGAL*/
case 0xbb: EA=Y+D; EAD=RM16(EAD); break;
case 0xbc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0xbd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0xbb: EA=Y+D; EAD=RM16(m68_state, EAD); break;
case 0xbc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xbd: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0xbe: EA=0; break; /* ILLEGAL*/
case 0xbf: IMMWORD(EAP); EAD=RM16(EAD); break;
case 0xbf: IMMWORD(EAP); EAD=RM16(m68_state, EAD); break;
case 0xc0: EA=U; U++; break;
case 0xc1: EA=U; U+=2; break;
@ -997,22 +1024,22 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0xce: EA=0; break; /*ILLEGAL*/
case 0xcf: IMMWORD(EAP); break;
case 0xd0: EA=U; U++; EAD=RM16(EAD); break;
case 0xd1: EA=U; U+=2; EAD=RM16(EAD); break;
case 0xd2: U--; EA=U; EAD=RM16(EAD); break;
case 0xd3: U-=2; EA=U; EAD=RM16(EAD); break;
case 0xd4: EA=U; EAD=RM16(EAD); break;
case 0xd5: EA=U+SIGNED(B); EAD=RM16(EAD); break;
case 0xd6: EA=U+SIGNED(A); EAD=RM16(EAD); break;
case 0xd0: EA=U; U++; EAD=RM16(m68_state, EAD); break;
case 0xd1: EA=U; U+=2; EAD=RM16(m68_state, EAD); break;
case 0xd2: U--; EA=U; EAD=RM16(m68_state, EAD); break;
case 0xd3: U-=2; EA=U; EAD=RM16(m68_state, EAD); break;
case 0xd4: EA=U; EAD=RM16(m68_state, EAD); break;
case 0xd5: EA=U+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0xd6: EA=U+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0xd7: EA=0; break; /*ILLEGAL*/
case 0xd8: IMMBYTE(EA); EA=U+SIGNED(EA); EAD=RM16(EAD); break;
case 0xd9: IMMWORD(EAP); EA+=U; EAD=RM16(EAD); break;
case 0xd8: IMMBYTE(EA); EA=U+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xd9: IMMWORD(EAP); EA+=U; EAD=RM16(m68_state, EAD); break;
case 0xda: EA=0; break; /*ILLEGAL*/
case 0xdb: EA=U+D; EAD=RM16(EAD); break;
case 0xdc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0xdd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0xdb: EA=U+D; EAD=RM16(m68_state, EAD); break;
case 0xdc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xdd: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0xde: EA=0; break; /*ILLEGAL*/
case 0xdf: IMMWORD(EAP); EAD=RM16(EAD); break;
case 0xdf: IMMWORD(EAP); EAD=RM16(m68_state, EAD); break;
case 0xe0: EA=S; S++; break;
case 0xe1: EA=S; S+=2; break;
@ -1031,22 +1058,22 @@ INLINE void fetch_effective_address( m68_state_t *m68_state )
case 0xee: EA=0; break; /*ILLEGAL*/
case 0xef: IMMWORD(EAP); break;
case 0xf0: EA=S; S++; EAD=RM16(EAD); break;
case 0xf1: EA=S; S+=2; EAD=RM16(EAD); break;
case 0xf2: S--; EA=S; EAD=RM16(EAD); break;
case 0xf3: S-=2; EA=S; EAD=RM16(EAD); break;
case 0xf4: EA=S; EAD=RM16(EAD); break;
case 0xf5: EA=S+SIGNED(B); EAD=RM16(EAD); break;
case 0xf6: EA=S+SIGNED(A); EAD=RM16(EAD); break;
case 0xf0: EA=S; S++; EAD=RM16(m68_state, EAD); break;
case 0xf1: EA=S; S+=2; EAD=RM16(m68_state, EAD); break;
case 0xf2: S--; EA=S; EAD=RM16(m68_state, EAD); break;
case 0xf3: S-=2; EA=S; EAD=RM16(m68_state, EAD); break;
case 0xf4: EA=S; EAD=RM16(m68_state, EAD); break;
case 0xf5: EA=S+SIGNED(B); EAD=RM16(m68_state, EAD); break;
case 0xf6: EA=S+SIGNED(A); EAD=RM16(m68_state, EAD); break;
case 0xf7: EA=0; break; /*ILLEGAL*/
case 0xf8: IMMBYTE(EA); EA=S+SIGNED(EA); EAD=RM16(EAD); break;
case 0xf9: IMMWORD(EAP); EA+=S; EAD=RM16(EAD); break;
case 0xf8: IMMBYTE(EA); EA=S+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xf9: IMMWORD(EAP); EA+=S; EAD=RM16(m68_state, EAD); break;
case 0xfa: EA=0; break; /*ILLEGAL*/
case 0xfb: EA=S+D; EAD=RM16(EAD); break;
case 0xfc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
case 0xfd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
case 0xfb: EA=S+D; EAD=RM16(m68_state, EAD); break;
case 0xfc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(m68_state, EAD); break;
case 0xfd: IMMWORD(EAP); EA+=PC; EAD=RM16(m68_state, EAD); break;
case 0xfe: EA=0; break; /*ILLEGAL*/
case 0xff: IMMWORD(EAP); EAD=RM16(EAD); break;
case 0xff: IMMWORD(EAP); EAD=RM16(m68_state, EAD); break;
}
m68_state->icount -= index_cycle_em[postbyte];
}
@ -1071,7 +1098,7 @@ static CPU_SET_INFO( m6809 )
case CPUINFO_INT_REGISTER + M6809_PC: PC = info->i; CHANGE_PC; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + M6809_S: S = info->i; break;
case CPUINFO_INT_REGISTER + M6809_CC: CC = info->i; CHECK_IRQ_LINES(m68_state); break;
case CPUINFO_INT_REGISTER + M6809_CC: CC = info->i; check_irq_lines(m68_state); break;
case CPUINFO_INT_REGISTER + M6809_U: U = info->i; break;
case CPUINFO_INT_REGISTER + M6809_A: A = info->i; break;
case CPUINFO_INT_REGISTER + M6809_B: B = info->i; break;

32
src/emu/cpu/m6809/m6809.h
View File

@ -21,41 +21,9 @@ CPU_GET_INFO( m6809 );
/* M6809e has LIC line to indicate opcode/data fetch */
CPU_GET_INFO( m6809e );
/****************************************************************************/
/* Read a byte from given memory location */
/****************************************************************************/
/* ASG 971005 -- changed to program_read_byte_8/cpu_writemem16 */
#define M6809_RDMEM(Addr) ((unsigned)program_read_byte_8be(Addr))
/****************************************************************************/
/* Write a byte to given memory location */
/****************************************************************************/
#define M6809_WRMEM(Addr,Value) (program_write_byte_8be(Addr,Value))
/****************************************************************************/
/* Z80_RDOP() is identical to Z80_RDMEM() except it is used for reading */
/* opcodes. In case of system with memory mapped I/O, this function can be */
/* used to greatly speed up emulation */
/****************************************************************************/
#define M6809_RDOP(Addr) ((unsigned)program_decrypted_read_byte(Addr))
/****************************************************************************/
/* Z80_RDOP_ARG() is identical to Z80_RDOP() except it is used for reading */
/* opcode arguments. This difference can be used to support systems that */
/* use different encoding mechanisms for opcodes and opcode arguments */
/****************************************************************************/
#define M6809_RDOP_ARG(Addr) ((unsigned)program_raw_read_byte(Addr))
#ifndef FALSE
# define FALSE 0
#endif
#ifndef TRUE
# define TRUE (!FALSE)
#endif
CPU_DISASSEMBLE( m6809 );
typedef struct _m6809_config m6809_config;
struct _m6809_config
{