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VS2015 fixes in SPARC, disassemble VIS II SIAM (nw)

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This commit is contained in:
Vas Crabb 2016-06-23 13:06:12 +10:00
parent c19d656617
commit 2d01c1abdc
4 changed files with 34 additions and 14 deletions
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10
src/devices/cpu/sparc/mb86901.cpp
View File

@ -1778,7 +1778,7 @@ void mb86901_device::execute_store(UINT32 op)
//byte_mask = 15;
data0 = REG(RD);
}
else if (STH or STHA)
else if (STH || STHA)
{
if ((address & 3) == 0)
{
@ -1791,7 +1791,7 @@ void mb86901_device::execute_store(UINT32 op)
data0 = REG(RD);
}
}
else if (STB or STBA)
else if (STB || STBA)
{
if ((address & 3) == 0)
{
@ -2029,7 +2029,7 @@ void mb86901_device::execute_load(UINT32 op)
}
}
UINT32 word0;
UINT32 word0(0);
if (!m_trap)
{
UINT32 data = read_sized_word(addr_space, address, (LD || LDD || LDA || LDDA) ? 4 : ((LDUH || LDSH || LDUHA || LDSHA) ? 2 : 1));
@ -2193,7 +2193,7 @@ void mb86901_device::execute_ldstub(UINT32 op)
}
}
UINT32 data;
UINT32 data(0);
if (!m_trap)
{
while (m_pb_block_ldst_byte || m_pb_block_ldst_word)
@ -2257,7 +2257,7 @@ void mb86901_device::execute_ldstub(UINT32 op)
{
word = (data >> 8) & 0xff;
}
else if ((address & 3) == 3)
else // if ((address & 3) == 3)
{
word = data & 0xff;
}

10
src/devices/cpu/sparc/sparcdasm.cpp
View File

@ -479,6 +479,7 @@ inline void sparc_disassembler::print(char *&output, const char *fmt, ...)
sparc_disassembler::sparc_disassembler(unsigned version)
: m_version(version)
, m_vis_level(0)
, m_op_field_width(9)
, m_branch_desc{
EMPTY_BRANCH_DESC,
@ -537,6 +538,7 @@ sparc_disassembler::sparc_disassembler(unsigned version)
void sparc_disassembler::enable_vis1()
{
m_vis_level = std::max(m_vis_level, 1U);
m_op_field_width = std::max(m_op_field_width, 12);
add_vis_op_desc(VIS1_OP_DESC);
add_state_reg_desc(VIS1_STATE_REG_DESC);
@ -547,6 +549,7 @@ void sparc_disassembler::enable_vis1()
void sparc_disassembler::enable_vis2()
{
enable_vis1();
m_vis_level = std::max(m_vis_level, 2U);
add_vis_op_desc(VIS2_OP_DESC);
}
@ -1052,7 +1055,7 @@ offs_t sparc_disassembler::dasm_fpop2(char *buf, offs_t pc, UINT32 op) const
case 1: mnemonic = "fmovs"; shift = false; break;
case 2: mnemonic = "fmovd"; shift = true; break;
case 3: mnemonic = "fmovq"; shift = true; break;
default: mnemonic = nullptr;
default: mnemonic = nullptr; shift = false; break;
}
if (mnemonic)
{
@ -1114,6 +1117,11 @@ offs_t sparc_disassembler::dasm_impdep1(char *buf, offs_t pc, UINT32 op) const
dasm_vis_arg(buf, args, it->second.rd, RD);
return 4 | DASMFLAG_SUPPORTED;
}
else if ((m_vis_level >= 2) && (OPF == 0x081))
{
print(buf, "%-*s0x%x", m_op_field_width, "siam", IAMODE);
return 4 | DASMFLAG_SUPPORTED;
}
// TODO: driver hook for other kinds of coprocessor?

25
src/devices/cpu/sparc/sparcdasm.h
View File

@ -17,6 +17,8 @@ class sparc_disassembler
public:
struct asi_desc
{
asi_desc() { }
asi_desc(const char *name_, const char *desc_) : name(name_), desc(desc_) { }
const char *name = nullptr;
const char *desc = nullptr;
};
@ -24,14 +26,18 @@ public:
struct state_reg_desc
{
bool reserved = false;
const char *read_name = nullptr;
const char *write_name = nullptr;
state_reg_desc() { }
state_reg_desc(bool reserved_, const char *read_name_, const char *write_name_) : reserved(reserved_), read_name(read_name_), write_name(write_name_) { }
bool reserved = false;
const char *read_name = nullptr;
const char *write_name = nullptr;
};
typedef std::map<UINT8, state_reg_desc> state_reg_desc_map;
struct prftch_desc
{
prftch_desc() { }
prftch_desc(const char *name_) : name(name_) { }
const char *name = nullptr;
};
typedef std::map<UINT8, prftch_desc> prftch_desc_map;
@ -107,6 +113,8 @@ private:
struct fpop1_desc
{
fpop1_desc() { }
fpop1_desc(bool three_op_, bool rs1_shift_, bool rs2_shift_, bool rd_shift_, const char *mnemonic_) : three_op(three_op_), rs1_shift(rs1_shift_), rs2_shift(rs2_shift_), rd_shift(rd_shift_), mnemonic(mnemonic_) { }
bool three_op = true;
bool rs1_shift = false;
bool rs2_shift = false;
@ -117,6 +125,8 @@ private:
struct fpop2_desc
{
fpop2_desc() { }
fpop2_desc(bool int_rs1_, bool shift_, const char *mnemonic_) : int_rs1(int_rs1_), shift(shift_), mnemonic(mnemonic_) { }
bool int_rs1 = false;
bool shift = false;
const char *mnemonic = nullptr;
@ -125,6 +135,8 @@ private:
struct ldst_desc
{
ldst_desc() { }
ldst_desc(bool rd_first_, bool alternate_, char rd_alt_reg_, bool rd_shift_, const char *mnemonic_, const char *g0_synth_) : rd_first(rd_first_), alternate(alternate_), rd_alt_reg(rd_alt_reg_), rd_shift(rd_shift_), mnemonic(mnemonic_), g0_synth(g0_synth_) { }
bool rd_first = false;
bool alternate = false;
char rd_alt_reg = '\0';
@ -137,6 +149,8 @@ private:
struct vis_op_desc
{
enum arg { X, I, Fs, Fd };
vis_op_desc() { }
vis_op_desc(arg rs1_, arg rs2_, arg rd_, bool collapse_, const char *mnemonic_) : rs1(rs1_), rs2(rs2_), rd(rd_), collapse(collapse_), mnemonic(mnemonic_) { }
arg rs1 = X;
arg rs2 = X;
arg rd = X;
@ -206,6 +220,7 @@ private:
static const vis_op_desc_map::value_type VIS2_OP_DESC[];
unsigned m_version;
unsigned m_vis_level;
int m_op_field_width;
branch_desc m_branch_desc[8];
int_op_desc_map m_int_op_desc;
@ -218,8 +233,4 @@ private:
vis_op_desc_map m_vis_op_desc;
};
CPU_DISASSEMBLE( sparcv7 );
CPU_DISASSEMBLE( sparcv8 );
CPU_DISASSEMBLE( sparcv9 );
#endif // MAME_DEVICES_CPU_SPARC_SPARC_DASM_H

3
src/devices/cpu/sparc/sparcdefs.h
View File

@ -102,11 +102,12 @@
#define SIMM13 (INT32(op << 19) >> 19)
#define SIMM11 (INT32(op << 21) >> 21)
#define SIMM10 (INT32(op << 22) >> 22)
#define SIMM8 (INT32(op << 24) >> 24)
#define IMM7 (op & 0x7f)
#define SIMM7 (INT32(op << 25) >> 25)
#define SIMM8 (INT32(op << 24) >> 24)
#define SHCNT32 (op & 31)
#define SHCNT64 (op & 63)
#define IAMODE (op & 0x7)
#define USEIMM ((op >> 13) & 1)
#define USEEXT ((op >> 12) & 1)