mirror of
https://github.com/holub/mame
synced 2025-05-24 23:05:32 +03:00
Done some work on the Forte Card driver,not yet working.
This commit is contained in:
parent
8d4cad0b8c
commit
2d1fbafcdf
@ -2,6 +2,14 @@
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/*
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/*
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TODO:
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-eeprom
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-bankswitch
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-inputs
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-missing color proms?
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-----------------------------------------------------
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Forte Card (POKER GAME)
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Forte Card (POKER GAME)
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CPU SGS Z8400AB1 (Z80ACPU)
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CPU SGS Z8400AB1 (Z80ACPU)
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@ -15,39 +23,113 @@ dip 1X8
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*/
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*/
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#include "driver.h"
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#include "driver.h"
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#include "machine/eeprom.h"
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#include "sound/ay8910.h"
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#include "machine/8255ppi.h"
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static UINT8 *fortecar_ram;
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static UINT8 *fortecar_ram;
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static int bank;
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static WRITE8_HANDLER( fortecar_videoregs_w )
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{
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static UINT8 address;
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if(offset == 0)
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address = data;
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else
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{
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switch(address)
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{
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default:
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logerror("Video Register %02x called with %02x data\n",address,data);
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}
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}
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}
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static WRITE8_DEVICE_HANDLER( ppi0_portc_w )
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{
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eeprom_write_bit(data & 0x04);
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eeprom_set_cs_line((data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
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eeprom_set_clock_line((data & 0x02) ? ASSERT_LINE : CLEAR_LINE);
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}
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static READ8_DEVICE_HANDLER( ppi0_portc_r )
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{
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// popmessage("%04x",activecpu_get_pc());
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return (~(eeprom_read_bit()<<1) & 2);
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}
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static READ8_DEVICE_HANDLER( ppi0_porta_r )
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{
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return input_port_read(device->machine, "DSW1");
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}
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static READ8_DEVICE_HANDLER( ppi0_portb_r )
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{
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return input_port_read(device->machine, "IN2");
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}
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static const ppi8255_interface ppi0intf =
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{
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ppi0_porta_r, ppi0_portb_r, ppi0_portc_r,
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NULL, NULL, ppi0_portc_w
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};
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static WRITE8_HANDLER( rom_bank_w )
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{
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int new_bank = (data&0xff)>>0;
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if(bank!=new_bank) {
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UINT8 *ROM = memory_region(machine, "main");
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UINT32 bankaddress;
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bank = new_bank;
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bankaddress = 0x10000 + 0x40 * bank;
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memory_set_bankptr(1, &ROM[bankaddress]);
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}
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}
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static WRITE8_HANDLER( ayporta_w )
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{
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}
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static WRITE8_HANDLER( ayportb_w )
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{
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}
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static const ay8910_interface ay8910_config =
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{
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AY8910_LEGACY_OUTPUT,
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AY8910_DEFAULT_LOADS,
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NULL,
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NULL,
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ayporta_w,
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ayportb_w
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};
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static ADDRESS_MAP_START( fortecar_map, ADDRESS_SPACE_PROGRAM, 8 )
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static ADDRESS_MAP_START( fortecar_map, ADDRESS_SPACE_PROGRAM, 8 )
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AM_RANGE(0x0000, 0xc7ff) AM_READ(SMH_ROM)
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AM_RANGE(0x0000, 0xbfff) AM_ROM
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AM_RANGE(0xd000, 0xd1ff) AM_RAM
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AM_RANGE(0xc000, 0xc7ff) AM_READWRITE(SMH_BANK1, SMH_ROM) //bank
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AM_RANGE(0xd000, 0xd7ff) AM_RAM
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AM_RANGE(0xd800, 0xffff) AM_RAM AM_BASE(&fortecar_ram)
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AM_RANGE(0xd800, 0xffff) AM_RAM AM_BASE(&fortecar_ram)
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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#ifdef UNUSED_FUNCTION
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READ8_HANDLER( fortecar_read62 )
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{
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return mame_rand(machine);
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}
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#endif
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static ADDRESS_MAP_START( fortecar_ports, ADDRESS_SPACE_IO, 8 )
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static ADDRESS_MAP_START( fortecar_ports, ADDRESS_SPACE_IO, 8 )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x40, 0x40) AM_WRITE(SMH_NOP)
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AM_RANGE(0x20, 0x21) AM_WRITE(fortecar_videoregs_w) // MC6845?
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AM_RANGE(0x41, 0x41) AM_WRITE(SMH_NOP)
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AM_RANGE(0x40, 0x40) AM_READWRITE(ay8910_read_port_0_r, ay8910_control_port_0_w)
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// AM_RANGE(0x62, 0x62) AM_READ(fortecar_read62) // nvram eeprom?
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AM_RANGE(0x41, 0x41) AM_WRITE(ay8910_write_port_0_w)
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AM_RANGE(0x60, 0x62) AM_DEVREADWRITE(PPI8255, "fcppi0", ppi8255_r, ppi8255_w)//M5L8255AP
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AM_RANGE(0x81, 0x81) AM_WRITE(rom_bank_w) //completely wrong,might not be there...
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AM_RANGE(0xa0, 0xa0) AM_READ_PORT("IN0") //written too,multiplexer?
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AM_RANGE(0xa1, 0xa1) AM_READ_PORT("IN1")
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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static INPUT_PORTS_START( fortecar )
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static INPUT_PORTS_START( fortecar )
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PORT_START("IN0") /* 8bit */
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PORT_START("IN0") /* 8bit */
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PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
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PORT_DIPNAME( 0x01, 0x01, "IN0" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
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PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
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@ -73,7 +155,59 @@ static INPUT_PORTS_START( fortecar )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_START("IN1") /* 8bit */
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PORT_START("IN1") /* 8bit */
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PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
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PORT_DIPNAME( 0x01, 0x01, "IN1" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_START("IN2") /* 8bit */
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PORT_DIPNAME( 0x01, 0x01, "IN2" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_START("DSW1") /* 8bit */
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PORT_DIPNAME( 0x01, 0x01, "DSW1" )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
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PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
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@ -122,16 +256,17 @@ static VIDEO_UPDATE(fortecar)
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{
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{
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int x,y,count;
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int x,y,count;
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count = 0;
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count = 0;
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fillbitmap(bitmap,0,cliprect);
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for (y=0;y<32;y++)
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{
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for(x=0;x<64;x++)
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{
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int tile;
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tile = fortecar_ram[0x800+(count*4)+1];
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for (y=0;y<0x1e;y++)
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{
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for(x=0;x<0x4b;x++)
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{
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int tile,color;
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drawgfx(bitmap,screen->machine->gfx[0],tile,0,0,0,x*8,y*8,cliprect,TRANSPARENCY_PEN,0);
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tile = fortecar_ram[(count*4)+1] | (fortecar_ram[(count*4)+2]<<8);
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color = fortecar_ram[(count*4)+3];
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drawgfx(bitmap,screen->machine->gfx[0],tile,color,0,0,x*8,y*8,cliprect,TRANSPARENCY_NONE,0);
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count++;
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count++;
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}
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}
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@ -139,13 +274,16 @@ static VIDEO_UPDATE(fortecar)
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return 0;
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return 0;
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}
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}
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static MACHINE_RESET(fortecar)
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{
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bank = -1;
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}
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static MACHINE_DRIVER_START( fortecar )
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static MACHINE_DRIVER_START( fortecar )
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/* basic machine hardware */
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/* basic machine hardware */
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MDRV_CPU_ADD("main", Z80,8000000) /* ? MHz */
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MDRV_CPU_ADD("main", Z80,6000000) /* ? MHz */
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MDRV_CPU_PROGRAM_MAP(fortecar_map,0)
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MDRV_CPU_PROGRAM_MAP(fortecar_map,0)
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MDRV_CPU_IO_MAP(fortecar_ports,0)
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MDRV_CPU_IO_MAP(fortecar_ports,0)
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MDRV_CPU_VBLANK_INT("main", nmi_line_pulse)
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MDRV_CPU_VBLANK_INT("main", nmi_line_pulse)
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/* video hardware */
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/* video hardware */
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@ -153,19 +291,31 @@ static MACHINE_DRIVER_START( fortecar )
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MDRV_SCREEN_REFRESH_RATE(60)
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MDRV_SCREEN_REFRESH_RATE(60)
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MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
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MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
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MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
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MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
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MDRV_SCREEN_SIZE(512, 256)
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MDRV_SCREEN_SIZE(640, 256)
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MDRV_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
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MDRV_SCREEN_VISIBLE_AREA(0, 640-1, 0, 256-1)
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MDRV_MACHINE_RESET(fortecar)
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MDRV_NVRAM_HANDLER(93C46) //GOLDSTAR GM76C256ALL-70
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MDRV_PPI8255_ADD("fcppi0", ppi0intf)
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MDRV_GFXDECODE(fortecar)
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MDRV_GFXDECODE(fortecar)
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MDRV_PALETTE_LENGTH(0x100)
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MDRV_PALETTE_LENGTH(0x100)
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MDRV_VIDEO_START(fortecar)
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MDRV_VIDEO_START(fortecar)
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MDRV_VIDEO_UPDATE(fortecar)
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MDRV_VIDEO_UPDATE(fortecar)
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MDRV_SPEAKER_STANDARD_MONO("mono")
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MDRV_SOUND_ADD("ay", AY8910, 1500000)
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MDRV_SOUND_CONFIG(ay8910_config)
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MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
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MACHINE_DRIVER_END
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MACHINE_DRIVER_END
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ROM_START( fortecar )
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ROM_START( fortecar )
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ROM_REGION( 0x10000, "main", 0 )
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ROM_REGION( 0x14000, "main", 0 )
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ROM_LOAD( "fortecar.u7", 0x00000, 0x10000, CRC(2a4b3429) SHA1(8fa630dac949e758678a1a36b05b3412abe8ae16) )
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ROM_LOAD( "fortecar.u7", 0x00000, 0x0c000, CRC(2a4b3429) SHA1(8fa630dac949e758678a1a36b05b3412abe8ae16) )
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ROM_CONTINUE( 0x10000, 0x04000 )
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ROM_REGION( 0x30000, "gfx1", 0 )
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ROM_REGION( 0x30000, "gfx1", 0 )
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ROM_LOAD( "fortecar.u38", 0x00000, 0x10000, CRC(c2090690) SHA1(f0aa8935b90a2ab6043555ece69f926372246648) )
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ROM_LOAD( "fortecar.u38", 0x00000, 0x10000, CRC(c2090690) SHA1(f0aa8935b90a2ab6043555ece69f926372246648) )
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@ -173,5 +323,8 @@ ROM_START( fortecar )
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ROM_LOAD( "fortecar.u40", 0x20000, 0x10000, CRC(9693bb83) SHA1(e3e3bc750c89a1edd1072ce3890b2ce498dec633) )
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ROM_LOAD( "fortecar.u40", 0x20000, 0x10000, CRC(9693bb83) SHA1(e3e3bc750c89a1edd1072ce3890b2ce498dec633) )
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ROM_END
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ROM_END
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static DRIVER_INIT( fortecar )
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{
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}
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GAME( 19??, fortecar, 0, fortecar, fortecar, 0, ROT0, "unknown", "Forte Card",GAME_NO_SOUND|GAME_NOT_WORKING )
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GAME( 19??, fortecar, 0, fortecar, fortecar, fortecar, ROT0, "Fortex LTD", "Forte Card",GAME_NOT_WORKING | GAME_WRONG_COLORS)
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