add b5000 cpu core file placeholders

hash/ngpc.xml

@@ -1571,7 +1571,7 @@ NEOP00220 NeoGeo Cup '98 Plus (Euro) [confirmed?]
 	</software>
 
 	<!-- Developer: SNK -->
-	<software name="svccard2">
+	<software name="svccard2" supported="partial"> <!-- gets stuck -->
 		<!-- NGPC only -->
 		<description>SNK vs. Capcom - Card Fighters 2 - Expand Edition (Jpn)</description>
 		<year>2001</year>

scripts/src/cpu.lua

@@ -2852,6 +2852,26 @@ if opt_tool(CPUS, "SUPERFX") then
 	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/superfx/sfx_dasm.h")
 end
 
+--------------------------------------------------
+-- Rockwell B5000 family
+--@src/devices/cpu/b5000/b5000.h,CPUS["B5000"] = true
+--------------------------------------------------
+
+if CPUS["B5000"] then
+	files {
+		MAME_DIR .. "src/devices/cpu/b5000/b5000base.cpp",
+		MAME_DIR .. "src/devices/cpu/b5000/b5000base.h",
+		MAME_DIR .. "src/devices/cpu/b5000/b5000.cpp",
+		MAME_DIR .. "src/devices/cpu/b5000/b5000.h",
+		MAME_DIR .. "src/devices/cpu/b5000/b5000op.cpp",
+	}
+end
+
+if opt_tool(CPUS, "B5000") then
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/b5000/b5000d.cpp")
+	table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/b5000/b5000d.h")
+end
+
 --------------------------------------------------
 -- Rockwell PPS-4
 --@src/devices/cpu/pps4/pps4.h,CPUS["PPS4"] = true

scripts/target/mame/arcade.lua

@@ -120,6 +120,7 @@ CPUS["UNSP"] = true
 CPUS["HCD62121"] = true
 CPUS["PPS4"] = true
 --CPUS["PPS41"] = true
+--CPUS["B5000"] = true
 CPUS["UPD7725"] = true
 CPUS["HD61700"] = true
 CPUS["LC8670"] = true

scripts/target/mame/mess.lua

@@ -123,6 +123,7 @@ CPUS["UNSP"] = true
 CPUS["HCD62121"] = true
 CPUS["PPS4"] = true
 CPUS["PPS41"] = true
+CPUS["B5000"] = true
 CPUS["UPD7725"] = true
 CPUS["HD61700"] = true
 CPUS["LC8670"] = true

src/devices/cpu/b5000/b5000.cpp

@@ -0,0 +1,61 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  Rockwell B5000 MCU core implementation
+
+*/
+
+#include "emu.h"
+#include "b5000.h"
+
+#include "b5000d.h"
+
+
+DEFINE_DEVICE_TYPE(B5000, b5000_cpu_device, "b5000", "Rockwell B5000")
+
+
+// constructor
+b5000_cpu_device::b5000_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
+	b5000_base_device(mconfig, B5000, tag, owner, clock, 9, address_map_constructor(FUNC(b5000_cpu_device::program_map), this), 6, address_map_constructor(FUNC(b5000_cpu_device::data_map), this))
+{ }
+
+
+// internal memory maps
+void b5000_cpu_device::program_map(address_map &map)
+{
+	map(0x000, 0x1ff).rom();
+}
+
+void b5000_cpu_device::data_map(address_map &map)
+{
+	map(0x00, 0x3f).ram();
+}
+
+
+// disasm
+std::unique_ptr<util::disasm_interface> b5000_cpu_device::create_disassembler()
+{
+	return std::make_unique<b5000_disassembler>();
+}
+
+
+// initialize
+void b5000_cpu_device::device_start()
+{
+	b5000_base_device::device_start();
+}
+
+void b5000_cpu_device::device_reset()
+{
+	b5000_base_device::device_reset();
+}
+
+
+//-------------------------------------------------
+//  execute
+//-------------------------------------------------
+
+void b5000_cpu_device::execute_one()
+{
+}

src/devices/cpu/b5000/b5000.h

@@ -0,0 +1,54 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  Rockwell B5000 MCU core implementation
+
+*/
+
+#ifndef MAME_CPU_B5000_B5000_H
+#define MAME_CPU_B5000_B5000_H
+
+#pragma once
+
+#include "b5000base.h"
+
+// pinout reference
+
+/*
+
+*/
+
+class b5000_cpu_device : public b5000_base_device
+{
+public:
+	b5000_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override;
+	virtual void device_reset() override;
+
+	// device_disasm_interface overrides
+	virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
+
+	// device_execute_interface overrides
+	virtual void execute_one() override;
+
+	void data_map(address_map &map);
+	void program_map(address_map &map);
+
+	// opcode helpers
+	u8 ram_r();
+	void ram_w(u8 data);
+	void pop_pc();
+	void push_pc();
+
+	// opcode handlers
+
+};
+
+
+DECLARE_DEVICE_TYPE(B5000, b5000_cpu_device)
+
+#endif // MAME_CPU_B5000_B5000_H

src/devices/cpu/b5000/b5000base.cpp

@@ -0,0 +1,106 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  Rockwell B5000 family MCU cores
+
+*/
+
+#include "emu.h"
+#include "b5000base.h"
+
+#include "debugger.h"
+
+
+b5000_base_device::b5000_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data) :
+	cpu_device(mconfig, type, tag, owner, clock),
+	m_program_config("program", ENDIANNESS_LITTLE, 8, prgwidth, 0, program),
+	m_data_config("data", ENDIANNESS_LITTLE, 8, datawidth, 0, data),
+	m_prgwidth(prgwidth),
+	m_datawidth(datawidth)
+{ }
+
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+enum
+{
+	B5000_PC=1
+};
+
+void b5000_base_device::device_start()
+{
+	m_program = &space(AS_PROGRAM);
+	m_data = &space(AS_DATA);
+	m_prgmask = (1 << m_prgwidth) - 1;
+	m_datamask = (1 << m_datawidth) - 1;
+
+	// resolve callbacks
+	//..
+
+	// zerofill
+	m_pc = 0;
+	m_prev_pc = 0;
+	m_op = 0;
+	m_skip = false;
+
+	// register for savestates
+	save_item(NAME(m_pc));
+	save_item(NAME(m_prev_pc));
+	save_item(NAME(m_op));
+	save_item(NAME(m_skip));
+
+	// register state for debugger
+	state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%03X").noshow();
+	state_add(STATE_GENPCBASE, "CURPC", m_prev_pc).formatstr("%03X").noshow();
+
+	state_add(B5000_PC, "PC", m_pc).formatstr("%03X");
+
+	set_icountptr(m_icount);
+}
+
+device_memory_interface::space_config_vector b5000_base_device::memory_space_config() const
+{
+	return space_config_vector {
+		std::make_pair(AS_PROGRAM, &m_program_config),
+		std::make_pair(AS_DATA,    &m_data_config)
+	};
+}
+
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void b5000_base_device::device_reset()
+{
+	m_pc = m_prev_pc = 0;
+	m_skip = false;
+}
+
+
+//-------------------------------------------------
+//  execute
+//-------------------------------------------------
+
+void b5000_base_device::increment_pc()
+{
+	// low part is LFSR
+	int feed = ((m_pc & 0x3e) == 0) ? 1 : 0;
+	feed ^= (m_pc >> 1 ^ m_pc) & 1;
+	m_pc = (m_pc & ~0x3f) | (m_pc >> 1 & 0x1f) | (feed << 5);
+}
+
+void b5000_base_device::execute_run()
+{
+	while (m_icount > 0)
+	{
+		debugger_instruction_hook(m_pc);
+		increment_pc();
+		m_icount--;
+
+		execute_one();
+	}
+}

src/devices/cpu/b5000/b5000base.h

@@ -0,0 +1,62 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  Rockwell B5000 family MCU cores
+
+*/
+
+#ifndef MAME_CPU_B5000_B5000BASE_H
+#define MAME_CPU_B5000_B5000BASE_H
+
+#pragma once
+
+
+class b5000_base_device : public cpu_device
+{
+public:
+	// ...
+
+protected:
+	// construction/destruction
+	b5000_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data);
+
+	// device-level overrides
+	virtual void device_start() override;
+	virtual void device_reset() override;
+
+	// device_execute_interface overrides
+	virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 4 - 1) / 4; } // 4-phase clock
+	virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 4); }
+	virtual u32 execute_min_cycles() const noexcept override { return 1; }
+	virtual u32 execute_max_cycles() const noexcept override { return 2; }
+	virtual void execute_run() override;
+	virtual void execute_one() = 0;
+	void increment_pc();
+
+	// device_memory_interface overrides
+	virtual space_config_vector memory_space_config() const override;
+
+	address_space_config m_program_config;
+	address_space_config m_data_config;
+	address_space *m_program;
+	address_space *m_data;
+
+	int m_icount;
+
+	int m_prgwidth; // ROM/RAM address size
+	int m_datawidth; // "
+	u16 m_prgmask; // "
+	u16 m_datamask; // "
+
+	u16 m_pc;
+	u16 m_prev_pc;
+	u8 m_op;
+
+	bool m_skip;
+
+	// i/o handlers
+};
+
+
+#endif // MAME_CPU_B5000_B5000BASE_H

src/devices/cpu/b5000/b5000d.cpp

@@ -0,0 +1,104 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  Rockwell B5000 family MCU disassembler
+
+*/
+
+#include "emu.h"
+#include "b5000d.h"
+
+// constructor
+
+b5000_common_disassembler::b5000_common_disassembler()
+{
+	// init lfsr pc lut
+	for (u32 i = 0, pc = 0; i < 0x40; i++)
+	{
+		m_l2r[i] = pc;
+		m_r2l[pc] = i;
+		pc = increment_pc(pc);
+	}
+}
+
+offs_t b5000_common_disassembler::increment_pc(offs_t pc)
+{
+	int feed = ((pc & 0x3e) == 0) ? 1 : 0;
+	feed ^= (pc >> 1 ^ pc) & 1;
+	return (pc & ~0x3f) | (pc >> 1 & 0x1f) | (feed << 5);
+}
+
+
+// common lookup tables
+
+const char *const b5000_common_disassembler::s_name[] =
+{
+	"?", "NOP"
+};
+
+// bitmask for opcode parameter
+const u8 b5000_common_disassembler::s_bits[] =
+{
+	0, 0
+};
+
+const u32 b5000_common_disassembler::s_flags[] =
+{
+	0, 0
+};
+
+
+// common disasm
+
+offs_t b5000_common_disassembler::common_disasm(const u8 *lut_opmap, std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
+{
+	// get raw opcode
+	u8 op = opcodes.r8(pc);
+	u8 instr = lut_opmap[op];
+
+	// get parameter
+	u8 mask = s_bits[instr];
+
+	// disassemble it
+	util::stream_format(stream, "%-8s ", s_name[instr]);
+
+	if (mask > 0)
+	{
+		;
+	}
+
+	return 1 | s_flags[instr] | SUPPORTED;
+}
+
+
+// B5000 disasm
+
+const u8 b5000_disassembler::b5000_opmap[0x100] =
+{
+/*  0        1        2        3        4        5        6        7        8        9        A        B        C        D        E        F  */
+	em_NOP,  0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 0
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 1
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 2
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 3
+
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 4
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 5
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 6
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 7
+
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 8
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // 9
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // A
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // B
+
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // C
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // D
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // E
+	0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       0,       // F
+};
+
+offs_t b5000_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
+{
+	return common_disasm(b5000_opmap, stream, pc, opcodes, params);
+}

src/devices/cpu/b5000/b5000d.h

@@ -0,0 +1,58 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  Rockwell B5000 family MCU disassembler
+
+*/
+
+#ifndef MAME_CPU_B5000_B5000D_H
+#define MAME_CPU_B5000_B5000D_H
+
+#pragma once
+
+
+class b5000_common_disassembler : public util::disasm_interface
+{
+public:
+	b5000_common_disassembler();
+	virtual ~b5000_common_disassembler() = default;
+
+	virtual u32 opcode_alignment() const override { return 1; }
+	virtual u32 interface_flags() const override { return NONLINEAR_PC | PAGED; }
+	virtual u32 page_address_bits() const override { return 6; }
+	virtual offs_t pc_linear_to_real(offs_t pc) const override { return (pc & ~0x3f) | m_l2r[pc & 0x3f]; }
+	virtual offs_t pc_real_to_linear(offs_t pc) const override { return (pc & ~0x3f) | m_r2l[pc & 0x3f]; }
+
+protected:
+	// opcode mnemonics
+	enum e_mnemonics
+	{
+		em_ILL, em_NOP
+	};
+
+	static const char *const s_name[];
+	static const u8 s_bits[];
+	static const u32 s_flags[];
+
+	u8 m_l2r[0x40];
+	u8 m_r2l[0x40];
+
+	offs_t increment_pc(offs_t pc);
+	offs_t common_disasm(const u8 *lut_opmap, std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params);
+};
+
+class b5000_disassembler : public b5000_common_disassembler
+{
+public:
+	b5000_disassembler() = default;
+	virtual ~b5000_disassembler() = default;
+
+	virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override;
+
+private:
+	static const u8 b5000_opmap[0x100];
+
+};
+
+#endif // MAME_CPU_B5000_B5000D_H

src/devices/cpu/b5000/b5000op.cpp

@@ -0,0 +1,34 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+
+// B5000 opcode handlers
+
+#include "emu.h"
+#include "b5000.h"
+
+
+// internal helpers
+
+inline u8 b5000_cpu_device::ram_r()
+{
+	return 0;
+	//return m_data->read_byte(m_b) & 0xf;
+}
+
+inline void b5000_cpu_device::ram_w(u8 data)
+{
+	//m_data->write_byte(m_b, data & 0xf);
+}
+
+void b5000_cpu_device::pop_pc()
+{
+	//m_pc = m_sa;
+}
+
+void b5000_cpu_device::push_pc()
+{
+	//m_sa = m_pc;
+}
+
+
+// opcodes

src/mame/drivers/hh_sm510.cpp

@@ -147,7 +147,7 @@ The MCUs used were not imported from Sharp, but cloned by USSR, renamed to
 #include "gnw_dualh.lh"
 
 //#include "hh_sm510_test.lh" // common test-layout - use external artwork
-//#include "hh_sm500_test.lh" // "
+#include "hh_sm500_test.lh" // "
 
 
 // machine start/reset
@@ -5372,11 +5372,13 @@ INPUT_PORTS_END
 void gamewatch_state::nsmb3(machine_config &config)
 {
 	sm530_common(config, 1000, 1000);
+	config.set_default_layout(layout_hh_sm500_test);
 }
 
 void gamewatch_state::nsmw(machine_config &config)
 {
 	sm530_common(config, 1000, 1000);
+	config.set_default_layout(layout_hh_sm500_test);
 }
 
 // roms

src/mame/layout/hh_sm500_test.lay

@@ -18,13 +18,13 @@ license:CC0
 <!-- build screen -->
 
 	<view name="Test Layout">
-		<bounds left="0" right="10" top="0" bottom="10" />
+		<bounds left="0" right="10" top="0" bottom="12" />
 		<element ref="static_black">
-			<bounds left="0" right="10" top="0" bottom="10" />
+			<bounds left="0" right="10" top="0" bottom="12" />
 		</element>
 
-		<!-- max 9*4*2 matrix -->
+		<!-- max 12*4*2 matrix -->
-		<repeat count="9">
+		<repeat count="12">
 			<param name="y" start="0" increment="1" />
 
 			<!-- h1 -->

src/tools/unidasm.cpp

@@ -28,6 +28,7 @@ using util::BIT;
 #include "cpu/arm7/arm7dasm.h"
 #include "cpu/asap/asapdasm.h"
 #include "cpu/avr8/avr8dasm.h"
+#include "cpu/b5000/b5000.h"
 #include "cpu/bcp/bcpdasm.h"
 #include "cpu/capricorn/capricorn_dasm.h"
 #include "cpu/ccpu/ccpudasm.h"
@@ -390,6 +391,7 @@ static const dasm_table_entry dasm_table[] =
 	{ "avr8",            le,  0, []() -> util::disasm_interface * { return new avr8_disassembler; } },
 	{ "axc51core",       le,  0, []() -> util::disasm_interface * { return new axc51core_disassembler; } },
 	{ "axc208",          le,  0, []() -> util::disasm_interface * { return new ax208_disassembler; } },
+	{ "b5000",           le,  0, []() -> util::disasm_interface * { return new b5000_disassembler; } },
 	{ "capricorn",       le,  0, []() -> util::disasm_interface * { return new capricorn_disassembler; } },
 	{ "ccpu",            le,  0, []() -> util::disasm_interface * { return new ccpu_disassembler; } },
 	{ "cdp1801",         le,  0, []() -> util::disasm_interface * { return new cosmac_disassembler(cosmac_disassembler::TYPE_1801); } },