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https://github.com/holub/mame
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video/pc_vga_matrox.cpp: add screen extension bit hook ups
video/mga2064w.cpp: translate alias space to 32-bits
This commit is contained in:
angelosa
parent
0268ef195e
commit
2dccaba3b4
@ -22,7 +22,7 @@ mga2064w_device::mga2064w_device(const machine_config &mconfig, const char *tag,
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, m_vga_rom(*this, "vga_rom")
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{
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set_ids(0x102b0519, 0x01, 0x030000, 0x00000000);
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m_mgabase1_real_space_config = address_space_config("mgabase1_regs", ENDIANNESS_LITTLE, 8, 14, 0, address_map_constructor(FUNC(mga2064w_device::mgabase1_map), this));
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m_mgabase1_real_space_config = address_space_config("mgabase1_regs", ENDIANNESS_LITTLE, 32, 14, 0, address_map_constructor(FUNC(mga2064w_device::mgabase1_map), this));
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}
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ROM_START( mga2064w )
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@ -128,8 +128,8 @@ void mga2064w_device::mgabase1_map(address_map &map)
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// map(0x1cc0, 0x1cff) DR0-DR15 (DR1-5-9-13 <reserved>)
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// map(0x1e00, 0x1eff) HSTREG Host registers
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// map(0x1e10, 0x1e13) FIFOSTATUS (r/o)
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// map(0x1e14, 0x1e17) Status (r/o)
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map(0x1e10, 0x1e13).r(FUNC(mga2064w_device::fifo_status_r));
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map(0x1e14, 0x1e17).r(FUNC(mga2064w_device::status_r));
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// map(0x1e18, 0x1e1b) ICLEAR
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// map(0x1e1c, 0x1e1f) IEN
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// map(0x1e20, 0x1e23) VCOUNT (r/o)
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@ -146,6 +146,32 @@ void mga2064w_device::mgabase2_map(address_map &map)
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map(0x000000, 0x7fffff).rw(m_svga, FUNC(matrox_vga_device::mem_linear_r), FUNC(matrox_vga_device::mem_linear_w));
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}
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/*
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* MGABASE1 + 1e10h FIFO Status (r/o)
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*
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* ---- -x-- ---- ---- BEMPTY Bus FIFO empty
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* ---- --x- ---- ---- BFULL Bus FIFO full
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* ---- ---- ---x xxxx FIFOCOUNT free locations in FIFO (max: 32)
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*/
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u32 mga2064w_device::fifo_status_r()
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{
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return (1 << 9) | 32;
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}
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/*
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* MGABASE1 + 1e14h Status (r/o)
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*
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* ---- ---- ---- ---x ---- ---- ---- ---- DWGENGSTS
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* ---- ---- ---- ---- ---- ---- -x-- ---- EXTPEN
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* ---- ---- ---- ---- ---- ---- --x- ---- VLINEPEN
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* ---- ---- ---- ---- ---- ---- ---x ---- VSYNCPEN
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* ---- ---- ---- ---- ---- ---- ---- x--- VSYNCSTS
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* ---- ---- ---- ---- ---- ---- ---- -x-- PICKPEN
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*/
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u32 mga2064w_device::status_r()
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{
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return m_svga->vsync_status() << 3;
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}
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// TODO: this should really be a subclass of VGA
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void mga2064w_device::legacy_memory_map(address_map &map)
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@ -153,7 +179,6 @@ void mga2064w_device::legacy_memory_map(address_map &map)
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map(0xa0000, 0xbffff).rw(FUNC(mga2064w_device::vram_r), FUNC(mga2064w_device::vram_w));
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}
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// TODO: card may not even support MDA access
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void mga2064w_device::legacy_io_map(address_map &map)
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{
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map(0, 0x02f).m(m_svga, FUNC(matrox_vga_device::io_map));
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@ -201,12 +226,12 @@ void mga2064w_device::mga_index_w(offs_t offset, u32 data, u32 mem_mask)
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m_mgabase1_real_index &= 0x3ffc;
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}
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u8 mga2064w_device::mga_data_r(offs_t offset)
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u32 mga2064w_device::mga_data_r(offs_t offset, u32 mem_mask)
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{
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return space(AS_IO).read_byte(offset + m_mgabase1_real_index);
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return space(AS_IO).read_dword(m_mgabase1_real_index, mem_mask);
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}
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void mga2064w_device::mga_data_w(offs_t offset, u8 data)
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void mga2064w_device::mga_data_w(offs_t offset, u32 data, u32 mem_mask)
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{
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space(AS_IO).write_byte(offset + m_mgabase1_real_index, data);
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space(AS_IO).write_dword(m_mgabase1_real_index, data, mem_mask);
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}
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@ -40,10 +40,12 @@ private:
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address_space_config m_mgabase1_real_space_config;
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u32 mga_index_r();
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void mga_index_w(offs_t offset, u32 data, u32 mem_mask = ~0);
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u8 mga_data_r(offs_t offset);
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void mga_data_w(offs_t offset, u8 data);
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u32 mga_data_r(offs_t offset, u32 mem_mask = ~0);
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void mga_data_w(offs_t offset, u32 data, u32 mem_mask = ~0);
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u32 m_mgabase1_real_index = 0;
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u32 status_r();
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u32 fifo_status_r();
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};
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DECLARE_DEVICE_TYPE(MGA2064W, mga2064w_device);
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@ -1327,7 +1327,8 @@ void vga_device::vga_vh_ega(bitmap_rgb32 &bitmap, const rectangle &cliprect)
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}
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}
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/* TODO: I'm guessing that in 256 colors mode every pixel actually outputs two pixels. Is it right? */
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// In mode 13h (256 colors) every pixel actually double height/width
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// i.e. a 320x200 is really 640x400
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void vga_device::vga_vh_vga(bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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int height = vga.crtc.maximum_scan_line * (vga.crtc.scan_doubling + 1);
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@ -1335,6 +1336,7 @@ void vga_device::vga_vh_vga(bitmap_rgb32 &bitmap, const rectangle &cliprect)
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int addrmask = vga.crtc.no_wrap ? -1 : 0xffff;
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/* line compare is screen sensitive */
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// FIXME: some clients extends line compare with bit 10
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uint16_t mask_comp = 0x3ff; //| (LINES & 0x300);
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// popmessage("%02x %02x",vga.attribute.pel_shift,vga.sequencer.data[4] & 0x08);
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@ -1806,7 +1808,8 @@ void svga_device::svga_vh_rgb8(bitmap_rgb32 &bitmap, const rectangle &cliprect)
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int height = vga.crtc.maximum_scan_line * (vga.crtc.scan_doubling + 1);
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/* line compare is screen sensitive */
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uint16_t mask_comp = 0x3ff;
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// FIXME: some clients extends line compare with bit 10
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uint16_t mask_comp = 0x3ff;
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int curr_addr = 0;
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// uint16_t line_length;
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// if(vga.crtc.dw)
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@ -31,7 +31,9 @@ void matrox_vga_device::device_reset()
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m_crtcext_index = 0;
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m_crtcext_misc = 0;
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m_crtcext_horz_counter = 0;
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m_mgamode = false;
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m_interlace_mode = false;
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m_truecolor_ctrl = 0x80;
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m_multiplex_ctrl = 0x98;
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}
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@ -60,11 +62,11 @@ void matrox_vga_device::io_3bx_3dx_map(address_map &map)
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// "CRTCEXT*"
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void matrox_vga_device::crtcext_map(address_map &map)
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{
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// map(0x00, 0x00) Address Generator Extensions
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// map(0x01, 0x01) Horizontal Counter Extensions
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// map(0x02, 0x02) Vertical Counter Extensions
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map(0x00, 0x00).rw(FUNC(matrox_vga_device::crtcext0_address_gen_r), FUNC(matrox_vga_device::crtcext0_address_gen_w));
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map(0x01, 0x01).rw(FUNC(matrox_vga_device::crtcext1_horizontal_counter_r), FUNC(matrox_vga_device::crtcext1_horizontal_counter_w));
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map(0x02, 0x02).rw(FUNC(matrox_vga_device::crtcext2_vertical_counter_r), FUNC(matrox_vga_device::crtcext2_vertical_counter_w));
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map(0x03, 0x03).rw(FUNC(matrox_vga_device::crtcext3_misc_r), FUNC(matrox_vga_device::crtcext3_misc_w));
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// CRTCEXT4 Memory Page register
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// CRTCEXT4 Memory Page register
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map(0x04, 0x04).lrw8(
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NAME([this] (offs_t offset) { return svga.bank_w & 0x7f; }),
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NAME([this] (offs_t offset, u8 data) { svga.bank_w = data & 0x7f; })
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@ -75,6 +77,87 @@ void matrox_vga_device::crtcext_map(address_map &map)
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// seems to disable SVGA drawing -> diagnostic check?
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}
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/*
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* CRTCEXT0 Address Generator extensions
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*
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* x--- ---- Interlace mode
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* --xx ---- Offset bits 9-8
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* ---- xxxx Start Address bits 19-16
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*/
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u8 matrox_vga_device::crtcext0_address_gen_r()
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{
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u8 res = ((vga.crtc.start_addr >> 16) & 0xf);
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res |= ((vga.crtc.offset >> 8) & 3) << 4;
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res |= (m_interlace_mode) << 7;
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return res;
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}
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void matrox_vga_device::crtcext0_address_gen_w(offs_t offset, u8 data)
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{
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m_interlace_mode = bool(BIT(data, 7));
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vga.crtc.offset = (vga.crtc.offset & 0xff) | ((data & 0x30) << 4);
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vga.crtc.start_addr = (vga.crtc.start_addr & 0xffff) | ((data & 0xf) << 16);
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if (m_interlace_mode)
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popmessage("MGA2064W: interlace mode enable");
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// recompute_params();
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}
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/*
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* CRTCEXT1 Horizontal Counter Extensions
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*
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* x--- ---- VRSTEN Vertical reset enable
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* -x-- ---- HBLKEND Horizontal end blank bit 6 (MGA mode only)
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* --x- ---- VSYNCOFF
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* ---x ---- HSYNCOFF
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* ---- x--- HRSTEN Horizontal reset enable
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* ---- -x-- HSYNCSTR horizontal retrace start bit 8
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* ---- --x- HBLKSTR horizontal blanking start bit 8
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* ---- ---x HTOTAL bit 8
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*/
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u8 matrox_vga_device::crtcext1_horizontal_counter_r()
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{
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return m_crtcext_horz_counter;
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}
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void matrox_vga_device::crtcext1_horizontal_counter_w(offs_t offset, u8 data)
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{
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// TODO: honor CRTC protect enable
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m_crtcext_horz_counter = data;
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vga.crtc.horz_total = (vga.crtc.horz_total & 0xff) | (BIT(data, 0) << 8);
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vga.crtc.horz_blank_start = (vga.crtc.horz_blank_start & 0xff) | (BIT(data, 1) << 8);
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vga.crtc.horz_retrace_start = (vga.crtc.horz_retrace_start & 0xff) | (BIT(data, 2) << 8);
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vga.crtc.horz_blank_end = (vga.crtc.horz_blank_end & 0x3f) | (BIT(data, 6) << 6);
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logerror("MGA2064W: CRTCEXT1 reset enable %02x syncoff %02x\n",data & 0x88, data & 0x30);
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recompute_params();
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}
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/*
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* CRTCEXT1 Vertical Counter Extensions
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*
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* x--- ---- LINECOMP Line compare bit 10
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* -xx- ---- VSYNCSTR Vertical retrace start bits 11-10
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* ---x x--- VBLKSTR Vertical blank start bits 11-10
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* ---- -x-- VDISPEND Vertical display end bit 10
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* ---- --xx VTOTAL bits 11-10
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*/
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u8 matrox_vga_device::crtcext2_vertical_counter_r()
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{
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return m_crtcext_vert_counter;
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}
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void matrox_vga_device::crtcext2_vertical_counter_w(offs_t offset, u8 data)
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{
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// TODO: honor CRTC protect enable
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m_crtcext_vert_counter = data;
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vga.crtc.vert_total = (vga.crtc.vert_total & 0x3ff) | ((data & 3) << 10);
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vga.crtc.vert_disp_end = (vga.crtc.vert_disp_end & 0x3ff) | (BIT(data, 2) << 10);
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vga.crtc.vert_blank_start = (vga.crtc.vert_blank_start & 0x3ff) | ((data & 0x18) << (10-3));
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vga.crtc.vert_retrace_start = (vga.crtc.vert_retrace_start & 0x3ff) | ((data & 0x60) << (10-5));
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vga.crtc.line_compare = (vga.crtc.line_compare & 0x3ff) | (BIT(data, 7) << 10);
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recompute_params();
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}
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/*
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* CRTCEXT3 Miscellaneous
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*
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@ -107,15 +190,19 @@ void matrox_vga_device::crtcext3_misc_w(offs_t offset, u8 data)
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m_mgamode = bool(BIT(data, 7));
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}
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// RAMDAC
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// - paired with a Texas Instruments TVP3026 here -> a superset of INMOS IMSG176/IMSG178
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// - integrated with a superset in G400 at least
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/*
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* RAMDAC
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* - paired with a Texas Instruments TVP3026 here -> a superset of INMOS IMSG176/IMSG178
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* - integrated and customized with supersets in the next iteration (Mystique MGA-1064SG) and onward
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*/
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void matrox_vga_device::ramdac_ext_map(address_map &map)
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{
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// map(0x00, 0x00).rw(FUNC(matrox_vga_device::ramdac_write_index_r), FUNC(matrox_vga_device::ramdac_write_index_w));
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// map(0x01, 0x01).rw(FUNC(matrox_vga_device::ramdac_data_r), FUNC(matrox_vga_device::ramdac_data_w));
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// map(0x02, 0x02).rw(FUNC(matrox_vga_device::ramdac_mask_r), FUNC(matrox_vga_device::ramdac_mask_w));
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// map(0x03, 0x03).rw(FUNC(matrox_vga_device::ramdac_read_index_r), FUNC(matrox_vga_device::ramdac_read_index_w));
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map(0x00, 0x00).rw(FUNC(matrox_vga_device::ramdac_write_index_r), FUNC(matrox_vga_device::ramdac_write_index_w));
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map(0x01, 0x01).rw(FUNC(matrox_vga_device::ramdac_data_r), FUNC(matrox_vga_device::ramdac_data_w));
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map(0x02, 0x02).rw(FUNC(matrox_vga_device::ramdac_mask_r), FUNC(matrox_vga_device::ramdac_mask_w));
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map(0x03, 0x03).lr8(
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NAME([this] (offs_t offset) { return vga.dac.read_index; })
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).w(FUNC(matrox_vga_device::ramdac_read_index_w));
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// map(0x04, 0x04) Cursor/Overscan Color Write Index
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// map(0x05, 0x05) Cursor/Overscan Color data
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// map(0x07, 0x07) Cursor/Overscan Color Read Index
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@ -255,6 +342,8 @@ void matrox_vga_device::flush_true_color_mode()
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popmessage("TVP3026: Unemulated RGB%c 4-4-4-4 mode", m_truecolor_ctrl & 0x40 ? "X" : "O");
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break;
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}
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recompute_params();
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}
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uint8_t matrox_vga_device::mem_r(offs_t offset)
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@ -274,10 +363,29 @@ void matrox_vga_device::mem_w(offs_t offset, uint8_t data)
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svga_device::mem_w(offset, data);
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}
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void matrox_vga_device::recompute_params()
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{
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u8 xtal_select = (vga.miscellaneous_output & 0x0c) >> 2;
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int xtal;
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switch(xtal_select & 3)
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{
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case 0: xtal = XTAL(25'174'800).value(); break;
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case 1: xtal = XTAL(28'636'363).value(); break;
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// TODO: stub, derives from RAMDAC PLLs
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case 2:
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default:
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xtal = XTAL(50'000'000).value();
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break;
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}
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recompute_params_clock(1, xtal);
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}
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uint16_t matrox_vga_device::offset()
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{
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// TODO: shifts depending on RAMDAC mode + CRTCEXT0 bits 5-4
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if (svga.rgb16_en)
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return (vga.crtc.offset << 5);
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return (vga.crtc.offset << 4);
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return svga_device::offset();
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}
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@ -19,12 +19,17 @@ public:
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virtual uint8_t mem_r(offs_t offset) override;
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virtual void mem_w(offs_t offset, uint8_t data) override;
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// TODO: polarity
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bool vsync_status() { return vga_vblank(); }
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protected:
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virtual void io_3bx_3dx_map(address_map &map) override;
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virtual void device_reset() override;
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virtual uint16_t offset() override;
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virtual void recompute_params() override;
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void crtcext_map(address_map &map);
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void ramdac_indexed_map(address_map &map);
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@ -36,12 +41,21 @@ private:
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address_space_config m_ramdac_indexed_space_config;
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// CRTC
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u8 crtcext0_address_gen_r();
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void crtcext0_address_gen_w(offs_t offset, u8 data);
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u8 crtcext1_horizontal_counter_r();
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void crtcext1_horizontal_counter_w(offs_t offset, u8 data);
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u8 crtcext2_vertical_counter_r();
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void crtcext2_vertical_counter_w(offs_t offset, u8 data);
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u8 crtcext3_misc_r();
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void crtcext3_misc_w(offs_t offset, u8 data);
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u8 m_crtcext_index = 0;
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u8 m_crtcext_misc = 0;
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u8 m_crtcext_horz_counter = 0;
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u8 m_crtcext_vert_counter = 0;
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bool m_mgamode = false;
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bool m_interlace_mode = false;
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// RAMDAC
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u8 ramdac_ext_indexed_r();
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