mirror of
https://github.com/holub/mame
synced 2025-07-01 00:09:18 +03:00
z80scc: general cleanup and backport of z80sio improvements part I
This commit is contained in:
Joakim Larsson Edstrom
parent
8ff47b6ec3
commit
2e9b62d4bd
@ -90,8 +90,9 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
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#define LOG_DCD (1U << 8)
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#define LOG_SYNC (1U << 9)
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//#define VERBOSE (LOG_INT|LOG_READ|LOG_SETUP|LOG_TX|LOG_CMD)
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//#define LOG_OUTPUT_FUNC printf
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//#define VERBOSE (LOG_TX)
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//#define LOG_OUTPUT_STREAM std::cout
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#include "logmacro.h"
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#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__)
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@ -111,10 +112,8 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
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#ifdef _MSC_VER
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#define FUNCNAME __func__
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#define LLFORMAT "%I64d"
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#else
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#define FUNCNAME __PRETTY_FUNCTION__
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#define LLFORMAT "%lld"
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#endif
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/* LOCAL _BRG is set in z80scc.h, local timer based BRG is not complete and will be removed if not needed for synchrounous mode */
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@ -157,10 +156,24 @@ MACHINE_CONFIG_END
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// LIVE DEVICE
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//**************************************************************************
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inline void z80scc_channel::out_txd_cb(int state)
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{
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m_uart->m_out_txd_cb[m_index](state);
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}
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inline void z80scc_channel::out_rts_cb(int state)
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{
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m_uart->m_out_rts_cb[m_index](state);
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}
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inline void z80scc_channel::out_dtr_cb(int state)
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{
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m_uart->m_out_dtr_cb[m_index](state);
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}
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//-------------------------------------------------
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// z80scc_device - constructor
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//-------------------------------------------------
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z80scc_device::z80scc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t variant)
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: device_t(mconfig, type, tag, owner, clock),
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device_z80daisy_interface(mconfig, *this),
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@ -170,21 +183,14 @@ z80scc_device::z80scc_device(const machine_config &mconfig, device_type type, co
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m_txca(0),
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m_rxcb(0),
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m_txcb(0),
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m_out_txda_cb(*this),
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m_out_dtra_cb(*this),
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m_out_rtsa_cb(*this),
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m_out_wreqa_cb(*this),
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m_out_synca_cb(*this),
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m_out_txdb_cb(*this),
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m_out_dtrb_cb(*this),
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m_out_rtsb_cb(*this),
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m_out_wreqb_cb(*this),
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m_out_syncb_cb(*this),
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m_out_txd_cb{ { *this }, { *this } },
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m_out_dtr_cb{ { *this }, { *this } },
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m_out_rts_cb{ { *this }, { *this } },
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m_out_wreq_cb{ { *this }, { *this } },
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m_out_sync_cb{ { *this }, { *this } },
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m_out_rxdrq_cb{ { *this }, { *this } },
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m_out_txdrq_cb{ { *this }, { *this } },
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m_out_int_cb(*this),
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m_out_rxdrqa_cb(*this),
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m_out_txdrqa_cb(*this),
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m_out_rxdrqb_cb(*this),
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m_out_txdrqb_cb(*this),
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m_variant(variant),
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m_wr0_ptrbits(0),
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m_cputag(nullptr)
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@ -238,29 +244,37 @@ scc8523l_device::scc8523l_device(const machine_config &mconfig, const char *tag,
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{
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}
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//-------------------------------------------------
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// device_resolve_objects - device-specific setup
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//-------------------------------------------------
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void z80scc_device::device_resolve_objects()
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{
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LOG("%s\n", FUNCNAME);
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// resolve callbacks
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m_out_txd_cb[CHANNEL_A].resolve_safe();
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m_out_dtr_cb[CHANNEL_A].resolve_safe();
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m_out_rts_cb[CHANNEL_A].resolve_safe();
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m_out_wreq_cb[CHANNEL_A].resolve_safe();
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m_out_sync_cb[CHANNEL_A].resolve_safe();
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m_out_txd_cb[CHANNEL_B].resolve_safe();
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m_out_dtr_cb[CHANNEL_B].resolve_safe();
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m_out_rts_cb[CHANNEL_B].resolve_safe();
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m_out_wreq_cb[CHANNEL_B].resolve_safe();
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m_out_sync_cb[CHANNEL_B].resolve_safe();
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m_out_rxdrq_cb[CHANNEL_A].resolve_safe();
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m_out_txdrq_cb[CHANNEL_A].resolve_safe();
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m_out_rxdrq_cb[CHANNEL_B].resolve_safe();
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m_out_txdrq_cb[CHANNEL_B].resolve_safe();
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m_out_int_cb.resolve_safe();
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void z80scc_device::device_start()
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{
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LOGSETUP("%s\n", FUNCNAME);
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// resolve callbacks
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m_out_txda_cb.resolve_safe();
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m_out_dtra_cb.resolve_safe();
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m_out_rtsa_cb.resolve_safe();
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m_out_wreqa_cb.resolve_safe();
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m_out_synca_cb.resolve_safe();
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m_out_txdb_cb.resolve_safe();
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m_out_dtrb_cb.resolve_safe();
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m_out_rtsb_cb.resolve_safe();
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m_out_wreqb_cb.resolve_safe();
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m_out_syncb_cb.resolve_safe();
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m_out_int_cb.resolve_safe();
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m_out_rxdrqa_cb.resolve_safe();
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m_out_txdrqa_cb.resolve_safe();
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m_out_rxdrqb_cb.resolve_safe();
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m_out_txdrqb_cb.resolve_safe();
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LOG("%s", FUNCNAME);
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// state saving
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save_item(NAME(m_int_state));
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@ -274,16 +288,15 @@ void z80scc_device::device_start()
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void z80scc_device::device_reset()
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{
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LOGSETUP("%s %s \n",tag(), FUNCNAME);
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LOG("%s %s \n",tag(), FUNCNAME);
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// Do channel reset on both channels
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m_chanA->reset();
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m_chanB->reset();
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// Fix hardware reset values for registers where it differs from channel reset values
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// Hardware reset values for registers where it differs from channel reset values
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m_wr9 &= 0x3c;
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m_wr9 |= 0xc0;
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m_chanA->m_wr10 = 0x00;
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@ -429,7 +442,6 @@ void z80scc_device::z80daisy_irq_reti()
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//-------------------------------------------------
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// check_interrupts -
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//-------------------------------------------------
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void z80scc_device::check_interrupts()
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{
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int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
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@ -441,7 +453,6 @@ void z80scc_device::check_interrupts()
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//-------------------------------------------------
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// reset_interrupts -
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//-------------------------------------------------
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void z80scc_device::reset_interrupts()
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{
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LOGINT("%s %s \n",tag(), FUNCNAME);
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@ -597,7 +608,6 @@ int z80scc_device::update_extint(int index)
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//-------------------------------------------------
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// m1_r - interrupt acknowledge
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//-------------------------------------------------
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int z80scc_device::m1_r()
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{
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return z80daisy_irq_ack();
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@ -760,7 +770,6 @@ WRITE8_MEMBER( z80scc_device::cd_ba_w )
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//-------------------------------------------------
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// ba_cd_r - Universal Bus read
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//-------------------------------------------------
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READ8_MEMBER( z80scc_device::ba_cd_r )
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{
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int ba = BIT(offset, 1);
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@ -782,7 +791,6 @@ READ8_MEMBER( z80scc_device::ba_cd_r )
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//-------------------------------------------------
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// ba_cd_w - Universal Bus write
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//-------------------------------------------------
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WRITE8_MEMBER( z80scc_device::ba_cd_w )
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{
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int ba = BIT(offset, 1);
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@ -807,7 +815,6 @@ WRITE8_MEMBER( z80scc_device::ba_cd_w )
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//-------------------------------------------------
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// ba_cd_inv_r - Universal Bus read
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//-------------------------------------------------
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READ8_MEMBER( z80scc_device::ba_cd_inv_r )
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{
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int ba = BIT(offset, 1);
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@ -829,7 +836,6 @@ READ8_MEMBER( z80scc_device::ba_cd_inv_r )
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//-------------------------------------------------
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// ba_cd_inv_w - Universal Bus read
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//-------------------------------------------------
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WRITE8_MEMBER( z80scc_device::ba_cd_inv_w )
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{
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int ba = BIT(offset, 1);
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@ -858,7 +864,6 @@ WRITE8_MEMBER( z80scc_device::ba_cd_inv_w )
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//-------------------------------------------------
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// SCC_channel - constructor
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//-------------------------------------------------
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z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, Z80SCC_CHANNEL, tag, owner, clock),
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device_serial_interface(mconfig, *this),
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@ -906,7 +911,6 @@ z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, d
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//-------------------------------------------------
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// start - channel startup
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//-------------------------------------------------
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void z80scc_channel::device_start()
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{
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LOGSETUP("%s\n", FUNCNAME);
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@ -987,7 +991,6 @@ void z80scc_channel::device_start()
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//-------------------------------------------------
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// reset - reset channel status
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//-------------------------------------------------
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void z80scc_channel::device_reset()
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{
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LOGSETUP("%s\n", FUNCNAME);
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@ -1003,7 +1006,7 @@ void z80scc_channel::device_reset()
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m_wr4 = 0x04;
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m_wr5 = 0x00;
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if (m_uart->m_variant & (z80scc_device::TYPE_SCC85C30 | z80scc_device::SET_ESCC))
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m_wr7 = 0x20;
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m_wr7 = 0x20;
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// WR9,WR10,WR11 and WR14 has a different hard reset (see z80scc_device::device_reset()) values
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m_uart->m_wr9 &= 0xdf;
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m_wr10 &= 0x60;
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@ -1020,9 +1023,8 @@ void z80scc_channel::device_reset()
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m_rr10 &= 0x40;
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// reset external lines
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set_rts(m_wr5 & WR5_RTS ? 0 : 1);
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set_dtr(m_wr14 & WR14_DTR_REQ_FUNC ? 0 : (m_wr5 & WR5_DTR ? 0 : 1));
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out_rts_cb(m_rts = m_wr5 & WR5_RTS ? 0 : 1);
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out_dtr_cb(m_dtr = m_wr14 & WR14_DTR_REQ_FUNC ? 0 : (m_wr5 & WR5_DTR ? 0 : 1));
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// reset interrupts
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if (m_index == z80scc_device::CHANNEL_A)
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{
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@ -1067,50 +1069,38 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para
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//-------------------------------------------------
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// tra_callback -
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//-------------------------------------------------
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void z80scc_channel::tra_callback()
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{
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if (!(m_wr5 & WR5_TX_ENABLE))
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{
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LOG(LLFORMAT " %s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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LOGTX("%s \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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// transmit mark
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if (m_index == z80scc_device::CHANNEL_A)
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m_uart->m_out_txda_cb(1);
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else
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m_uart->m_out_txdb_cb(1);
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out_txd_cb(1);
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}
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else if (m_wr5 & WR5_SEND_BREAK)
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{
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LOG(LLFORMAT " %s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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LOGTX("%s \"%s \"Channel %c send break 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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// transmit break
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if (m_index == z80scc_device::CHANNEL_A)
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m_uart->m_out_txda_cb(0);
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else
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m_uart->m_out_txdb_cb(0);
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out_txd_cb(0);
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}
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else if (!is_transmit_register_empty())
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{
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int db = transmit_register_get_data_bit();
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LOG(LLFORMAT " %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, db, m_wr5);
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LOGTX("%s \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, db, m_wr5);
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// transmit data
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if (m_index == z80scc_device::CHANNEL_A)
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m_uart->m_out_txda_cb(db);
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else
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m_uart->m_out_txdb_cb(db);
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out_txd_cb(db);
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}
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else
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{
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LOG(LLFORMAT " %s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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LOGTX("%s \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, owner()->tag(), 'A' + m_index);
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}
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}
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//-------------------------------------------------
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// tra_complete -
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//-------------------------------------------------
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void z80scc_channel::tra_complete()
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{
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// Delayed baudrate change according to SCC specs
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@ -1118,7 +1108,7 @@ void z80scc_channel::tra_complete()
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{
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m_delayed_tx_brg_change = 0;
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set_tra_rate(m_brg_rate);
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LOG("Delayed Init - Baud Rate Generator: %d mode: %dx\n", m_brg_rate, get_clock_mode() );
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LOGTX("Delayed Init - Baud Rate Generator: %d mode: %dx\n", m_brg_rate, get_clock_mode() );
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}
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if ((m_wr5 & WR5_TX_ENABLE) && !(m_wr5 & WR5_SEND_BREAK))
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@ -1126,7 +1116,7 @@ void z80scc_channel::tra_complete()
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if ( (m_rr0 & RR0_TX_BUFFER_EMPTY) == 0 || // Takes care of the NMOS/CMOS 1 slot TX FIFO
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m_tx_fifo_rp != m_tx_fifo_wp) // or there are more characters to send in a longer FIFO.
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{
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LOGTX(" %s() %s %c done sending, loading data from fifo:%02x '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index,
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LOGTX("%s %s %c done sending, loading data from fifo:%02x '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index,
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m_tx_data_fifo[m_tx_fifo_rp], isascii(m_tx_data_fifo[m_tx_fifo_rp]) ? m_tx_data_fifo[m_tx_fifo_rp] : ' ');
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transmit_register_setup(m_tx_data_fifo[m_tx_fifo_rp]); // Reload the shift register
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m_tx_fifo_rp_step();
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@ -1134,7 +1124,7 @@ void z80scc_channel::tra_complete()
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}
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else
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{
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LOGTX(" %s() %s %c done sending, setting all sent bit\n", FUNCNAME, owner()->tag(), 'A' + m_index);
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LOGTX("%s %s %c done sending, setting all sent bit\n", FUNCNAME, owner()->tag(), 'A' + m_index);
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m_rr1 |= RR1_ALL_SENT;
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// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
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@ -1163,21 +1153,15 @@ void z80scc_channel::tra_complete()
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}
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else if (m_wr5 & WR5_SEND_BREAK)
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{
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LOG(LLFORMAT " %s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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LOG("%s \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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// transmit break
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if (m_index == z80scc_device::CHANNEL_A)
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m_uart->m_out_txda_cb(0);
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else
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m_uart->m_out_txdb_cb(0);
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out_txd_cb(0);
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}
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else
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{
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LOG(LLFORMAT " %s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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LOG("%s \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_wr5);
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// transmit mark
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if (m_index == z80scc_device::CHANNEL_A)
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m_uart->m_out_txda_cb(1);
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else
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m_uart->m_out_txdb_cb(1);
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out_txd_cb(1);
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}
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}
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@ -1185,18 +1169,17 @@ void z80scc_channel::tra_complete()
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//-------------------------------------------------
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// rcv_callback -
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//-------------------------------------------------
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void z80scc_channel::rcv_callback()
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{
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if (m_wr3 & WR3_RX_ENABLE)
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{
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LOG(LLFORMAT " %s() \"%s \"Channel %c receive data bit %d m_wr3:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, m_rxd, m_wr3);
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LOG("%s \"%s \"Channel %c receive data bit %d m_wr3:%02x\n", FUNCNAME, owner()->tag(), 'A' + m_index, m_rxd, m_wr3);
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receive_register_update_bit(m_rxd);
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}
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#if 1
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else
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{
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LOG(LLFORMAT " %s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index);
|
||||
LOG("%s \"%s \"Channel %c Received Data Bit but receiver is disabled\n", FUNCNAME, owner()->tag(), 'A' + m_index);
|
||||
logerror("%s \"%s \"Channel %c Received data dit but receiver is disabled\n", FUNCNAME, owner()->tag(), 'A' + m_index);
|
||||
}
|
||||
#endif
|
||||
@ -1206,14 +1189,13 @@ void z80scc_channel::rcv_callback()
|
||||
//-------------------------------------------------
|
||||
// rcv_complete -
|
||||
//-------------------------------------------------
|
||||
|
||||
void z80scc_channel::rcv_complete()
|
||||
{
|
||||
uint8_t data;
|
||||
|
||||
receive_register_extract();
|
||||
data = get_received_char();
|
||||
LOG(LLFORMAT " %s() \"%s \"Channel %c Received Data %c\n", machine().firstcpu->total_cycles(), FUNCNAME, owner()->tag(), 'A' + m_index, data);
|
||||
LOG("%s \"%s \"Channel %c Received Data %c\n", FUNCNAME, owner()->tag(), 'A' + m_index, data);
|
||||
receive_data(data);
|
||||
#if START_BIT_HUNT
|
||||
m_rcv_mode = RCV_SEEKING;
|
||||
@ -1224,7 +1206,6 @@ void z80scc_channel::rcv_complete()
|
||||
//-------------------------------------------------
|
||||
// get_clock_mode - get clock divisor
|
||||
//-------------------------------------------------
|
||||
|
||||
int z80scc_channel::get_clock_mode()
|
||||
{
|
||||
int clocks = 1;
|
||||
@ -1254,10 +1235,7 @@ TODO:
|
||||
void z80scc_channel::set_rts(int state)
|
||||
{
|
||||
LOG("%s(%d) \"%s\": %c \n", FUNCNAME, state, owner()->tag(), 'A' + m_index);
|
||||
if (m_index == z80scc_device::CHANNEL_A)
|
||||
m_uart->m_out_rtsa_cb(state);
|
||||
else
|
||||
m_uart->m_out_rtsb_cb(state);
|
||||
out_rts_cb(state);
|
||||
}
|
||||
|
||||
void z80scc_channel::update_rts()
|
||||
@ -1282,7 +1260,6 @@ void z80scc_channel::update_rts()
|
||||
//-------------------------------------------------
|
||||
// get_stop_bits - get number of stop bits
|
||||
//-------------------------------------------------
|
||||
|
||||
device_serial_interface::stop_bits_t z80scc_channel::get_stop_bits()
|
||||
{
|
||||
switch (m_wr4 & WR4_STOP_BITS_MASK)
|
||||
@ -1299,7 +1276,6 @@ device_serial_interface::stop_bits_t z80scc_channel::get_stop_bits()
|
||||
//-------------------------------------------------
|
||||
// get_rx_word_length - get receive word length
|
||||
//-------------------------------------------------
|
||||
|
||||
int z80scc_channel::get_rx_word_length()
|
||||
{
|
||||
int bits = 5;
|
||||
@ -1319,7 +1295,6 @@ int z80scc_channel::get_rx_word_length()
|
||||
//-------------------------------------------------
|
||||
// get_tx_word_length - get transmit word length
|
||||
//-------------------------------------------------
|
||||
|
||||
int z80scc_channel::get_tx_word_length()
|
||||
{
|
||||
int bits = 5;
|
||||
@ -1482,7 +1457,7 @@ uint8_t z80scc_channel::do_sccreg_rr7()
|
||||
LOGR("%s\n", FUNCNAME);
|
||||
if (!(m_uart->m_variant & (z80scc_device::SET_NMOS)))
|
||||
{
|
||||
logerror(" %s() not implemented feature\n", FUNCNAME);
|
||||
logerror("%s not implemented feature\n", FUNCNAME);
|
||||
return 0;
|
||||
}
|
||||
return m_rr3;
|
||||
@ -1513,7 +1488,7 @@ uint8_t z80scc_channel::do_sccreg_rr9()
|
||||
uint8_t z80scc_channel::do_sccreg_rr10()
|
||||
{
|
||||
LOGR("%s\n", FUNCNAME);
|
||||
logerror("%s() not implemented feature\n", FUNCNAME);
|
||||
logerror("%s not implemented feature\n", FUNCNAME);
|
||||
return m_rr10;
|
||||
}
|
||||
|
||||
@ -1623,7 +1598,7 @@ uint8_t z80scc_channel::scc_register_read( uint8_t reg)
|
||||
case REG_RR14_WR7_OR_R10: data = do_sccreg_rr14(); break;
|
||||
case REG_RR15_WR15_EXT_STAT: data = do_sccreg_rr15(); break;
|
||||
default:
|
||||
logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", owner()->tag(), FUNCNAME, 'A' + m_index, reg);
|
||||
logerror(" \"%s\"%s: %c : Unsupported RRx register:%02x\n", owner()->tag(), FUNCNAME, 'A' + m_index, reg);
|
||||
}
|
||||
return data;
|
||||
}
|
||||
@ -1927,7 +1902,7 @@ void z80scc_channel::do_sccreg_wr7(uint8_t data)
|
||||
/* WR8 is the transmit buffer register */
|
||||
void z80scc_channel::do_sccreg_wr8(uint8_t data)
|
||||
{
|
||||
LOG("%s(%02x) \"%s\": %c : Transmit Buffer write %02x\n", FUNCNAME, data, owner()->tag(), 'A' + m_index, data);
|
||||
LOGTX("%s(%02x) \"%s\": %c : Transmit Buffer write %02x\n", FUNCNAME, data, owner()->tag(), 'A' + m_index, data);
|
||||
data_write(data);
|
||||
}
|
||||
|
||||
@ -2257,7 +2232,6 @@ with 0 before accessing WR0 or RR0.*/
|
||||
//-------------------------------------------------
|
||||
// control_write - write control register
|
||||
//-------------------------------------------------
|
||||
|
||||
void z80scc_channel::control_write(uint8_t data)
|
||||
{
|
||||
uint8_t reg = m_uart->m_wr0_ptrbits; //m_wr0;
|
||||
@ -2286,7 +2260,6 @@ void z80scc_channel::control_write(uint8_t data)
|
||||
//-------------------------------------------------
|
||||
// data_read - read data register from fifo
|
||||
//-------------------------------------------------
|
||||
|
||||
uint8_t z80scc_channel::data_read()
|
||||
{
|
||||
uint8_t data = 0;
|
||||
@ -2383,7 +2356,7 @@ WRITE8_MEMBER (z80scc_device::db_w) { m_chanB->data_write(data); }
|
||||
void z80scc_channel::data_write(uint8_t data)
|
||||
{
|
||||
/* Tx FIFO is full or...? */
|
||||
LOGTX("%s \"%s\": %c : Data Register Write: %02d '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index, data, isprint(data) ? data : ' ');
|
||||
LOG("%s \"%s\": %c : Data Register Write: %02d '%c'\n", FUNCNAME, owner()->tag(), 'A' + m_index, data, isprint(data) ? data : ' ');
|
||||
|
||||
if ( !(m_rr0 & RR0_TX_BUFFER_EMPTY) && // NMOS/CMOS 1 slot "FIFO" is controlled by the TBE bit instead of fifo logic
|
||||
( (m_tx_fifo_wp + 1 == m_tx_fifo_rp) || ( (m_tx_fifo_wp + 1 == m_tx_fifo_sz) && (m_tx_fifo_rp == 0) )))
|
||||
@ -2469,7 +2442,6 @@ void z80scc_channel::data_write(uint8_t data)
|
||||
//-------------------------------------------------
|
||||
// receive_data - put received data word into fifo
|
||||
//-------------------------------------------------
|
||||
|
||||
void z80scc_channel::receive_data(uint8_t data)
|
||||
{
|
||||
LOGRCV("\"%s\": %c : Received Data Byte '%c'/%02x put into FIFO\n", owner()->tag(), 'A' + m_index, isprint(data) ? data : ' ', data);
|
||||
@ -2522,10 +2494,9 @@ void z80scc_channel::receive_data(uint8_t data)
|
||||
//-------------------------------------------------
|
||||
// cts_w - clear to send handler
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE_LINE_MEMBER( z80scc_channel::cts_w )
|
||||
{
|
||||
LOG("\"%s\" %s: %c : CTS %u\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
|
||||
LOG("\"%s\"%s: %c : CTS %u\n", owner()->tag(), FUNCNAME, 'A' + m_index, state);
|
||||
|
||||
if ((m_rr0 & RR0_CTS) != (state ? RR0_CTS : 0)) // SCC change detection logic
|
||||
{
|
||||
@ -2782,7 +2753,7 @@ void z80scc_channel::update_serial()
|
||||
parity = PARITY_NONE;
|
||||
}
|
||||
|
||||
LOG(" %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", FUNCNAME, owner()->tag(), 'A' + m_index, 1,
|
||||
LOG("%s \"%s \"Channel %c setting data frame %d+%d%c%d\n", FUNCNAME, owner()->tag(), 'A' + m_index, 1,
|
||||
data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2);
|
||||
|
||||
set_data_frame(1, data_bit_count, parity, stop_bits);
|
||||
@ -2841,10 +2812,7 @@ void z80scc_channel::set_dtr(int state)
|
||||
LOG("%s(%d)\n", FUNCNAME, state);
|
||||
m_dtr = state;
|
||||
|
||||
if (m_index == z80scc_device::CHANNEL_A)
|
||||
m_uart->m_out_dtra_cb(m_dtr);
|
||||
else
|
||||
m_uart->m_out_dtrb_cb(m_dtr);
|
||||
out_dtr_cb(m_dtr);
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -2893,8 +2861,6 @@ void z80scc_channel::check_waitrequest()
|
||||
if (m_wr1 & WR1_WREQ_FUNCTION)
|
||||
{
|
||||
// assert /W//REQ if transmit buffer is empty, clear if it's not
|
||||
int state = (m_rr0 & RR0_TX_BUFFER_EMPTY) ? ASSERT_LINE : CLEAR_LINE;
|
||||
|
||||
(m_index ? m_uart->m_out_wreqb_cb : m_uart->m_out_wreqa_cb)(state);
|
||||
m_uart->m_out_wreq_cb[m_index]((m_rr0 & RR0_TX_BUFFER_EMPTY) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
@ -90,47 +90,47 @@
|
||||
|
||||
// Port A callbacks
|
||||
#define MCFG_Z80SCC_OUT_TXDA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txda_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_txd_callback<0>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_DTRA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_dtra_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_dtr_callback<0>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RTSA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rtsa_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_rts_callback<0>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_WREQA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_wreqa_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_wreq_callback<0>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_SYNCA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_synca_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_sync_callback<0>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RXDRQA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rxdrqa_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_rxdrq_callback<0>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_TXDRQA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txdrqa_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_txdrq_callback<0>(*device, DEVCB_##_devcb);
|
||||
|
||||
// Port B callbacks
|
||||
#define MCFG_Z80SCC_OUT_TXDB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txdb_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_txd_callback<1>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_DTRB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_dtrb_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_dtr_callback<1>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RTSB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rtsb_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_rts_callback<1>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_WREQB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_wreqb_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_wreq_callback<1>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_SYNCB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_syncb_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_sync_callback<1>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RXDRQB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rxdrqb_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_rxdrq_callback<1>(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_TXDRQB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txdrqb_callback(*device, DEVCB_##_devcb);
|
||||
devcb = &z80scc_device::set_out_txdrq_callback<1>(*device, DEVCB_##_devcb);
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
@ -632,6 +632,12 @@ protected:
|
||||
// SCC specifics
|
||||
int m_ph; // Point high command to access regs 08-0f
|
||||
uint8_t m_zc;
|
||||
private:
|
||||
// helpers
|
||||
void out_txd_cb(int state);
|
||||
void out_rts_cb(int state);
|
||||
void out_dtr_cb(int state);
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -645,21 +651,14 @@ public:
|
||||
// construction/destruction
|
||||
z80scc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
template <class Object> static devcb_base &set_out_txda_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txda_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_dtra_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_dtra_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_rtsa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rtsa_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_wreqa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_wreqa_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_synca_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_synca_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_txdb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdb_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_dtrb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_dtrb_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_rtsb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rtsb_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_wreqb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_wreqb_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_syncb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_syncb_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <unsigned N, class Object> static devcb_base &set_out_txd_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txd_cb[N].set_callback(std::forward<Object>(cb)); }
|
||||
template <unsigned N, class Object> static devcb_base &set_out_dtr_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_dtr_cb[N].set_callback(std::forward<Object>(cb)); }
|
||||
template <unsigned N, class Object> static devcb_base &set_out_rts_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rts_cb[N].set_callback(std::forward<Object>(cb)); }
|
||||
template <unsigned N, class Object> static devcb_base &set_out_wreq_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_wreq_cb[N].set_callback(std::forward<Object>(cb)); }
|
||||
template <unsigned N, class Object> static devcb_base &set_out_sync_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_sync_cb[N].set_callback(std::forward<Object>(cb)); }
|
||||
template <unsigned N, class Object> static devcb_base &set_out_rxdrq_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rxdrq_cb[N].set_callback(std::forward<Object>(cb)); }
|
||||
template <unsigned N, class Object> static devcb_base &set_out_txdrq_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdrq_cb[N].set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_int_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_int_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_rxdrqa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rxdrqa_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_txdrqa_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdrqa_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_rxdrqb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_rxdrqb_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template <class Object> static devcb_base &set_out_txdrqb_callback(device_t &device, Object &&cb) { return downcast<z80scc_device &>(device).m_out_txdrqb_cb.set_callback(std::forward<Object>(cb)); }
|
||||
|
||||
static void static_set_cputag(device_t &device, const char *tag)
|
||||
{
|
||||
@ -727,6 +726,7 @@ protected:
|
||||
z80scc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t variant);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_resolve_objects() override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
@ -781,23 +781,16 @@ protected:
|
||||
int m_rxcb;
|
||||
int m_txcb;
|
||||
|
||||
devcb_write_line m_out_txda_cb;
|
||||
devcb_write_line m_out_dtra_cb;
|
||||
devcb_write_line m_out_rtsa_cb;
|
||||
devcb_write_line m_out_wreqa_cb;
|
||||
devcb_write_line m_out_synca_cb;
|
||||
|
||||
devcb_write_line m_out_txdb_cb;
|
||||
devcb_write_line m_out_dtrb_cb;
|
||||
devcb_write_line m_out_rtsb_cb;
|
||||
devcb_write_line m_out_wreqb_cb;
|
||||
devcb_write_line m_out_syncb_cb;
|
||||
// internal state
|
||||
devcb_write_line m_out_txd_cb[2];
|
||||
devcb_write_line m_out_dtr_cb[2];
|
||||
devcb_write_line m_out_rts_cb[2];
|
||||
devcb_write_line m_out_wreq_cb[2];
|
||||
devcb_write_line m_out_sync_cb[2];
|
||||
devcb_write_line m_out_rxdrq_cb[2];
|
||||
devcb_write_line m_out_txdrq_cb[2];
|
||||
|
||||
devcb_write_line m_out_int_cb;
|
||||
devcb_write_line m_out_rxdrqa_cb;
|
||||
devcb_write_line m_out_txdrqa_cb;
|
||||
devcb_write_line m_out_rxdrqb_cb;
|
||||
devcb_write_line m_out_txdrqb_cb;
|
||||
|
||||
int m_int_state[6]; // interrupt state
|
||||
int m_int_source[6]; // interrupt source
|
||||
|
||||
Loading…
Reference in New Issue
Block a user