mirror of
https://github.com/holub/mame
synced 2025-04-26 02:07:14 +03:00
Rewrote NCR539x SCSI emulation from scratch [R. Belmont]
This commit is contained in:
R. Belmont
parent
73d359e0ed
commit
2f3b6bc006
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -909,6 +909,8 @@ src/emu/machine/msm58321.c svneol=native#text/plain
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src/emu/machine/msm58321.h svneol=native#text/plain
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src/emu/machine/msm6242.c svneol=native#text/plain
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src/emu/machine/msm6242.h svneol=native#text/plain
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src/emu/machine/ncr539x.c svneol=native#text/plain
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src/emu/machine/ncr539x.h svneol=native#text/plain
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src/emu/machine/nmc9306.c svneol=native#text/plain
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src/emu/machine/nmc9306.h svneol=native#text/plain
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src/emu/machine/nvram.c svneol=native#text/plain
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@ -215,6 +215,7 @@ EMUMACHINEOBJS = \
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$(EMUMACHINE)/msm5832.o \
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$(EMUMACHINE)/msm58321.o \
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$(EMUMACHINE)/msm6242.o \
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$(EMUMACHINE)/ncr539x.o \
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$(EMUMACHINE)/nmc9306.o \
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$(EMUMACHINE)/nvram.o \
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$(EMUMACHINE)/pc16552d.o \
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912
src/emu/machine/ncr539x.c
Normal file
912
src/emu/machine/ncr539x.c
Normal file
@ -0,0 +1,912 @@
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/*
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* ncr539x.c
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*
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* NCR 53(CF)94/53(CF)96 SCSI controller
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* Includes enhanced features of the AMD 53CF94/96 and compatibles
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*
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* All new emulation in 2011 by R. Belmont.
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*
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*/
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#include "emu.h"
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#include "ncr539x.h"
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#define VERBOSE (0)
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#define VERBOSE_READS (0)
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enum
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{
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TIMER_539X_COMMAND,
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TIMER_539X_END
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};
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#define MAIN_STATUS_INTERRUPT 0x80
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#define MAIN_STATUS_ILLEGAL_OPER 0x40
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#define MAIN_STATUS_PARITY_ERROR 0x20
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#define MAIN_STATUS_COUNT_TO_ZERO 0x10
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#define MAIN_STATUS_GROUP_VALID 0x08
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#define MAIN_STATUS_MESSAGE 0x04
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#define MAIN_STATUS_CMD_DATA 0x02
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#define MAIN_STATUS_IO 0x01
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#define IRQ_STATUS_RESET 0x80
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#define IRQ_STATUS_INVALID_COMMAND 0x40
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#define IRQ_STATUS_DISCONNECTED 0x20
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#define IRQ_STATUS_SERVICE_REQUEST 0x10
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#define IRQ_STATUS_SUCCESS 0x08
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#define IRQ_STATUS_RESELECTED 0x04 // we were reselected as a target
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#define IRQ_STATUS_SELECTED_WITH_ATN 0x02 // we were selected as a target with ATN steps
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#define IRQ_STATUS_SELECTED 0x01 // we were selected as a target
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#define CR2_ALIGN_ENABLE 0x80
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#define CR2_FEATURES_ENABLE 0x40
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#define CR2_BYTE_ORDER 0x20
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#define CR2_TRISTATE_DMA 0x10
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#define CR2_SCSI2_ENABLE 0x08
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#define CR2_ABORT_ON_PARITY_ERROR 0x04
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#define CR2_GENERATE_REGISTER_PARITY 0x02
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#define CR2_GENERATE_DATA_PARITY 0x01
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#if VERBOSE
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#if VERBOSE_READS
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static const char *rdregs[16] = {
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"Transfer count LSB", // 0
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"Transfer count MSB", // 1
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"FIFO", // 2
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"Command", // 3
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"Status", // 4
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"Interrupt Status", // 5
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"Internal State",
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"Current FIFO/Internal State",
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"Control Register 1",
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"0x9",
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"0xA",
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"Control Register 2",
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"Control Register 3",
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"Control Register 4",
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"Transfer count HSB/Chip ID",
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"0xF"
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};
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#endif
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static const char *wrregs[16] = {
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"Start Transfer count LSB",
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"Start Transfer count MSB",
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"FIFO",
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"Command",
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"SCSI Destination ID",
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"SCSI Timeout",
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"Synchronous Transfer Period",
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"Synchronous Offset",
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"Control Register 1",
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"Clock Factor",
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"Forced Test Mode",
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"Control Register 2",
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"Control Register 3",
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"Control Register 4",
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"Start Transfer count HSB",
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"Data Alignment"
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};
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#endif
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// get the length of a SCSI command based on its command byte type
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static int get_cmd_len(int cbyte)
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{
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int group;
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group = (cbyte>>5) & 7;
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if (group == 0) return 6;
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if (group == 1 || group == 2) return 10;
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if (group == 5) return 12;
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return 6;
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}
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//-------------------------------------------------
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// device_config_complete - perform any
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// operations now that the configuration is
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// complete
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//-------------------------------------------------
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void ncr539x_device::device_config_complete()
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{
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// inherit a copy of the static data
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const NCR539Xinterface *intf = reinterpret_cast<const NCR539Xinterface *>(static_config());
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if (intf != NULL)
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{
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*static_cast<NCR539Xinterface *>(this) = *intf;
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}
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// or initialize to defaults if none provided
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else
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{
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scsidevs = NULL;
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memset(&m_out_irq_cb, 0, sizeof(m_out_irq_cb));
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memset(&m_out_drq_cb, 0, sizeof(m_out_drq_cb));
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}
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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const device_type NCR539X = &device_creator<ncr539x_device>;
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//-------------------------------------------------
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// ncr539x_device - constructor/destructor
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//-------------------------------------------------
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ncr539x_device::ncr539x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, NCR539X, "539x SCSI", tag, owner, clock)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void ncr539x_device::device_start()
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{
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int i;
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memset(m_scsi_devices, 0, sizeof(m_scsi_devices));
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// resolve line callbacks
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m_out_irq_func.resolve(m_out_irq_cb, *this);
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m_out_drq_func.resolve(m_out_drq_cb, *this);
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// try to open the devices
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for (i = 0; i < scsidevs->devs_present; i++)
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{
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SCSIAllocInstance( machine(),
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scsidevs->devices[i].scsiClass,
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&m_scsi_devices[scsidevs->devices[i].scsiID],
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scsidevs->devices[i].diskregion );
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}
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m_operation_timer = timer_alloc(0, NULL);
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void ncr539x_device::device_reset()
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{
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memset(m_scsi_devices, 0, sizeof(m_scsi_devices));
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m_fifo_ptr = 0;
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m_irq_status = 0;
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m_status = SCSI_PHASE_STATUS;
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m_internal_state = 0;
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m_buffer_offset = 512;
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m_buffer_remaining = 0;
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m_dma_size = 0;
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m_xfer_count = 0;
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m_total_data = 0;
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m_selected = false;
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m_control1 = m_control2 = m_control3 = m_control4 = 0;
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m_chipid_available = false;
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m_chipid_lock = false;
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m_out_irq_func(CLEAR_LINE);
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m_out_drq_func(CLEAR_LINE);
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scan_devices();
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}
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//-------------------------------------------------
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// device_stop - device-specific stop/shutdown
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//-------------------------------------------------
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void ncr539x_device::device_stop()
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{
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int i;
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// clean up the devices
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for (i = 0; i < scsidevs->devs_present; i++)
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{
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SCSIDeleteInstance( m_scsi_devices[scsidevs->devices[i].scsiID] );
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}
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}
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void ncr539x_device::dma_read_data(int bytes, UINT8 *pData)
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{
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if (m_scsi_devices[m_last_id])
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{
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if (VERBOSE)
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logerror("NCR539x: issuing read for %d bytes\n", bytes);
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SCSIReadData(m_scsi_devices[m_last_id], pData, bytes);
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}
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else
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{
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logerror("ncr539x: read unknown device SCSI ID %d\n", m_last_id);
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}
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}
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void ncr539x_device::dma_write_data(int bytes, UINT8 *pData)
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{
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if (bytes)
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{
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if (m_scsi_devices[m_last_id])
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{
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SCSIWriteData(m_scsi_devices[m_last_id], pData, bytes);
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}
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else
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{
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logerror("ncr539x: write to unknown device SCSI ID %d\n", m_last_id);
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}
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}
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}
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void ncr539x_device::scan_devices()
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{
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int i;
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// try to open the devices
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for (i = 0; i < scsidevs->devs_present; i++)
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{
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// if a device wasn't already allocated
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if (!m_scsi_devices[scsidevs->devices[i].scsiID])
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{
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SCSIAllocInstance( machine(),
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scsidevs->devices[i].scsiClass,
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&m_scsi_devices[scsidevs->devices[i].scsiID],
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scsidevs->devices[i].diskregion );
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}
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}
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}
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void ncr539x_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
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{
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//printf("539X: device_timer expired, param = %d, m_command = %02x\n", param, m_command);
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switch (param)
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{
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case TIMER_539X_COMMAND:
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// if this is a DMA command, raise DRQ now
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if (m_command & 0x80)
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{
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m_out_drq_func(ASSERT_LINE);
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}
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switch (m_command & 0x7f)
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{
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case 0x41: // select without ATN steps
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if (m_scsi_devices[m_last_id])
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{
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m_irq_status |= IRQ_STATUS_SERVICE_REQUEST | IRQ_STATUS_SUCCESS;
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// we should now be in the command phase
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m_status &= ~7; // clear bus phases
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m_status |= MAIN_STATUS_INTERRUPT | SCSI_PHASE_COMMAND;
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m_fifo_ptr = 0;
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m_selected = true;
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#if VERBOSE
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printf("Selecting w/o ATN, irq_status = %02x, status = %02x!\n", m_irq_status, m_status);
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#endif
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// if DMA is not enabled, there should already be a command loaded into the FIFO
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if (!(m_command & 0x80))
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{
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exec_fifo();
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}
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update_fifo_internal_state(0);
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}
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else
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{
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#if VERBOSE
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printf("Select failed, no device @ ID %d!\n", m_last_id);
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#endif
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m_status |= MAIN_STATUS_INTERRUPT;
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m_irq_status |= IRQ_STATUS_DISCONNECTED;
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}
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m_out_irq_func(ASSERT_LINE);
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break;
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case 0x42: // Select with ATN steps
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if (m_scsi_devices[m_last_id])
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{
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m_irq_status |= IRQ_STATUS_SERVICE_REQUEST | IRQ_STATUS_SUCCESS;
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// we should now be in the command phase
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m_status &= ~7; // clear bus phases
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m_status |= MAIN_STATUS_INTERRUPT | SCSI_PHASE_COMMAND;
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m_fifo_ptr = 0;
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m_selected = true;
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#if VERBOSE
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printf("Selecting with ATN, irq_status = %02x, status = %02x!\n", m_irq_status, m_status);
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#endif
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// if DMA is not enabled, there should already be a command loaded into the FIFO
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if (!(m_command & 0x80))
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{
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exec_fifo();
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}
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update_fifo_internal_state(0);
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}
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else
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{
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#if VERBOSE
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printf("Select failed, no device @ ID %d!\n", m_last_id);
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#endif
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m_status |= MAIN_STATUS_INTERRUPT;
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m_irq_status |= IRQ_STATUS_DISCONNECTED;
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}
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m_out_irq_func(ASSERT_LINE);
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break;
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case 0x11: // initiator command complete
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#if VERBOSE
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printf("Initiator command complete\n");
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#endif
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m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
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m_status &= ~7; // clear phase bits
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m_status |= MAIN_STATUS_INTERRUPT | SCSI_PHASE_DATAIN; // go to data in phase (?)
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m_out_irq_func(ASSERT_LINE);
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// this puts status and message bytes into the FIFO (todo: what are these?)
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m_fifo_ptr = 0;
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m_xfer_count = 2;
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m_buffer_remaining = m_total_data = 0;
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m_fifo[0] = 0; // status byte
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m_fifo[1] = 0; // message byte
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m_selected = false;
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update_fifo_internal_state(2);
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break;
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case 0x12: // message accepted
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#if VERBOSE
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printf("Message accepted\n");
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#endif
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m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
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m_status |= MAIN_STATUS_INTERRUPT;
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m_out_irq_func(ASSERT_LINE);
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break;
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default:
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fatalerror("539x: Unhandled command %02x\n", m_command);
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break;
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}
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break;
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default:
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break;
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}
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}
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READ8_MEMBER( ncr539x_device::read )
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{
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UINT8 rv = 0;
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#if VERBOSE
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#if VERBOSE_READS
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printf("539x: Read @ %s (%02x) (PC=%x) (status %02x irq_status %02x)\n", rdregs[offset], offset, cpu_get_pc(&space.device()), m_status, m_irq_status);
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#endif
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#endif
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switch (offset)
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{
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case 0:
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rv = m_xfer_count & 0xff;
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break;
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case 1:
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rv = (m_xfer_count>>8) & 0xff;
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break;
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case 2: // FIFO
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{
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UINT8 fifo_bytes = m_fifo_internal_state & 0x1f;
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if (!fifo_bytes)
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{
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rv = 0;
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}
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else
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{
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rv = m_fifo[m_fifo_ptr++];
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fifo_bytes--;
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m_xfer_count--;
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update_fifo_internal_state(fifo_bytes);
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#if VERBOSE
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printf("Read %02x from FIFO[%d], FIFO now contains %d bytes (PC=%x, m_buffer_remaining %x)\n", rv, m_fifo_ptr-1, fifo_bytes, cpu_get_pc(&space.device()), m_buffer_remaining);
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#endif
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if (fifo_bytes == 0)
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{
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// the last transfer command has more data for us
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if (m_xfer_count > 0)
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{
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int fifo_fill_size = m_fifo_size;
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if (m_xfer_count < fifo_fill_size)
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{
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fifo_fill_size = m_xfer_count;
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}
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memcpy(m_fifo, &m_buffer[m_buffer_offset], fifo_fill_size);
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m_buffer_offset += fifo_fill_size;
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m_buffer_remaining -= fifo_fill_size;
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m_fifo_ptr = 0;
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update_fifo_internal_state(fifo_fill_size);
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#if VERBOSE
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printf("Refreshing FIFO (%x remaining from transfer, %x in buffer, %x in total)\n", m_xfer_count, m_buffer_remaining, m_total_data);
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#endif
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}
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else
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{
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#if VERBOSE
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printf("FIFO empty, asserting service request (buffer_remaining %x)\n", m_buffer_remaining);
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#endif
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m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
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m_status &= 0x7; // clear everything but the phase bits
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m_status |= MAIN_STATUS_INTERRUPT | MAIN_STATUS_COUNT_TO_ZERO;
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m_out_irq_func(ASSERT_LINE);
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// if no data at all, drop the phase
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if ((m_buffer_remaining + m_total_data) == 0)
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{
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#if VERBOSE
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printf("Out of data, setting phase STATUS\n");
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#endif
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m_status &= ~0x7;
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m_status |= SCSI_PHASE_STATUS;
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}
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}
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}
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}
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}
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break;
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||||
|
||||
case 3:
|
||||
rv = m_command;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
rv = m_status;
|
||||
break;
|
||||
|
||||
case 5:
|
||||
rv = m_irq_status;
|
||||
// clear the interrupt state
|
||||
m_status &= ~MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(CLEAR_LINE);
|
||||
break;
|
||||
|
||||
case 6:
|
||||
rv = m_internal_state;
|
||||
break;
|
||||
|
||||
case 7:
|
||||
rv = m_fifo_internal_state;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
rv = m_control1;
|
||||
break;
|
||||
|
||||
case 0xb:
|
||||
rv = m_control2;
|
||||
break;
|
||||
|
||||
case 0xc:
|
||||
rv = m_control3;
|
||||
break;
|
||||
|
||||
case 0xd:
|
||||
rv = m_control4;
|
||||
break;
|
||||
|
||||
case 0xe:
|
||||
if (m_control2 & CR2_FEATURES_ENABLE)
|
||||
{
|
||||
if (m_chipid_available)
|
||||
{
|
||||
rv = 0xa2; // 0x12 for CF94, 0xa2 for CF96
|
||||
}
|
||||
else
|
||||
{
|
||||
rv = (m_xfer_count>>16) & 0xff;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
return rv;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( ncr539x_device::write )
|
||||
{
|
||||
#if VERBOSE
|
||||
if (offset != 2) printf("539x: Write %02x @ %s (%02x) (PC=%x)\n", data, wrregs[offset], offset, cpu_get_pc(&space.device()));
|
||||
#endif
|
||||
|
||||
switch (offset)
|
||||
{
|
||||
case 0:
|
||||
m_dma_size &= 0xff00;
|
||||
m_dma_size |= data;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
m_dma_size &= 0x00ff;
|
||||
m_dma_size |= (data<<8);
|
||||
break;
|
||||
|
||||
case 2: // FIFO
|
||||
fifo_write(data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
m_command = data;
|
||||
|
||||
// clear status bits (OK to do here?)
|
||||
m_status &= ~MAIN_STATUS_INTERRUPT;
|
||||
m_irq_status = 0;
|
||||
|
||||
switch (data & 0x7f)
|
||||
{
|
||||
case 0x00: // NOP
|
||||
m_irq_status = IRQ_STATUS_SUCCESS;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
|
||||
// DMA NOP? allow chip ID
|
||||
if ((m_command == 0x80) && (!m_chipid_lock))
|
||||
{
|
||||
m_chipid_available = true;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x01: // Clear FIFO (must not change buffer state)
|
||||
m_fifo_ptr = 0;
|
||||
update_fifo_internal_state(0);
|
||||
m_irq_status = IRQ_STATUS_SUCCESS;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
break;
|
||||
|
||||
case 0x02: // Reset device
|
||||
device_reset();
|
||||
|
||||
m_irq_status = IRQ_STATUS_SUCCESS;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
break;
|
||||
|
||||
case 0x03: // Reset SCSI bus
|
||||
m_status = 0;
|
||||
m_irq_status = IRQ_STATUS_SUCCESS;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
break;
|
||||
|
||||
case 0x10: // information transfer (must happen immediately)
|
||||
m_status &= 0x7; // clear everything but the phase bits
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_irq_status = IRQ_STATUS_SUCCESS;
|
||||
|
||||
int phase;
|
||||
SCSIGetPhase( m_scsi_devices[m_last_id], &phase );
|
||||
|
||||
#if VERBOSE
|
||||
printf("Information transfer: phase %d buffer remaining %x\n", phase, m_buffer_remaining);
|
||||
#endif
|
||||
|
||||
if (phase == SCSI_PHASE_DATAIN) // target -> initiator transfer
|
||||
{
|
||||
int amtToGet = m_buffer_size;
|
||||
|
||||
// fill the internal sector buffer
|
||||
if (m_buffer_remaining <= 0)
|
||||
{
|
||||
if (m_total_data < m_buffer_size)
|
||||
{
|
||||
amtToGet = m_total_data;
|
||||
}
|
||||
|
||||
#if VERBOSE
|
||||
printf("amtToGet = %x\n", amtToGet);
|
||||
#endif
|
||||
|
||||
if (amtToGet > 0)
|
||||
{
|
||||
SCSIReadData(m_scsi_devices[m_last_id], m_buffer, amtToGet);
|
||||
|
||||
m_total_data -= amtToGet;
|
||||
m_buffer_offset = 0;
|
||||
m_buffer_remaining = amtToGet;
|
||||
}
|
||||
}
|
||||
|
||||
// copy the requested amount into the FIFO
|
||||
if (amtToGet > 0)
|
||||
{
|
||||
if (m_buffer_remaining < m_dma_size)
|
||||
{
|
||||
m_dma_size = m_buffer_remaining;
|
||||
}
|
||||
|
||||
int fifo_fill_size = m_fifo_size;
|
||||
|
||||
if (m_dma_size < fifo_fill_size)
|
||||
{
|
||||
fifo_fill_size = m_dma_size;
|
||||
}
|
||||
|
||||
#if VERBOSE
|
||||
printf("filling FIFO from buffer[%x] for %x bytes\n", m_buffer_offset, fifo_fill_size);
|
||||
#endif
|
||||
|
||||
memcpy(m_fifo, &m_buffer[m_buffer_offset], fifo_fill_size);
|
||||
m_buffer_offset += fifo_fill_size;
|
||||
m_buffer_remaining -= fifo_fill_size;
|
||||
|
||||
m_xfer_count = m_dma_size;
|
||||
m_fifo_ptr = 0;
|
||||
update_fifo_internal_state(fifo_fill_size);
|
||||
m_out_drq_func(ASSERT_LINE);
|
||||
}
|
||||
|
||||
m_status |= MAIN_STATUS_COUNT_TO_ZERO;
|
||||
|
||||
#if VERBOSE
|
||||
printf("Information transfer: put %02x bytes into FIFO (dma size %x) (buffer remaining %x)\n", m_fifo_internal_state & 0x1f, m_dma_size, m_buffer_remaining);
|
||||
#endif
|
||||
}
|
||||
else if (phase == SCSI_PHASE_DATAOUT)
|
||||
{
|
||||
m_xfer_count = m_dma_size;
|
||||
if (m_xfer_count == 0)
|
||||
{
|
||||
m_xfer_count = 0x10000;
|
||||
}
|
||||
#if VERBOSE
|
||||
printf("dma_size %x, xfer_count %x\n", m_dma_size, m_xfer_count);
|
||||
#endif
|
||||
m_status &= ~MAIN_STATUS_COUNT_TO_ZERO;
|
||||
m_fifo_ptr = 0;
|
||||
m_buffer_offset = 0;
|
||||
m_buffer_remaining = 0;
|
||||
}
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
break;
|
||||
|
||||
case 0x24: // Terminate steps
|
||||
#if VERBOSE
|
||||
printf("Terminate steps\n");
|
||||
#endif
|
||||
m_irq_status = IRQ_STATUS_SUCCESS | IRQ_STATUS_DISCONNECTED;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
m_fifo_ptr = 0;
|
||||
update_fifo_internal_state(0);
|
||||
break;
|
||||
|
||||
case 0x27: // Disconnect
|
||||
#if VERBOSE
|
||||
printf("Disconnect\n");
|
||||
#endif
|
||||
m_irq_status = IRQ_STATUS_SUCCESS;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
break;
|
||||
|
||||
case 0x44: // Enable selection/reselection
|
||||
#if VERBOSE
|
||||
printf("Enable selection/reselection\n");
|
||||
#endif
|
||||
m_irq_status = IRQ_STATUS_SUCCESS;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
break;
|
||||
|
||||
case 0x47: // Reselect with ATN3 steps
|
||||
if (m_scsi_devices[m_last_id])
|
||||
{
|
||||
m_irq_status |= IRQ_STATUS_SERVICE_REQUEST | IRQ_STATUS_SUCCESS;
|
||||
// we should now be in the command phase
|
||||
m_status &= ~7; // clear bus phases
|
||||
m_status |= MAIN_STATUS_INTERRUPT | SCSI_PHASE_COMMAND;
|
||||
m_fifo_ptr = 0;
|
||||
m_selected = true;
|
||||
#if VERBOSE
|
||||
printf("Reselecting with ATN3, irq_status = %02x, status = %02x!\n", m_irq_status, m_status);
|
||||
#endif
|
||||
|
||||
// if DMA is not enabled, there should already be a command loaded into the FIFO
|
||||
if (!(m_command & 0x80))
|
||||
{
|
||||
exec_fifo();
|
||||
}
|
||||
update_fifo_internal_state(0);
|
||||
}
|
||||
else
|
||||
{
|
||||
#if VERBOSE
|
||||
printf("Reselect with ATN3 failed, no device @ ID %d!\n", m_last_id);
|
||||
#endif
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_irq_status |= IRQ_STATUS_DISCONNECTED;
|
||||
}
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
break;
|
||||
|
||||
default: // other commands are not instantaneous
|
||||
#if VERBOSE
|
||||
printf("Setting timer for command %02x\n", data);
|
||||
#endif
|
||||
// 1x commands happen much faster
|
||||
if ((m_command & 0x70) == 0x10)
|
||||
{
|
||||
m_operation_timer->adjust(attotime::from_hz(65536), TIMER_539X_COMMAND);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_operation_timer->adjust(attotime::from_hz(16384), TIMER_539X_COMMAND);
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 4:
|
||||
m_last_id = data;
|
||||
break;
|
||||
|
||||
case 5:
|
||||
m_timeout = data;
|
||||
break;
|
||||
|
||||
case 6:
|
||||
m_sync_xfer_period = data;
|
||||
break;
|
||||
|
||||
case 7:
|
||||
m_sync_offset = data;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
m_control1 = data;
|
||||
break;
|
||||
|
||||
case 9:
|
||||
m_clock_factor = data;
|
||||
break;
|
||||
|
||||
case 0xa:
|
||||
m_forced_test = data;
|
||||
break;
|
||||
|
||||
case 0xb:
|
||||
m_control2 = data;
|
||||
break;
|
||||
|
||||
case 0xc:
|
||||
m_control3 = data;
|
||||
break;
|
||||
|
||||
case 0xd:
|
||||
m_control4 = data;
|
||||
break;
|
||||
|
||||
case 0xe:
|
||||
if (m_control2 & CR2_FEATURES_ENABLE)
|
||||
{
|
||||
m_dma_size &= 0xffff;
|
||||
m_dma_size |= (data<<16);
|
||||
m_chipid_available = false;
|
||||
m_chipid_lock = true;
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xf:
|
||||
m_data_alignment = data;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void ncr539x_device::exec_fifo()
|
||||
{
|
||||
int length, phase;
|
||||
|
||||
SCSISetCommand(m_scsi_devices[m_last_id], &m_fifo[0], 12);
|
||||
SCSIExecCommand(m_scsi_devices[m_last_id], &length);
|
||||
SCSIGetPhase(m_scsi_devices[m_last_id], &phase);
|
||||
|
||||
#if VERBOSE
|
||||
printf("Command executed (id %d), new phase %d, length %x\n", m_last_id, phase, length);
|
||||
#endif
|
||||
|
||||
m_buffer_offset = m_buffer_size;
|
||||
m_buffer_remaining = 0;
|
||||
m_total_data = length;
|
||||
|
||||
m_status &= ~7; // clear bus phases
|
||||
m_status |= (phase & 7); // set the phase reported by the device
|
||||
}
|
||||
|
||||
void ncr539x_device::check_fifo_executable()
|
||||
{
|
||||
if (get_cmd_len(m_fifo[0]) == m_fifo_ptr)
|
||||
{
|
||||
exec_fifo();
|
||||
}
|
||||
}
|
||||
|
||||
void ncr539x_device::fifo_write(UINT8 data)
|
||||
{
|
||||
int phase = (m_status & 7);
|
||||
|
||||
if (phase != SCSI_PHASE_DATAOUT)
|
||||
{
|
||||
#if VERBOSE
|
||||
printf("539x: Write %02x @ FIFO[%x]\n", data, m_fifo_ptr);
|
||||
#endif
|
||||
m_fifo[m_fifo_ptr++] = data;
|
||||
|
||||
if (m_selected)
|
||||
{
|
||||
check_fifo_executable();
|
||||
}
|
||||
}
|
||||
else // phase is DATAOUT
|
||||
{
|
||||
m_buffer[m_buffer_offset++] = data;
|
||||
m_xfer_count--;
|
||||
m_total_data--;
|
||||
#if VERBOSE
|
||||
printf("539x: Write %02x @ buffer[%x], xfer_count %x, total %x\n", data, m_buffer_offset-1, m_xfer_count, m_total_data);
|
||||
#endif
|
||||
|
||||
// default to flushing our entire buffer
|
||||
int flush_size = m_buffer_size;
|
||||
|
||||
// if the actual size is less than the buffer size, flush that instead
|
||||
if (m_dma_size < m_buffer_size)
|
||||
{
|
||||
flush_size = m_dma_size;
|
||||
}
|
||||
|
||||
if ((m_buffer_offset == flush_size) || (m_xfer_count == 0))
|
||||
{
|
||||
#if VERBOSE
|
||||
printf("Flushing buffer to device, %x bytes left in buffer (%x total)\n", m_xfer_count, m_total_data);
|
||||
#endif
|
||||
SCSIWriteData(m_scsi_devices[m_last_id], m_buffer, flush_size);
|
||||
m_buffer_offset = 0;
|
||||
|
||||
// need a service request here too
|
||||
m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
|
||||
m_status &= 7;
|
||||
m_status |= MAIN_STATUS_INTERRUPT;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
}
|
||||
|
||||
if ((m_xfer_count == 0) && (m_total_data == 0))
|
||||
{
|
||||
#if VERBOSE
|
||||
printf("End of write, asserting service request\n");
|
||||
#endif
|
||||
|
||||
m_buffer_offset = 0;
|
||||
m_irq_status = IRQ_STATUS_SERVICE_REQUEST;
|
||||
m_status = MAIN_STATUS_INTERRUPT | SCSI_PHASE_STATUS;
|
||||
m_out_irq_func(ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ncr539x_device::update_fifo_internal_state(int bytes)
|
||||
{
|
||||
if (bytes >= 0x1f)
|
||||
{
|
||||
m_fifo_internal_state |= 0x1f;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_fifo_internal_state &= ~0x1f;
|
||||
m_fifo_internal_state |= (bytes & 0x1f);
|
||||
}
|
||||
}
|
||||
97
src/emu/machine/ncr539x.h
Normal file
97
src/emu/machine/ncr539x.h
Normal file
@ -0,0 +1,97 @@
|
||||
/*
|
||||
* ncr5394/5396.h SCSI controller
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _NCR539x_H_
|
||||
#define _NCR539x_H_
|
||||
|
||||
#include "machine/scsidev.h"
|
||||
|
||||
struct NCR539Xinterface
|
||||
{
|
||||
const SCSIConfigTable *scsidevs; /* SCSI devices */
|
||||
devcb_write_line m_out_irq_cb; /* IRQ line */
|
||||
devcb_write_line m_out_drq_cb; /* DRQ line */
|
||||
};
|
||||
|
||||
// 539x registers
|
||||
enum
|
||||
{
|
||||
};
|
||||
|
||||
// device stuff
|
||||
#define MCFG_NCR539X_ADD(_tag, _clock, _intrf) \
|
||||
MCFG_DEVICE_ADD(_tag, NCR539X, _clock) \
|
||||
MCFG_DEVICE_CONFIG(_intrf)
|
||||
|
||||
class ncr539x_device : public device_t,
|
||||
public NCR539Xinterface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
ncr539x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// our API
|
||||
DECLARE_READ8_MEMBER(read);
|
||||
DECLARE_WRITE8_MEMBER(write);
|
||||
|
||||
void dma_read_data(int bytes, UINT8 *pData);
|
||||
void dma_write_data(int bytes, UINT8 *pData);
|
||||
|
||||
void *get_scsi_device(int id);
|
||||
|
||||
void scan_devices();
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_stop();
|
||||
virtual void device_config_complete();
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
|
||||
private:
|
||||
void fifo_write(UINT8 data);
|
||||
void check_fifo_executable();
|
||||
void exec_fifo();
|
||||
void update_fifo_internal_state(int bytes);
|
||||
|
||||
SCSIInstance *m_scsi_devices[8];
|
||||
|
||||
UINT32 m_xfer_count;
|
||||
UINT32 m_dma_size;
|
||||
UINT8 m_command;
|
||||
UINT8 m_last_id;
|
||||
UINT8 m_timeout;
|
||||
UINT8 m_sync_xfer_period;
|
||||
UINT8 m_sync_offset;
|
||||
UINT8 m_control1, m_control2, m_control3, m_control4;
|
||||
UINT8 m_clock_factor;
|
||||
UINT8 m_forced_test;
|
||||
UINT8 m_data_alignment;
|
||||
|
||||
bool m_selected;
|
||||
bool m_chipid_available, m_chipid_lock;
|
||||
|
||||
static const int m_fifo_size = 16;
|
||||
UINT8 m_fifo_ptr, m_fifo[m_fifo_size];
|
||||
|
||||
int m_xfer_remaining; // amount in the FIFO when we're in data in phase
|
||||
|
||||
// read-only registers
|
||||
UINT8 m_status, m_irq_status, m_internal_state, m_fifo_internal_state;
|
||||
|
||||
static const int m_buffer_size = 2048;
|
||||
|
||||
UINT8 m_buffer[m_buffer_size];
|
||||
int m_buffer_offset, m_buffer_remaining, m_total_data;
|
||||
|
||||
emu_timer *m_operation_timer;
|
||||
|
||||
devcb_resolved_write_line m_out_irq_func;
|
||||
devcb_resolved_write_line m_out_drq_func;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
extern const device_type NCR539X;
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user