Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-05-21 21:29:15 +03:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

Sync with MESS

Browse Source
This commit is contained in:
Nathan Woods 2008-11-11 03:58:52 +00:00
parent 5590dc71fe
commit 2f64840531
7 changed files with 48 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitattributes vendored
View File

@ -238,7 +238,6 @@ src/emu/cpu/m6800/m6800.h svneol=native#text/plain
src/emu/cpu/m68000/m68000.h svneol=native#text/plain src/emu/cpu/m68000/m68000.h svneol=native#text/plain
src/emu/cpu/m68000/m68k.h svneol=native#text/plain src/emu/cpu/m68000/m68k.h svneol=native#text/plain
src/emu/cpu/m68000/m68k_in.c svneol=native#text/plain src/emu/cpu/m68000/m68k_in.c svneol=native#text/plain
src/emu/cpu/m68000/m68kconf.h svneol=native#text/plain
src/emu/cpu/m68000/m68kcpu.c svneol=native#text/plain src/emu/cpu/m68000/m68kcpu.c svneol=native#text/plain
src/emu/cpu/m68000/m68kcpu.h svneol=native#text/plain src/emu/cpu/m68000/m68kcpu.h svneol=native#text/plain
src/emu/cpu/m68000/m68kdasm.c svneol=native#text/plain src/emu/cpu/m68000/m68kdasm.c svneol=native#text/plain

30
src/emu/cpu/m68000/m68000.h
View File

@ -5,6 +5,36 @@
#include "cpuintrf.h" #include "cpuintrf.h"
/* There are 7 levels of interrupt to the 68K.
* A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
*/
#define M68K_IRQ_NONE 0
#define M68K_IRQ_1 1
#define M68K_IRQ_2 2
#define M68K_IRQ_3 3
#define M68K_IRQ_4 4
#define M68K_IRQ_5 5
#define M68K_IRQ_6 6
#define M68K_IRQ_7 7
/* Special interrupt acknowledge values.
* Use these as special returns from the interrupt acknowledge callback
* (specified later in this header).
*/
/* Causes an interrupt autovector (0x18 + interrupt level) to be taken.
* This happens in a real 68K if VPA or AVEC is asserted during an interrupt
* acknowledge cycle instead of DTACK.
*/
#define M68K_INT_ACK_AUTOVECTOR 0xffffffff
/* Causes the spurious interrupt vector (0x18) to be taken
* This happens in a real 68K if BERR is asserted during the interrupt
* acknowledge cycle (i.e. no devices responded to the acknowledge).
*/
#define M68K_INT_ACK_SPURIOUS 0xfffffffe
enum enum
{ {
/* NOTE: M68K_SP fetches the current SP, be it USP, ISP, or MSP */ /* NOTE: M68K_SP fetches the current SP, be it USP, ISP, or MSP */

31
src/emu/cpu/m68000/m68k.h
View File

@ -29,37 +29,6 @@
/* ======================================================================== */ /* ======================================================================== */
/* There are 7 levels of interrupt to the 68K.
* A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
*/
#define M68K_IRQ_NONE 0
#define M68K_IRQ_1 1
#define M68K_IRQ_2 2
#define M68K_IRQ_3 3
#define M68K_IRQ_4 4
#define M68K_IRQ_5 5
#define M68K_IRQ_6 6
#define M68K_IRQ_7 7
/* Special interrupt acknowledge values.
* Use these as special returns from the interrupt acknowledge callback
* (specified later in this header).
*/
/* Causes an interrupt autovector (0x18 + interrupt level) to be taken.
* This happens in a real 68K if VPA or AVEC is asserted during an interrupt
* acknowledge cycle instead of DTACK.
*/
#define M68K_INT_ACK_AUTOVECTOR 0xffffffff
/* Causes the spurious interrupt vector (0x18) to be taken
* This happens in a real 68K if BERR is asserted during the interrupt
* acknowledge cycle (i.e. no devices responded to the acknowledge).
*/
#define M68K_INT_ACK_SPURIOUS 0xfffffffe
/* CPU types for use in m68k_set_cpu_type() */ /* CPU types for use in m68k_set_cpu_type() */
enum enum
{ {

0
src/emu/cpu/m68000/m68kconf.h
View File

16
src/emu/cpu/m68000/m68kmame.c
View File

@ -570,14 +570,14 @@ static CPU_SET_INFO( m68008 )
switch (state) switch (state)
{ {
/* --- the following bits of info are set as 64-bit signed integers --- */ /* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(0, info->i); break; case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(m68k, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(1, info->i); break; case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(m68k, 1, info->i); break;
case CPUINFO_INT_INPUT_STATE + 2: set_irq_line(2, info->i); break; case CPUINFO_INT_INPUT_STATE + 2: set_irq_line(m68k, 2, info->i); break;
case CPUINFO_INT_INPUT_STATE + 3: set_irq_line(3, info->i); break; case CPUINFO_INT_INPUT_STATE + 3: set_irq_line(m68k, 3, info->i); break;
case CPUINFO_INT_INPUT_STATE + 4: set_irq_line(4, info->i); break; case CPUINFO_INT_INPUT_STATE + 4: set_irq_line(m68k, 4, info->i); break;
case CPUINFO_INT_INPUT_STATE + 5: set_irq_line(5, info->i); break; case CPUINFO_INT_INPUT_STATE + 5: set_irq_line(m68k, 5, info->i); break;
case CPUINFO_INT_INPUT_STATE + 6: set_irq_line(6, info->i); break; case CPUINFO_INT_INPUT_STATE + 6: set_irq_line(m68k, 6, info->i); break;
case CPUINFO_INT_INPUT_STATE + 7: set_irq_line(7, info->i); break; case CPUINFO_INT_INPUT_STATE + 7: set_irq_line(m68k, 7, info->i); break;
case CPUINFO_INT_PC: m68k_set_reg(m68k, M68K_REG_PC, info->i&0x00ffffff); break; case CPUINFO_INT_PC: m68k_set_reg(m68k, M68K_REG_PC, info->i&0x00ffffff); break;
case CPUINFO_INT_REGISTER + M68K_PC: m68k_set_reg(m68k, M68K_REG_PC, info->i); break; case CPUINFO_INT_REGISTER + M68K_PC: m68k_set_reg(m68k, M68K_REG_PC, info->i); break;

18
src/emu/cpu/minx/minx.c
View File

@ -121,7 +121,7 @@ static CPU_INIT( minx )
} }
static void minx_reset( void ) static CPU_RESET( minx )
{ {
regs.SP = regs.BA = regs.HL = regs.X = regs.Y = 0; regs.SP = regs.BA = regs.HL = regs.X = regs.Y = 0;
regs.U = regs.V = regs.F = regs.E = regs.I = regs.XI = regs.YI = 0; regs.U = regs.V = regs.F = regs.E = regs.I = regs.XI = regs.YI = 0;
@ -132,7 +132,7 @@ static void minx_reset( void )
} }
static void minx_exit( void ) static CPU_EXIT( minx )
{ {
} }
@ -159,7 +159,7 @@ INLINE UINT16 rdop16( void )
#include "minxops.h" #include "minxops.h"
static int minx_execute( int cycles ) static CPU_EXECUTE( minx )
{ {
UINT32 oldpc; UINT32 oldpc;
UINT8 op; UINT8 op;
@ -204,18 +204,18 @@ static int minx_execute( int cycles )
} }
static void minx_burn( int cycles ) static CPU_BURN( minx )
{ {
minx_icount = 0; minx_icount = 0;
} }
static void minx_set_context( void *src ) static CPU_SET_CONTEXT( minx )
{ {
} }
static void minx_get_context( void *dst ) static CPU_GET_CONTEXT( minx )
{ {
} }
@ -282,7 +282,7 @@ static void minx_set_irq_line( int irqline, int state )
} }
static void minx_set_info( UINT32 state, cpuinfo *info ) static CPU_SET_INFO( minx )
{ {
switch( state ) switch( state )
{ {
@ -308,7 +308,7 @@ static void minx_set_info( UINT32 state, cpuinfo *info )
} }
void minx_get_info( UINT32 state, cpuinfo *info ) CPU_GET_INFO( minx )
{ {
switch( state ) switch( state )
{ {
@ -356,7 +356,7 @@ void minx_get_info( UINT32 state, cpuinfo *info )
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(minx); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(minx); break;
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(minx); break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(minx); break;
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(minx); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(minx); break;
case CPUINFO_PTR_BURN: info->burn = CPU_GET_BURN_NAME(minx); break; case CPUINFO_PTR_BURN: info->burn = CPU_BURN_NAME(minx); break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(minx); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(minx); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &minx_icount; break; case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &minx_icount; break;
case CPUINFO_STR_NAME: strcpy( info->s = cpuintrf_temp_str(), "Minx" ); break; case CPUINFO_STR_NAME: strcpy( info->s = cpuintrf_temp_str(), "Minx" ); break;

2
src/emu/cpuintrf.c
View File

@ -557,7 +557,7 @@ static const struct
{ CPU_TMS34020, CPU_GET_INFO_NAME(tms34020) }, { CPU_TMS34020, CPU_GET_INFO_NAME(tms34020) },
#endif #endif
#if (HAS_TI990_10) #if (HAS_TI990_10)
{ CPU_TI990_10, ti990_CPU_GET_INFO_NAME(10) }, { CPU_TI990_10, CPU_GET_INFO_NAME(ti990_10) },
#endif #endif
#if (HAS_TMS9900) #if (HAS_TMS9900)
{ CPU_TMS9900, CPU_GET_INFO_NAME(tms9900) }, { CPU_TMS9900, CPU_GET_INFO_NAME(tms9900) },