From 2faf681f44d5c87988e4ab3ddaef655753f336c9 Mon Sep 17 00:00:00 2001 From: arbee Date: Sun, 22 Mar 2015 16:34:49 -0400 Subject: [PATCH] iteagle: don't forget the new files (nw) --- src/emu/machine/vrc4373.c | 344 ++++++++++++++++++++++++++++++ src/emu/machine/vrc4373.h | 116 ++++++++++ src/emu/sound/es1373.c | 196 +++++++++++++++++ src/emu/sound/es1373.h | 63 ++++++ src/emu/video/voodoo_pci.c | 81 +++++++ src/emu/video/voodoo_pci.h | 35 +++ src/mame/machine/iteagle_fpga.c | 364 ++++++++++++++++++++++++++++++++ src/mame/machine/iteagle_fpga.h | 91 ++++++++ 8 files changed, 1290 insertions(+) create mode 100644 src/emu/machine/vrc4373.c create mode 100644 src/emu/machine/vrc4373.h create mode 100644 src/emu/sound/es1373.c create mode 100644 src/emu/sound/es1373.h create mode 100644 src/emu/video/voodoo_pci.c create mode 100644 src/emu/video/voodoo_pci.h create mode 100644 src/mame/machine/iteagle_fpga.c create mode 100644 src/mame/machine/iteagle_fpga.h diff --git a/src/emu/machine/vrc4373.c b/src/emu/machine/vrc4373.c new file mode 100644 index 00000000000..e1a3c7eac81 --- /dev/null +++ b/src/emu/machine/vrc4373.c @@ -0,0 +1,344 @@ +#include "vrc4373.h" + +#define LOG_NILE (1) +#define LOG_NILE_MASTER (0) +#define LOG_NILE_TARGET (1) + +const device_type VRC4373 = &device_creator; + +DEVICE_ADDRESS_MAP_START(config_map, 32, vrc4373_device) + AM_RANGE(0x40, 0x43) AM_READWRITE (pcictrl_r, pcictrl_w) + AM_INHERIT_FROM(pci_host_device::config_map) +ADDRESS_MAP_END + +// cpu i/f map +DEVICE_ADDRESS_MAP_START(cpu_map, 32, vrc4373_device) + AM_RANGE(0x00000000, 0x0000007b) AM_READWRITE( vrc4373_device::cpu_if_r, vrc4373_device::cpu_if_w) +ADDRESS_MAP_END + +// Target Window 1 map +DEVICE_ADDRESS_MAP_START(target1_map, 32, vrc4373_device) + AM_RANGE(0x00000000, 0xFFFFFFFF) AM_READWRITE( vrc4373_device::target1_r, vrc4373_device::target1_w) +ADDRESS_MAP_END + +// Target Window 2 map +DEVICE_ADDRESS_MAP_START(target2_map, 32, vrc4373_device) + AM_RANGE(0x00000000, 0xFFFFFFFF) AM_READWRITE( vrc4373_device::target2_r, vrc4373_device::target2_w) +ADDRESS_MAP_END + +vrc4373_device::vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_host_device(mconfig, VRC4373, "NEC VRC4373 System Controller", tag, owner, clock, "vrc4373", __FILE__), + m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32), + m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32) +{ +} + +const address_space_config *vrc4373_device::memory_space_config(address_spacenum spacenum) const +{ + return (spacenum == AS_PROGRAM) ? pci_bridge_device::memory_space_config(spacenum) : (spacenum == AS_DATA) ? &m_mem_config : (spacenum == AS_IO) ? &m_io_config : NULL; +} + +void vrc4373_device::device_start() +{ + pci_host_device::device_start(); + m_cpu = machine().device(cpu_tag); + m_cpu_space = &m_cpu->space(AS_PROGRAM); + memory_space = &space(AS_DATA); + io_space = &space(AS_IO); + + memset(m_cpu_regs, 0, sizeof(m_cpu_regs)); + + memory_window_start = 0; + memory_window_end = 0xffffffff; + memory_offset = 0; + io_window_start = 0; + io_window_end = 0xffffffff; + io_offset = 0x00000000; + status = 0x0280; + m_ram_size = 1<<22; + m_ram_base = 0; + m_simm_size = 1<<21; + m_simm_base = 0; + regenerate_config_mapping(); +} + +void vrc4373_device::device_reset() +{ + pci_device::device_reset(); + memset(m_cpu_regs, 0, sizeof(m_cpu_regs)); + remap_cb(); +} + +void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space, + UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space) +{ + m_cpu_space->unmap_readwrite(0x00000000, 0xffffffff); + + m_cpu_space->install_rom (0x1fc00000, 0x1fcfffff, m_region->base()); + m_cpu_space->install_device(0x0f000000, 0x0f0000ff, *static_cast(this), &vrc4373_device::cpu_map); + // PCI Configuration also mapped at 0x0f000100 + m_cpu_space->install_device(0x0f000100, 0x0f0001ff, *static_cast(this), &vrc4373_device::config_map); + + UINT32 winStart, winEnd, winSize; + + if (m_cpu_regs[NREG_BMCR]&0x8) { + m_cpu_space->install_ram (m_ram_base, m_ram_base+m_ram_size-1, &m_ram[0]); + if (LOG_NILE) + logerror("%s: map_extra ram_size=%08X ram_base=%08X\n", tag(),m_ram_size,m_ram_base); + } + if (m_cpu_regs[NREG_SIMM1]&0x8) { + m_cpu_space->install_ram (m_simm_base, m_simm_base+m_simm_size-1, &m_simm[0]); + if (LOG_NILE) + logerror("%s: map_extra simm_size=%08X simm_base=%08X\n", tag(),m_simm_size,m_simm_base); + } + // PCI Master Window 1 + if (m_cpu_regs[NREG_PCIMW1]&0x1000) { + winStart = m_cpu_regs[NREG_PCIMW1]&0xff000000; + winEnd = winStart | (~(0x80000000 | (((m_cpu_regs[NREG_PCIMW1]>>13)&0x7f)<<24))); + winSize = winEnd - winStart + 1; + m_cpu_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::master1_r), this)); + m_cpu_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::master1_w), this)); + if (LOG_NILE) + logerror("%s: map_extra Master Window 1 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci1_laddr); + } + // PCI Master Window 2 + if (m_cpu_regs[NREG_PCIMW2]&0x1000) { + winStart = m_cpu_regs[NREG_PCIMW2]&0xff000000; + winEnd = winStart | (~(0x80000000 | (((m_cpu_regs[NREG_PCIMW2]>>13)&0x7f)<<24))); + winSize = winEnd - winStart + 1; + m_cpu_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::master2_r), this)); + m_cpu_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::master2_w), this)); + if (LOG_NILE) + logerror("%s: map_extra Master Window 2 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci2_laddr); + } + // PCI IO Window + if (m_cpu_regs[NREG_PCIMIOW]&0x1000) { + winStart = m_cpu_regs[NREG_PCIMIOW]&0xff000000; + winEnd = winStart | (~(0x80000000 | (((m_cpu_regs[NREG_PCIMIOW]>>13)&0x7f)<<24))); + winSize = winEnd - winStart + 1; + m_cpu_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::master_io_r), this)); + m_cpu_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::master_io_w), this)); + if (LOG_NILE) + logerror("%s: map_extra IO Window start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci_io_laddr); + } + // PCI Target Window 1 + if (m_cpu_regs[NREG_PCITW1]&0x1000) { + winStart = m_cpu_regs[NREG_PCITW1]&0xffe00000; + winEnd = winStart | (~(0xf0000000 | (((m_cpu_regs[NREG_PCITW1]>>13)&0x7f)<<21))); + winSize = winEnd - winStart + 1; + memory_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::target1_r), this)); + memory_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::target1_w), this)); + if (LOG_NILE) + logerror("%s: map_extra Target Window 1 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_target1_laddr); + } + // PCI Target Window 2 + if (m_cpu_regs[NREG_PCITW2]&0x1000) { + winStart = m_cpu_regs[NREG_PCITW2]&0xffe00000; + winEnd = winStart | (~(0xf0000000 | (((m_cpu_regs[NREG_PCITW2]>>13)&0x7f)<<21))); + winSize = winEnd - winStart + 1; + memory_space->install_read_handler(winStart, winEnd, 0, 0, read32_delegate(FUNC(vrc4373_device::target2_r), this)); + memory_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(vrc4373_device::target2_w), this)); + if (LOG_NILE) + logerror("%s: map_extra Target Window 2 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_target2_laddr); + } +} + +void vrc4373_device::reset_all_mappings() +{ + pci_device::reset_all_mappings(); +} + +void vrc4373_device::set_cpu_tag(const char *_cpu_tag) +{ + if (LOG_NILE) + logerror("%s: set_cpu_tag\n", tag()); + cpu_tag = _cpu_tag; +} +// PCI bus control +READ32_MEMBER (vrc4373_device::pcictrl_r) +{ + UINT32 result = 0; + if (LOG_NILE) + logerror("%06X:nile pcictrl_r from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER (vrc4373_device::pcictrl_w) +{ + if (LOG_NILE) + logerror("%06X:nile pcictrl_w to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); +} +// PCI Master Window 1 +READ32_MEMBER (vrc4373_device::master1_r) +{ + UINT32 result = this->space(AS_DATA).read_dword(m_pci1_laddr | (offset*4), mem_mask); + if (LOG_NILE_MASTER) + logerror("%06X:nile master1 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER (vrc4373_device::master1_w) +{ + this->space(AS_DATA).write_dword(m_pci1_laddr | (offset*4), data, mem_mask); + if (LOG_NILE_MASTER) + logerror("%06X:nile master1 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); +} + +// PCI Master Window 2 +READ32_MEMBER (vrc4373_device::master2_r) +{ + UINT32 result = this->space(AS_DATA).read_dword(m_pci2_laddr | (offset*4), mem_mask); + if (LOG_NILE_MASTER) + logerror("%06X:nile master2 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER (vrc4373_device::master2_w) +{ + this->space(AS_DATA).write_dword(m_pci2_laddr | (offset*4), data, mem_mask); + if (LOG_NILE_MASTER) + logerror("%06X:nile master2 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); +} + +// PCI Master IO Window +READ32_MEMBER (vrc4373_device::master_io_r) +{ + UINT32 result = this->space(AS_IO).read_dword(m_pci_io_laddr | (offset*4), mem_mask); + if (LOG_NILE_MASTER) + logerror("%06X:nile master io read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER (vrc4373_device::master_io_w) +{ + this->space(AS_IO).write_dword(m_pci_io_laddr | (offset*4), data, mem_mask); + if (LOG_NILE_MASTER) + logerror("%06X:nile master io write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); +} + +// PCI Target Window 1 +READ32_MEMBER (vrc4373_device::target1_r) +{ + UINT32 result = this->space(AS_PROGRAM).read_dword(m_target1_laddr | (offset*4), mem_mask); + if (LOG_NILE_TARGET) + logerror("%06X:nile target1 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER (vrc4373_device::target1_w) +{ + this->space(AS_PROGRAM).write_dword(m_target1_laddr | (offset*4), data, mem_mask); + if (LOG_NILE_TARGET) + logerror("%06X:nile target1 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); +} + +// PCI Target Window 2 +READ32_MEMBER (vrc4373_device::target2_r) +{ + UINT32 result = this->space(AS_PROGRAM).read_dword(m_target2_laddr | (offset*4), mem_mask); + if (LOG_NILE_TARGET) + logerror("%06X:nile target2 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER (vrc4373_device::target2_w) +{ + this->space(AS_PROGRAM).write_dword(m_target2_laddr | (offset*4), data, mem_mask); + if (LOG_NILE_TARGET) + logerror("%06X:nile target2 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); +} + +// CPU I/F +READ32_MEMBER (vrc4373_device::cpu_if_r) +{ + UINT32 result = m_cpu_regs[offset]; + switch (offset) { + case NREG_PCICAR: + result = config_address_r(space, offset); + break; + case NREG_PCICDR: + result = config_data_r(space, offset); + break; + default: + break; + } + if (LOG_NILE) + logerror("%06X:nile read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} + +WRITE32_MEMBER(vrc4373_device::cpu_if_w) +{ + if (LOG_NILE) + logerror("%06X:nile write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + + UINT32 modData; + COMBINE_DATA(&m_cpu_regs[offset]); + switch (offset) { + case NREG_PCIMW1: + m_pci1_laddr = (data&0xff)<<24; + remap_cb(); + break; + case NREG_PCIMW2: + m_pci2_laddr = (data&0xff)<<24; + remap_cb(); + break; + case NREG_PCIMIOW: + m_pci_io_laddr = (data&0xff)<<24; + remap_cb(); + break; + case NREG_PCITW1: + m_target1_laddr = (data&0x7FF)<<21; + break; + case NREG_PCITW2: + m_target2_laddr = (data&0x7FF)<<21; + break; + case NREG_PCICAR: + // Bits in reserved area are used for device selection of type 0 config transactions + // Assuming 23:11 get mapped into device number for configuration + if ((data&0x3) == 0x0) { + // Type 0 transaction + modData = 0; + // Select the device based on one hot bit + for (int i=11; i<24; i++) { + if ((data>>i)&0x1) { + // One hot encoding, bit 11 will mean device 1 + modData = i-10; + break; + } + } + // Re-organize into Type 1 transaction for bus 0 (local bus) + modData = (modData<<11) | (data&0x7ff) | (0x80000000); + } else { + // Type 1 transaction, no modification needed + modData = data; + } + pci_host_device::config_address_w(space, offset, modData); + break; + case NREG_PCICDR: + pci_host_device::config_data_w(space, offset, data); + break; + case NREG_BMCR: + if ((data>>3)&0x1) { + m_ram_size = 1<<22; // 4MB + for (int i=14; i<=15; i++) { + if (!((data>>i)&0x1)) m_ram_size<<=1; + else break; + } + m_ram.resize(m_ram_size/4); + m_ram_base = (data & 0x0fc00000); + } + remap_cb(); + break; + case NREG_SIMM1: + if ((data>>3)&0x1) { + m_simm_size = 1<<21; // 2MB + for (int i=13; i<=17; i++) { + if (!((data>>i)&0x1)) m_simm_size<<=1; + else break; + } + m_simm.resize(m_simm_size/4); + m_simm_base = (data & 0x0fe00000); + } + remap_cb(); + break; + default: + break; + } + +} + diff --git a/src/emu/machine/vrc4373.h b/src/emu/machine/vrc4373.h new file mode 100644 index 00000000000..17fa5de7e9c --- /dev/null +++ b/src/emu/machine/vrc4373.h @@ -0,0 +1,116 @@ +// NEC VRC 4373 System Controller + +#ifndef VRC4373_H +#define VRC4373_H + +#include "pci.h" + +#define MCFG_VRC4373_ADD(_tag, _cpu_tag) \ + MCFG_PCI_HOST_ADD(_tag, VRC4373, 0x005B1033, 0x00, 0x00000000) \ + downcast(device)->set_cpu_tag(_cpu_tag); + +#define VRC4373_PAGESHIFT 12 + +/* NILE 3 registers 0x000-0x0ff */ +#define NREG_BMCR (0x000/4) +#define NREG_SIMM1 (0x004/4) +#define NREG_SIMM2 (0x008/4) +#define NREG_SIMM3 (0x00C/4) +#define NREG_SIMM4 (0x010/4) +#define NREG_PCIMW1 (0x014/4) +#define NREG_PCIMW2 (0x018/4) +#define NREG_PCITW1 (0x01C/4) +#define NREG_PCITW2 (0x020/4) +#define NREG_PCIMIOW (0x024/4) +#define NREG_PCICDR (0x028/4) +#define NREG_PCICAR (0x02C/4) +#define NREG_PCIMB1 (0x030/4) +#define NREG_PCIMB2 (0x034/4) +#define NREG_DMACR1 (0x038/4) +#define NREG_DMAMAR1 (0x03C/4) +#define NREG_DMAPCI1 (0x040/4) +#define NREG_DMACR2 (0x044/4) +#define NREG_DMAMAR2 (0x048/4) +#define NREG_DMAPCI2 (0x04C/4) + +#define NREG_BESR (0x050/4) +#define NREG_ICSR (0x054/4) +#define NREG_DRAMRCR (0x058/4) +#define NREG_BOOTWP (0x05C/4) +#define NREG_PCIEAR (0x060/4) +#define NREG_DMA_WR (0x064/4) +#define NREG_DMA_CMAR (0x068/4) +#define NREG_DMA_CPAR (0x06C/4) +#define NREG_PCIRC (0x070/4) +#define NREG_PCIEN (0x074/4) +#define NREG_PMIR (0x078/4) + +class vrc4373_device : public pci_host_device { +public: + vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + virtual void reset_all_mappings(); + virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space, + UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space); + + + void set_cpu_tag(const char *tag); + + virtual DECLARE_ADDRESS_MAP(config_map, 32); + + DECLARE_READ32_MEMBER( pcictrl_r); + DECLARE_WRITE32_MEMBER( pcictrl_w); + //cpu bus registers + DECLARE_READ32_MEMBER (cpu_if_r); + DECLARE_WRITE32_MEMBER(cpu_if_w); + + DECLARE_READ32_MEMBER (master1_r); + DECLARE_WRITE32_MEMBER(master1_w); + + DECLARE_READ32_MEMBER (master2_r); + DECLARE_WRITE32_MEMBER(master2_w); + + DECLARE_READ32_MEMBER (master_io_r); + DECLARE_WRITE32_MEMBER(master_io_w); + + virtual DECLARE_ADDRESS_MAP(target1_map, 32); + DECLARE_READ32_MEMBER (target1_r); + DECLARE_WRITE32_MEMBER(target1_w); + + virtual DECLARE_ADDRESS_MAP(target2_map, 32); + DECLARE_READ32_MEMBER (target2_r); + DECLARE_WRITE32_MEMBER(target2_w); + +protected: + address_space *m_cpu_space; + virtual const address_space_config *memory_space_config(address_spacenum spacenum) const; + virtual void device_start(); + virtual void device_reset(); + +private: + cpu_device *m_cpu; + const char *cpu_tag; + + address_space_config m_mem_config, m_io_config; + + DECLARE_ADDRESS_MAP(cpu_map, 32); + + UINT32 m_ram_size; + UINT32 m_ram_base; + dynamic_array m_ram; + + UINT32 m_simm_size; + UINT32 m_simm_base; + dynamic_array m_simm; + + + UINT32 m_cpu_regs[0x7c]; + + UINT32 m_pci1_laddr, m_pci2_laddr, m_pci_io_laddr; + UINT32 m_target1_laddr, m_target2_laddr; +}; + + +extern const device_type VRC4373; + +#endif diff --git a/src/emu/sound/es1373.c b/src/emu/sound/es1373.c new file mode 100644 index 00000000000..aae26ba93f9 --- /dev/null +++ b/src/emu/sound/es1373.c @@ -0,0 +1,196 @@ +#include "es1373.h" + +#define LOG_ES (1) + +const device_type ES1373 = &device_creator; + +DEVICE_ADDRESS_MAP_START(map, 32, es1373_device) + AM_RANGE(0x00, 0x3f) AM_READWRITE (reg_r, reg_w) +ADDRESS_MAP_END + +es1373_device::es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_device(mconfig, ES1373, "Creative Labs Ensoniq AudioPCI97 ES1373", tag, owner, clock, "es1373", __FILE__) +{ +} + +void es1373_device::device_start() +{ + pci_device::device_start(); + add_map(0x40, M_IO, FUNC(es1373_device::map)); +} + +void es1373_device::device_reset() +{ + pci_device::device_reset(); + memset(m_es_regs, 0, sizeof(m_es_regs)); + memset(m_ac97_regs, 0, sizeof(m_ac97_regs)); + m_ac97_regs[0] = 0x0800; +} + +READ32_MEMBER (es1373_device::reg_r) +{ + UINT32 result = m_es_regs[offset]; + switch (offset) { + case ES_CODEC: + break; + case ES_HOST_IF0: // 0x30 + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + result = m_dac1_fr.pci_addr; + break; + case 0xd: + result = m_adc_fr.pci_addr; + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 Read UART offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask); + default: + break; + } + break; + case ES_HOST_IF1: // 0x34 + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + result = (m_dac1_fr.curr_count<<16) | m_dac1_fr.buff_size; + break; + case 0xd: + result = (m_adc_fr.curr_count<<16) | m_adc_fr.buff_size; + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 write UART offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask); + default: + break; + } + break; + case ES_HOST_IF2: // 0x38 + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + result = m_dac2_fr.pci_addr; + break; + case 0xd: + logerror("%06X:ES1373 read Unknown place offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask); + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 read UART offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask); + default: + break; + } + break; + case ES_HOST_IF3: // 0x3C + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + result = (m_dac2_fr.curr_count<<16) | m_dac2_fr.buff_size; + break; + case 0xd: + logerror("%06X:ES1373 read Unknown place offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask); + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 read UART offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask); + default: + break; + } + break; + default: + break; + } + if (LOG_ES) + logerror("%06X:ES1373 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask); + return result; +} + +WRITE32_MEMBER(es1373_device::reg_w) +{ + COMBINE_DATA(&m_es_regs[offset]); + switch (offset) { + case ES_SRC_IF: + if (data&(1<<24)) { + // Write to Sample Rate Converter Ram + m_src_ram[(data>>25)&0x7F] = data&0xFFFF; + } else { + // Read From Sample Rate Converter Ram + m_es_regs[offset] = (data&0xFFFF0000) | m_src_ram[(data>>25)&0x7F]; + } + break; + case ES_CODEC: + if (data&(1<<23)) { + // Read from AC97 codec registers + m_es_regs[offset] = (data&0xFFFF0000) | m_ac97_regs[(data>>16)&0x7f] | 0x80000000; + } else { + // Write to AC97 codec registers + m_ac97_regs[(data>>16)&0x7f] = data&0xFFFF; + } + break; + case ES_HOST_IF0: // 0x30 + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + m_dac1_fr.pci_addr = data; + break; + case 0xd: + m_adc_fr.pci_addr = data; + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + default: + break; + } + break; + case ES_HOST_IF1: // 0x34 + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + m_dac1_fr.curr_count = (data>>16)&0xffff; + m_dac1_fr.buff_size = data&0xffff; + break; + case 0xd: + m_adc_fr.curr_count = (data>>16)&0xffff; + m_adc_fr.buff_size = data&0xffff; + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + default: + break; + } + break; + case ES_HOST_IF2: // 0x38 + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + m_dac2_fr.pci_addr = data; + break; + case 0xd: + logerror("%06X:ES1373 write Unknown place offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + default: + break; + } + break; + case ES_HOST_IF3: // 0x3C + switch (m_es_regs[ES_MEM_PAGE]&0xf) { + case 0xc: + m_dac2_fr.curr_count = (data>>16)&0xffff; + m_dac2_fr.buff_size = data&0xffff; + break; + case 0xd: + logerror("%06X:ES1373 write Unknown place offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + break; + case 0xe: + case 0xf: + logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + default: + break; + } + break; + default: + break; + } + + if (LOG_ES) + logerror("%06X:ES1373 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); + +} diff --git a/src/emu/sound/es1373.h b/src/emu/sound/es1373.h new file mode 100644 index 00000000000..b2ee13f1feb --- /dev/null +++ b/src/emu/sound/es1373.h @@ -0,0 +1,63 @@ +// Creative Labs Ensonic AudioPCI97 ES1373 + +#ifndef ES1373_H +#define ES1373_H + +#include "machine/pci.h" + +#define MCFG_ES1373_ADD(_tag) \ + MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371) + +/* Ensonic ES1373 registers 0x00-0x3f */ +#define ES_INT_CS_CTRL (0x00/4) +#define ES_INT_CS_STATUS (0x04/4) +#define ES_UART_DATA (0x08/4) +#define ES_UART_STATUS (0x09/4) +#define ES_UART_CTRL (0x09/4) +#define ES_UART_RSVD (0x0A/4) +#define ES_MEM_PAGE (0x0C/4) +#define ES_SRC_IF (0x10/4) +#define ES_CODEC (0x14/4) +#define ES_LEGACY (0x18/4) +#define ES_CHAN_CTRL (0x1C/4) +#define ES_SERIAL_CTRL (0x20/4) +#define ES_DAC1_CNT (0x24/4) +#define ES_DAC2_CNT (0x28/4) +#define ES_ADC_CNT (0x2C/4) +#define ES_ADC_CNT (0x2C/4) +#define ES_HOST_IF0 (0x30/4) +#define ES_HOST_IF1 (0x34/4) +#define ES_HOST_IF2 (0x38/4) +#define ES_HOST_IF3 (0x3C/4) + +struct frame_reg { + UINT32 pci_addr; + UINT16 curr_count; + UINT16 buff_size; + frame_reg() : pci_addr(0), curr_count(0), buff_size(0) {} +}; + +class es1373_device : public pci_device { +public: + es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + DECLARE_READ32_MEMBER (reg_r); + DECLARE_WRITE32_MEMBER(reg_w); + +protected: + virtual void device_start(); + virtual void device_reset(); + +private: + DECLARE_ADDRESS_MAP(map, 32); + UINT16 m_ac97_regs[0x80]; + UINT32 m_es_regs[0x10]; + UINT16 m_src_ram[0x80]; + frame_reg m_dac1_fr; + frame_reg m_dac2_fr; + frame_reg m_adc_fr; +}; + +extern const device_type ES1373; + +#endif diff --git a/src/emu/video/voodoo_pci.c b/src/emu/video/voodoo_pci.c new file mode 100644 index 00000000000..2b7a6f07433 --- /dev/null +++ b/src/emu/video/voodoo_pci.c @@ -0,0 +1,81 @@ +#include "voodoo_pci.h" + +static MACHINE_CONFIG_FRAGMENT( voodoo_pci ) + MCFG_DEVICE_ADD("voodoo", VOODOO_BANSHEE, STD_VOODOO_BANSHEE_CLOCK) + MCFG_VOODOO_FBMEM(16) + MCFG_VOODOO_SCREEN_TAG("screen") + MCFG_VOODOO_CPU_TAG(":maincpu") +MACHINE_CONFIG_END + +machine_config_constructor voodoo_pci_device::device_mconfig_additions() const +{ + return MACHINE_CONFIG_NAME( voodoo_pci ); +} + +const device_type VOODOO_PCI = &device_creator; + +DEVICE_ADDRESS_MAP_START(reg_map, 32, voodoo_pci_device) + AM_RANGE(0x0, 0x01ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_r, banshee_w) +ADDRESS_MAP_END +DEVICE_ADDRESS_MAP_START(lfb_map, 32, voodoo_pci_device) + AM_RANGE(0x0, 0x00ffffff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_fb_r, banshee_fb_w) +ADDRESS_MAP_END +DEVICE_ADDRESS_MAP_START(io_map, 32, voodoo_pci_device) + AM_RANGE(0x000, 0x0ff) AM_DEVREADWRITE("voodoo", voodoo_banshee_device, banshee_io_r, banshee_io_w) +ADDRESS_MAP_END + +voodoo_pci_device::voodoo_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_device(mconfig, VOODOO_PCI, "Voodoo PCI", tag, owner, clock, "voodoo_pci", __FILE__), + m_voodoo(*this, "voodoo") +{ +} + +void voodoo_pci_device::device_start() +{ + pci_device::device_start(); + add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::reg_map)); + add_map(16*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map)); + add_map(256, M_IO, FUNC(voodoo_pci_device::io_map)); +} + +void voodoo_pci_device::device_reset() +{ + pci_device::device_reset(); +} + +void voodoo_pci_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space, + UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space) +{ + logerror("%s: map_extra\n", tag()); + // Really awkward way of getting vga address space mapped + // Should really be dependent on voodoo VGAINIT0 bit 8 and IO base + 0xc3 bit 0 + if (1) { + // io map is on bank_infos[2] + bank_info &bi = bank_infos[2]; + if(bi.adr==-1) + return; + if(UINT32(bi.adr) == UINT32(~(bi.size - 1))) + return; + + UINT64 start; + address_space *space; + if(bi.flags & M_IO) { + space = io_space; + start = bi.adr + io_offset; + } else { + space = memory_space; + start = bi.adr + memory_offset; + } + // The mapping needs to only check high address bits + start = (start & 0xFFFF0000) + 0x300; + UINT64 end = (start & 0xFFFF0000) + 0x3ef; + space->install_device_delegate(start, end, *this, bi.map); + logerror("%s: map %s at %0*x-%0*x\n", tag(), bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end)); + } + +} + +UINT32 voodoo_pci_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + return voodoo_update(m_voodoo, bitmap, cliprect) ? 0 : UPDATE_HAS_NOT_CHANGED; +} diff --git a/src/emu/video/voodoo_pci.h b/src/emu/video/voodoo_pci.h new file mode 100644 index 00000000000..878c564e4b8 --- /dev/null +++ b/src/emu/video/voodoo_pci.h @@ -0,0 +1,35 @@ +// 3dfx Voodoo Graphics SST-1/2 emulator. + +#ifndef VOODOO_PCI_H +#define VOODOO_PCI_H + +#include "machine/pci.h" +#include "voodoo.h" + +#define MCFG_VOODOO_ADD(_tag) \ + MCFG_PCI_DEVICE_ADD(_tag, VOODOO_PCI, 0x121a0005, 0x02, 0x000003, 0x000000) + +class voodoo_pci_device : public pci_device { +public: + voodoo_pci_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space, + UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space); + // optional information overrides + virtual machine_config_constructor device_mconfig_additions() const; + UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + +protected: + virtual void device_start(); + virtual void device_reset(); + +private: + required_device m_voodoo; + + DECLARE_ADDRESS_MAP(reg_map, 32); + DECLARE_ADDRESS_MAP(lfb_map, 32); + DECLARE_ADDRESS_MAP(io_map, 32); +}; + +extern const device_type VOODOO_PCI; + +#endif diff --git a/src/mame/machine/iteagle_fpga.c b/src/mame/machine/iteagle_fpga.c new file mode 100644 index 00000000000..22f907ddcdd --- /dev/null +++ b/src/mame/machine/iteagle_fpga.c @@ -0,0 +1,364 @@ +#include "iteagle_fpga.h" +#include "coreutil.h" + +#define LOG_FPGA (1) +#define LOG_RTC (0) +#define LOG_EEPROM (1) +#define LOG_IDE (0) +#define LOG_IDE_CTRL (0) + + +const device_type ITEAGLE_FPGA = &device_creator; + +DEVICE_ADDRESS_MAP_START(ctrl_map, 32, iteagle_fpga_device) + AM_RANGE(0x000, 0x02f) AM_READWRITE(ctrl_r, ctrl_w) +ADDRESS_MAP_END + +DEVICE_ADDRESS_MAP_START(fpga_map, 32, iteagle_fpga_device) + AM_RANGE(0x000, 0x01f) AM_READWRITE(fpga_r, fpga_w) +ADDRESS_MAP_END + +DEVICE_ADDRESS_MAP_START(rtc_map, 32, iteagle_fpga_device) + AM_RANGE(0x000, 0x800) AM_READWRITE(rtc_r, rtc_w) +ADDRESS_MAP_END + +iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__) +{ +} + +void iteagle_fpga_device::device_start() +{ + pci_device::device_start(); + status = 0x5555; + command = 0x5555; + + add_map(sizeof(m_ctrl_regs), M_IO, FUNC(iteagle_fpga_device::ctrl_map)); + // ctrl defaults to base address 0x00000000 + bank_infos[0].adr = 0x00000000 & (~(bank_infos[0].size - 1)); + + add_map(sizeof(m_fpga_regs), M_IO, FUNC(iteagle_fpga_device::fpga_map)); + // fpga defaults to base address 0x00000300 + bank_infos[1].adr = 0x00000300 & (~(bank_infos[1].size - 1)); + + add_map(sizeof(m_rtc_regs), M_MEM, FUNC(iteagle_fpga_device::rtc_map)); + // RTC defaults to base address 0x000c0000 + bank_infos[2].adr = 0x000c0000 & (~(bank_infos[2].size - 1)); +} + +void iteagle_fpga_device::device_reset() +{ + pci_device::device_reset(); + memset(m_ctrl_regs, 0, sizeof(m_ctrl_regs)); + memset(m_fpga_regs, 0, sizeof(m_fpga_regs)); + memset(m_rtc_regs, 0, sizeof(m_rtc_regs)); + // 0x23 & 0x20 = IDE LED + m_ctrl_regs[0x10/4] = 0x00000000; // 0xFFFFFFFF causes a write of 0xFFFEFFFF then 0xFFFFFFFF // Not sure + // 0x00&0x2 == 1 for boot + m_fpga_regs[0x00/4] = 0xC0000002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low + //m_fpga_regs[0x308/4]=0x0000ffff; // Low 16 bits gets read alot? + m_fpga_regs[0x08/4]=0x00000000; // Low 16 bits gets read alot? + m_prev_reg = 0; +} + +READ32_MEMBER( iteagle_fpga_device::ctrl_r ) +{ + UINT32 result = m_fpga_regs[offset]; + switch (offset) { + case 0x0/4: + if (LOG_FPGA) + logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + default: + if (LOG_FPGA) + logerror("%s:fpga ctrl_r from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + } + return result; +} + +WRITE32_MEMBER( iteagle_fpga_device::ctrl_w ) +{ + COMBINE_DATA(&m_fpga_regs[offset]); + switch (offset) { + case 0x20/4: // IDE LED and ?? + if (ACCESSING_BITS_16_23) { + // Probably watchdog + } else if (ACCESSING_BITS_24_31) { + // Bit 1 is IDE LED + } else { + if (LOG_FPGA) + logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + } + break; + default: + if (LOG_FPGA) + logerror("%s:fpga ctrl_w to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + break; + } +} + +READ32_MEMBER( iteagle_fpga_device::fpga_r ) +{ + UINT32 result = m_fpga_regs[offset]; + switch (offset) { + case 0x00/4: + if (LOG_FPGA && (m_prev_reg != offset && m_prev_reg != (0x08/4))) + logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + case 0x04/4: + result = (result & 0xFF0FFFFF) | (machine().root_device().ioport("SW5")->read()<<20); // Resolution + if (LOG_FPGA) + logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + + case 0x08/4: + if (LOG_FPGA && (m_prev_reg != offset && m_prev_reg != (0x00/4))) + logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + default: + if (LOG_FPGA) + logerror("%s:fpga read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + } + m_prev_reg = offset; + return result; +} + +WRITE32_MEMBER( iteagle_fpga_device::fpga_w ) +{ + UINT8 byte; + + COMBINE_DATA(&m_fpga_regs[offset]); + switch (offset) { + case 0x04/4: + if (ACCESSING_BITS_0_7) { + // ATMEL Chip access. Returns version id's when bit 7 is set. + byte = data & 0xFF; + if (byte & 0x80) { + switch (byte&0x3) { + case 0: + m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>4)&0xF); + break; + case 1: + m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>8)&0xF); + break; + case 2: + m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>12)&0xF); + break; + case 3: + m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((machine().root_device().ioport("VERSION")->read()>>0)&0xF); + break; + } + } // Else??? + } + if (LOG_FPGA) + logerror("%s:fpga write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + break; + default: + if (LOG_FPGA) + logerror("%s:fpga write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + break; + } +} +//************************************* +//* RTC M48T02 +//************************************* +READ32_MEMBER( iteagle_fpga_device::rtc_r ) +{ + UINT32 result = m_rtc_regs[offset]; + + switch (offset) { + default: + if (LOG_RTC) + logerror("%s:RTC read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + } + return result; +} +WRITE32_MEMBER( iteagle_fpga_device::rtc_w ) +{ + system_time systime; + int raw[8]; + + COMBINE_DATA(&m_rtc_regs[offset]); + switch (offset) { + case 0x7F8/4: // M48T02 time + if (data & mem_mask & 0x40) { + // get the current date/time from the core + machine().current_datetime(systime); + raw[0] = 0x40; + raw[1] = dec_2_bcd(systime.local_time.second); + raw[2] = dec_2_bcd(systime.local_time.minute); + raw[3] = dec_2_bcd(systime.local_time.hour); + + raw[4] = dec_2_bcd((systime.local_time.weekday != 0) ? systime.local_time.weekday : 7); + raw[5] = dec_2_bcd(systime.local_time.mday); + raw[6] = dec_2_bcd(systime.local_time.month + 1); + raw[7] = dec_2_bcd(systime.local_time.year - 1900); // Epoch is 1900 + m_rtc_regs[0x7F8/4] = (raw[3]<<24) | (raw[2]<<16) | (raw[1]<<8) | (raw[0] <<0); + //m_rtc_regs[0x7FC/4] = (raw[7]<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0); + m_rtc_regs[0x7FC/4] = (0x95<<24) | (raw[6]<<16) | (raw[5]<<8) | (raw[4] <<0); + } + if (LOG_RTC) + logerror("%s:RTC write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + + break; + default: + if (LOG_RTC) + logerror("%s:RTC write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + break; + } + +} + +//************************************ +// Attached serial EEPROM +//************************************ + +const device_type ITEAGLE_EEPROM = &device_creator; + +DEVICE_ADDRESS_MAP_START(eeprom_map, 32, iteagle_eeprom_device) + AM_RANGE(0x0000, 0x000F) AM_READWRITE(eeprom_r, eeprom_w) AM_SHARE("eeprom") +ADDRESS_MAP_END + +static MACHINE_CONFIG_FRAGMENT( iteagle_eeprom ) + MCFG_EEPROM_SERIAL_93C46_ADD("eeprom") +MACHINE_CONFIG_END + +machine_config_constructor iteagle_eeprom_device::device_mconfig_additions() const +{ + return MACHINE_CONFIG_NAME( iteagle_eeprom ); +} + +iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_device(mconfig, ITEAGLE_EEPROM, "ITEagle EEPROM AT93C46", tag, owner, clock, "eeprom", __FILE__), + m_eeprom(*this, "eeprom") +{ +} + +void iteagle_eeprom_device::device_start() +{ + pci_device::device_start(); + skip_map_regs(1); + add_map(0x10, M_IO, FUNC(iteagle_eeprom_device::eeprom_map)); +} + +void iteagle_eeprom_device::device_reset() +{ + pci_device::device_reset(); +} + +READ32_MEMBER( iteagle_eeprom_device::eeprom_r ) +{ + UINT32 result = 0; + + switch (offset) { + case 0xC/4: // I2C Handler + if (ACCESSING_BITS_16_23) { + result = m_eeprom->do_read()<<(16+3); + } else { + if (LOG_EEPROM) + logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + } + break; + default: + if (LOG_EEPROM) + logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + break; + } + return result; +} + +WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w ) +{ + switch (offset) { + case 0xC/4: // I2C Handler + if (ACCESSING_BITS_16_23) { + m_eeprom->di_write((data & 0x040000) >> (16+2)); + m_eeprom->cs_write((data & 0x020000) ? ASSERT_LINE : CLEAR_LINE); + m_eeprom->clk_write((data & 0x010000) ? ASSERT_LINE : CLEAR_LINE); + } else { + if (LOG_EEPROM) + logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + } + break; + default: + if (LOG_EEPROM) + logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); + break; + } +} + +//************************************ +// Attached IDE Controller +//************************************ + +const device_type ITEAGLE_IDE = &device_creator; + +DEVICE_ADDRESS_MAP_START(ide_map, 32, iteagle_ide_device) + AM_RANGE(0x0, 0xf) AM_READWRITE(ide_r, ide_w) +ADDRESS_MAP_END + +DEVICE_ADDRESS_MAP_START(ide_ctrl_map, 32, iteagle_ide_device) + AM_RANGE(0x0, 0x3) AM_READWRITE(ide_ctrl_r, ide_ctrl_w) +ADDRESS_MAP_END + + +static MACHINE_CONFIG_FRAGMENT( iteagle_ide ) + MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true) + MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM) +MACHINE_CONFIG_END + +machine_config_constructor iteagle_ide_device::device_mconfig_additions() const +{ + return MACHINE_CONFIG_NAME( iteagle_ide ); +} +iteagle_ide_device::iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_device(mconfig, ITEAGLE_IDE, "ITEagle IDE Controller", tag, owner, clock, "ide", __FILE__), + m_ide(*this, "ide") +{ +} + +void iteagle_ide_device::device_start() +{ + pci_device::device_start(); + add_map(0x10, M_IO, FUNC(iteagle_ide_device::ide_map)); + bank_infos[0].adr = 0x1f0; + add_map(0x4, M_IO, FUNC(iteagle_ide_device::ide_ctrl_map)); + bank_infos[1].adr = 0x3f4; +} + +void iteagle_ide_device::device_reset() +{ + pci_device::device_reset(); +} +//************************************* +//* IDE +//************************************* +READ32_MEMBER( iteagle_ide_device::ide_r ) +{ + UINT32 result = m_ide->read_cs0(space, offset, mem_mask); + if (LOG_IDE) + logerror("%s:ide_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER( iteagle_ide_device::ide_w ) +{ + m_ide->write_cs0(space, offset, data, mem_mask); + if (LOG_IDE) + logerror("%s:ide_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); +} +READ32_MEMBER( iteagle_ide_device::ide_ctrl_r ) +{ + UINT32 result = m_ide->read_cs1(space, offset+1, mem_mask); + if (LOG_IDE_CTRL) + logerror("%s:ide_ctrl_r read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); + return result; +} +WRITE32_MEMBER( iteagle_ide_device::ide_ctrl_w ) +{ + m_ide->write_cs1(space, offset+1, data, mem_mask); + if (LOG_IDE_CTRL) + logerror("%s:ide_ctrl_w write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); +} diff --git a/src/mame/machine/iteagle_fpga.h b/src/mame/machine/iteagle_fpga.h new file mode 100644 index 00000000000..acc4bd85b00 --- /dev/null +++ b/src/mame/machine/iteagle_fpga.h @@ -0,0 +1,91 @@ +//************************************* +// iteagle fpga device +//************************************* +#ifndef ITEAGLE_FPGA_H +#define ITEAGLE_FPGA_H + +#include "machine/pci.h" +#include "machine/idectrl.h" +#include "machine/eepromser.h" + +#define MCFG_ITEAGLE_FPGA_ADD(_tag) \ + MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_FPGA, 0x55CC33AA, 0xAA, 0xAAAAAA, 0x00) + +#define MCFG_ITEAGLE_EEPROM_ADD(_tag) \ + MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_EEPROM, 0xAABBCCDD, 0x00, 0x088000, 0x00) + +#define MCFG_ITEAGLE_IDE_ADD(_tag) \ + MCFG_PCI_DEVICE_ADD(_tag, ITEAGLE_IDE, 0x11223344, 0x00, 0x010100, 0x00) + +class iteagle_fpga_device : public pci_device { +public: + iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual void device_start(); + virtual void device_reset(); + +private: + + UINT32 m_ctrl_regs[0x30]; + UINT32 m_fpga_regs[0x20]; + UINT32 m_rtc_regs[0x800]; + UINT32 m_prev_reg; + + DECLARE_ADDRESS_MAP(rtc_map, 32); + DECLARE_ADDRESS_MAP(fpga_map, 32); + DECLARE_ADDRESS_MAP(ctrl_map, 32); + + DECLARE_READ32_MEMBER( ctrl_r ); + DECLARE_WRITE32_MEMBER( ctrl_w ); + DECLARE_READ32_MEMBER( fpga_r ); + DECLARE_WRITE32_MEMBER( fpga_w ); + DECLARE_READ32_MEMBER( rtc_r ); + DECLARE_WRITE32_MEMBER( rtc_w ); +}; + +class iteagle_eeprom_device : public pci_device { +public: + iteagle_eeprom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + // optional information overrides + virtual machine_config_constructor device_mconfig_additions() const; + + required_device m_eeprom; + +protected: + virtual void device_start(); + virtual void device_reset(); + +private: + DECLARE_ADDRESS_MAP(eeprom_map, 32); + DECLARE_READ32_MEMBER( eeprom_r ); + DECLARE_WRITE32_MEMBER( eeprom_w ); +}; + +class iteagle_ide_device : public pci_device { +public: + iteagle_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + // optional information overrides + virtual machine_config_constructor device_mconfig_additions() const; + + required_device m_ide; + +protected: + virtual void device_start(); + virtual void device_reset(); + +private: + DECLARE_ADDRESS_MAP(ide_map, 32); + DECLARE_ADDRESS_MAP(ide_ctrl_map, 32); + + DECLARE_READ32_MEMBER( ide_r ); + DECLARE_WRITE32_MEMBER( ide_w ); + DECLARE_READ32_MEMBER( ide_ctrl_r ); + DECLARE_WRITE32_MEMBER( ide_ctrl_w ); +}; + +extern const device_type ITEAGLE_FPGA; +extern const device_type ITEAGLE_EEPROM; +extern const device_type ITEAGLE_IDE; + +#endif