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https://github.com/holub/mame
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New non-working machines
------------------------ Convergent Miniframe [rfka01, R. Belmont]
This commit is contained in:
arbee
parent
b0ab451ced
commit
2fb457352d
@ -3491,6 +3491,7 @@ files {
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MAME_DIR .. "src/mame/drivers/micronic.cpp",
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MAME_DIR .. "src/mame/includes/micronic.h",
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MAME_DIR .. "src/mame/drivers/mini2440.cpp",
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MAME_DIR .. "src/mame/drivers/miniframe.cpp"
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MAME_DIR .. "src/mame/drivers/minitel_2_rpic.cpp",
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MAME_DIR .. "src/mame/drivers/mmd1.cpp",
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MAME_DIR .. "src/mame/drivers/mod8.cpp",
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280
src/mame/drivers/miniframe.cpp
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280
src/mame/drivers/miniframe.cpp
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@ -0,0 +1,280 @@
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// license:GPL-2.0+
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// copyright-holders:Dirk Best, R. Belmont
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/***************************************************************************
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Convergent Miniframe
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Preliminary driver by R. Belmont based on unixpc.cpp by Dirk Best & R. Belmont
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***************************************************************************/
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#include "emu.h"
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#include "cpu/m68000/m68000.h"
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#include "machine/ram.h"
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#include "machine/wd_fdc.h"
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#include "machine/bankdev.h"
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#include "machine/pit8253.h"
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#include "machine/pic8259.h"
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#include "screen.h"
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/***************************************************************************
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DRIVER STATE
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***************************************************************************/
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class miniframe_state : public driver_device
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{
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public:
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miniframe_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_ram(*this, RAM_TAG),
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m_wd2797(*this, "wd2797"),
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m_floppy(*this, "wd2797:0:525dd"),
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m_ramrombank(*this, "ramrombank"),
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m_mapram(*this, "mapram")
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{ }
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required_device<m68010_device> m_maincpu;
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required_device<ram_device> m_ram;
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required_device<wd2797_device> m_wd2797;
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required_device<floppy_image_device> m_floppy;
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required_device<address_map_bank_device> m_ramrombank;
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uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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virtual void machine_start() override;
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virtual void machine_reset() override;
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DECLARE_READ16_MEMBER(ram_mmu_r);
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DECLARE_WRITE16_MEMBER(ram_mmu_w);
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DECLARE_WRITE16_MEMBER(general_ctrl_w);
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DECLARE_WRITE_LINE_MEMBER( wd2797_intrq_w );
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DECLARE_WRITE_LINE_MEMBER( wd2797_drq_w );
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required_shared_ptr<uint16_t> m_mapram;
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private:
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uint16_t *m_ramptr;
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uint32_t m_ramsize;
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uint16_t m_diskdmasize;
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uint32_t m_diskdmaptr;
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bool m_fdc_intrq;
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};
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/***************************************************************************
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MEMORY
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***************************************************************************/
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static constexpr unsigned MMU_MAX_PAGES = 1024;
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static constexpr uint16_t MMU_WRITE_ENABLE = 0x8000;
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static constexpr uint16_t MMU_STATUS_MASK = 0x6000;
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static constexpr uint16_t MMU_STATUS_NOT_PRESENT = 0x0000;
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static constexpr uint16_t MMU_STATUS_PRESENT_NOT_ACCESSED = 0x2000;
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static constexpr uint16_t MMU_STATUS_ACCESSED_NOT_WRITTEN = 0x4000;
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static constexpr uint16_t MMU_STATUS_ACCESSED_WRITTEN = 0x6000;
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READ16_MEMBER( miniframe_state::ram_mmu_r )
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{
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uint8_t fc = m_maincpu->get_fc();
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uint16_t mapentry = m_mapram[(offset >> 11) & 0x7ff];
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if ((offset < ((512*1024)>>1)) && (fc != M68K_FC_SUPERVISOR_DATA) && (fc != M68K_FC_SUPERVISOR_PROGRAM))
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{
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fatalerror("mmu: user mode access to lower 512K, need to generate a fault\n");
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}
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if ((mapentry & MMU_STATUS_MASK) != MMU_STATUS_NOT_PRESENT)
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{
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uint32_t addr = (offset & 0x7ff) | ((mapentry & 0xfff) << 11);
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//printf("mmu_r: orig %x entry %04x xlate %x\n", offset, mapentry, addr);
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// indicate page has been read
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if ((mapentry & MMU_STATUS_MASK) == MMU_STATUS_PRESENT_NOT_ACCESSED)
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{
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m_mapram[(offset >> 11) & 0x7ff] &= ~MMU_STATUS_MASK;
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m_mapram[(offset >> 11) & 0x7ff] |= MMU_STATUS_ACCESSED_NOT_WRITTEN;
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}
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return m_ramptr[addr];
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}
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else
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{
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fatalerror("miniframe: invalid MMU page accessed, need to throw a fault\n");
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}
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}
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WRITE16_MEMBER( miniframe_state::ram_mmu_w )
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{
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uint8_t fc = m_maincpu->get_fc();
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uint16_t mapentry = m_mapram[(offset >> 11) & 0x7ff];
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if ((offset < ((512*1024)>>1)) && (fc != M68K_FC_SUPERVISOR_DATA) && (fc != M68K_FC_SUPERVISOR_PROGRAM))
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{
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fatalerror("mmu: user mode access to lower 512K, need to generate a fault\n");
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}
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if ((mapentry & MMU_STATUS_MASK) != MMU_STATUS_NOT_PRESENT)
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{
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uint32_t addr = (offset & 0x7ff) | ((mapentry & 0xfff) << 11);
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//printf("mmu_w: orig %x entry %04x xlate %x\n", offset, mapentry, addr);
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if (!(mapentry & MMU_WRITE_ENABLE) && (fc != M68K_FC_SUPERVISOR_PROGRAM) && (fc != M68K_FC_SUPERVISOR_DATA))
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{
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fatalerror("mmu: write protection violation, need to throw a fault\n");
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}
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// indicate page has been written
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// we know it's OK to just OR this
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m_mapram[(offset >> 11) & 0x7ff] |= MMU_STATUS_ACCESSED_WRITTEN;
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COMBINE_DATA(&m_ramptr[addr]);
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}
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else
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{
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fatalerror("miniframe: invalid MMU page accessed, need to throw a fault\n");
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}
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}
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WRITE16_MEMBER( miniframe_state::general_ctrl_w )
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{
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if (data & 0x1000) // ROM mirror at 0 if set
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{
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m_ramrombank->set_bank(1);
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}
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else
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{
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m_ramrombank->set_bank(0);
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}
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logerror("%x to general_ctrl_w\n", data);
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}
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void miniframe_state::machine_start()
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{
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m_ramptr = (uint16_t *)m_ram->pointer();
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m_ramsize = m_ram->size();
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}
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void miniframe_state::machine_reset()
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{
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// force ROM into lower mem on reset
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m_ramrombank->set_bank(0);
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// reset cpu so that it can pickup the new values
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m_maincpu->reset();
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// invalidate all pages by clearing all entries
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memset(m_mapram, 0, MMU_MAX_PAGES * sizeof(uint16_t));
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}
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/***************************************************************************
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VIDEO
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***************************************************************************/
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uint32_t miniframe_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
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{
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return 0;
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}
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/***************************************************************************
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ADDRESS MAPS
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***************************************************************************/
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static ADDRESS_MAP_START( miniframe_mem, AS_PROGRAM, 16, miniframe_state )
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AM_RANGE(0x000000, 0x3fffff) AM_DEVICE("ramrombank", address_map_bank_device, amap16)
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AM_RANGE(0x400000, 0x4007ff) AM_RAM AM_SHARE("mapram")
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AM_RANGE(0x450000, 0x450001) AM_WRITE(general_ctrl_w)
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AM_RANGE(0x800000, 0x81ffff) AM_ROM AM_REGION("bootrom", 0)
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AM_RANGE(0xc00000, 0xc00007) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0x00ff)
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AM_RANGE(0xc40000, 0xc40007) AM_DEVREADWRITE8("baudgen", pit8253_device, read, write, 0x00ff)
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AM_RANGE(0xc90000, 0xc90003) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0x00ff)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( ramrombank_map, AS_PROGRAM, 16, miniframe_state )
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AM_RANGE(0x000000, 0x3fffff) AM_ROM AM_REGION("bootrom", 0)
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AM_RANGE(0x400000, 0x7fffff) AM_READWRITE(ram_mmu_r, ram_mmu_w)
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ADDRESS_MAP_END
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/***************************************************************************
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INPUT PORTS
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***************************************************************************/
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static INPUT_PORTS_START( miniframe )
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INPUT_PORTS_END
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/***************************************************************************
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MACHINE DRIVERS
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***************************************************************************/
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static SLOT_INTERFACE_START( miniframe_floppies )
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SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
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SLOT_INTERFACE_END
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static MACHINE_CONFIG_START( miniframe )
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// basic machine hardware
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MCFG_CPU_ADD("maincpu", M68010, XTAL_10MHz)
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MCFG_CPU_PROGRAM_MAP(miniframe_mem)
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// internal ram
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MCFG_RAM_ADD(RAM_TAG)
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MCFG_RAM_DEFAULT_SIZE("1M")
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MCFG_RAM_EXTRA_OPTIONS("2M")
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// RAM/ROM bank
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MCFG_DEVICE_ADD("ramrombank", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(ramrombank_map)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x400000)
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// floppy
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MCFG_DEVICE_ADD("wd2797", WD2797, 1000000)
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// MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(miniframe_state, wd2797_intrq_w))
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// MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(miniframe_state, wd2797_drq_w))
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MCFG_FLOPPY_DRIVE_ADD("wd2797:0", miniframe_floppies, "525dd", floppy_image_device::default_floppy_formats)
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// 8263s
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MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
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MCFG_PIT8253_CLK0(76800)
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MCFG_PIT8253_CLK1(76800)
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MCFG_PIT8253_OUT0_HANDLER(DEVWRITELINE("pic8259", pic8259_device, ir4_w))
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// chain clock 1 output into clock 2
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MCFG_PIT8253_OUT1_HANDLER(DEVWRITELINE("pit8253", pit8253_device, write_clk2))
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// and ir4 on the PIC
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MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("pic8259", pic8259_device, ir4_w))
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MCFG_DEVICE_ADD("baudgen", PIT8253, 0)
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MCFG_PIT8253_CLK0(1228800)
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MCFG_PIT8253_CLK1(1228800)
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MCFG_PIT8253_CLK2(1228800)
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// PIC8259s
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MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
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MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", M68K_IRQ_4))
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MCFG_PIC8259_IN_SP_CB(VCC)
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MACHINE_CONFIG_END
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/***************************************************************************
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ROM DEFINITIONS
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***************************************************************************/
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ROM_START( minifram )
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ROM_REGION16_BE(0x400000, "bootrom", 0)
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ROM_LOAD16_BYTE("72-00357.bin", 0x000001, 0x002000, CRC(17c2749c) SHA1(972b5300b4d6ec65536910eab2b8550b9df9bb4d))
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ROM_LOAD16_BYTE("72-00356.bin", 0x000000, 0x002000, CRC(28b6c23a) SHA1(479e739a8154b6754e2e9b1fcfeb99d6ceaf9dbe))
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ROM_END
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/***************************************************************************
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GAME DRIVERS
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***************************************************************************/
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// YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS
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COMP( 1985, minifram, 0, 0, miniframe, miniframe, miniframe_state, 0, "Convergent", "Miniframe", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
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@ -20834,6 +20834,9 @@ minicom //
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@source:miniforce.cpp
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miniforce // D26 cabinet test board
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@source:miniframe.cpp
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minifram
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@source:minitel_2_rpic.cpp
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minitel2 //
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