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Hooked up PSX IRQ's using DEVCB2 [smf]

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This commit is contained in:
smf- 2012-10-25 16:51:48 +00:00
parent 69a501e040
commit 2fe5db642f
25 changed files with 288 additions and 187 deletions
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9
src/emu/cpu/psx/dma.c
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@ -26,8 +26,9 @@ INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level,
const device_type PSX_DMA = &device_creator<psxdma_device>; const device_type PSX_DMA = &device_creator<psxdma_device>;
psxdma_device::psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) psxdma_device::psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
: device_t(mconfig, PSX_DMA, "PSX DMA", tag, owner, clock) device_t(mconfig, PSX_DMA, "PSX DMA", tag, owner, clock),
m_irq_handler(*this)
{ {
} }
@ -56,6 +57,8 @@ void psxdma_device::device_post_load()
void psxdma_device::device_start() void psxdma_device::device_start()
{ {
m_irq_handler.resolve_safe();
for( int index = 0; index < 7; index++ ) for( int index = 0; index < 7; index++ )
{ {
psx_dma_channel *dma = &channel[ index ]; psx_dma_channel *dma = &channel[ index ];
@ -116,7 +119,7 @@ void psxdma_device::dma_interrupt_update()
{ {
verboselog( machine(), 2, "dma_interrupt_update( %02x, %02x ) interrupt triggered\n", n_int, n_mask ); verboselog( machine(), 2, "dma_interrupt_update( %02x, %02x ) interrupt triggered\n", n_int, n_mask );
n_dicr |= 0x80000000; n_dicr |= 0x80000000;
psx_irq_set( machine(), PSX_IRQ_DMA ); m_irq_handler(1);
} }
else if( n_int != 0 ) else if( n_int != 0 )
{ {

8
src/emu/cpu/psx/dma.h
View File

@ -14,6 +14,9 @@
extern const device_type PSX_DMA; extern const device_type PSX_DMA;
#define MCFG_PSX_DMA_IRQ_HANDLER(_devcb) \
devcb = &psxdma_device::set_irq_handler(*device, DEVCB2_##_devcb);
typedef delegate<void (UINT32, INT32)> psx_dma_read_delegate; typedef delegate<void (UINT32, INT32)> psx_dma_read_delegate;
typedef delegate<void (UINT32, INT32)> psx_dma_write_delegate; typedef delegate<void (UINT32, INT32)> psx_dma_write_delegate;
@ -34,6 +37,9 @@ class psxdma_device : public device_t
public: public:
psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); psxdma_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// static configuration helpers
template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<psxdma_device &>(device).m_irq_handler.set_callback(object); }
void install_read_handler( int n_channel, psx_dma_read_delegate p_fn_dma_read ); void install_read_handler( int n_channel, psx_dma_read_delegate p_fn_dma_read );
void install_write_handler( int n_channel, psx_dma_read_delegate p_fn_dma_write ); void install_write_handler( int n_channel, psx_dma_read_delegate p_fn_dma_write );
@ -58,6 +64,8 @@ private:
psx_dma_channel channel[7]; psx_dma_channel channel[7];
UINT32 n_dpcp; UINT32 n_dpcp;
UINT32 n_dicr; UINT32 n_dicr;
devcb2_write_line m_irq_handler;
}; };
#endif #endif

90
src/emu/cpu/psx/irq.c
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@ -10,6 +10,8 @@
#define VERBOSE_LEVEL ( 0 ) #define VERBOSE_LEVEL ( 0 )
#define PSX_IRQ_MASK ( 0x7fd )
INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level, const char *s_fmt, ... ) INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level, const char *s_fmt, ... )
{ {
if( VERBOSE_LEVEL >= n_level ) if( VERBOSE_LEVEL >= n_level )
@ -110,3 +112,91 @@ READ32_MEMBER( psxirq_device::read )
} }
return 0; return 0;
} }
WRITE_LINE_MEMBER( psxirq_device::intin0 )
{
if( state )
{
set( 1 << 0 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin1 )
{
if( state )
{
set( 1 << 3 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin2 )
{
if( state )
{
set( 1 << 3 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin3 )
{
if( state )
{
set( 1 << 3 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin4 )
{
if( state )
{
set( 1 << 3 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin5 )
{
if( state )
{
set( 1 << 3 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin6 )
{
if( state )
{
set( 1 << 3 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin7 )
{
if( state )
{
set( 1 << 7 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin8 )
{
if( state )
{
set( 1 << 8 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin9 )
{
if( state )
{
set( 1 << 9 );
}
}
WRITE_LINE_MEMBER( psxirq_device::intin10 )
{
if( state )
{
set( 1 << 10 );
}
}

24
src/emu/cpu/psx/irq.h
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@ -12,18 +12,6 @@
#include "emu.h" #include "emu.h"
#define PSX_IRQ_VBLANK 0x0001
#define PSX_IRQ_CDROM 0x0004
#define PSX_IRQ_DMA 0x0008
#define PSX_IRQ_ROOTCOUNTER0 0x0010
#define PSX_IRQ_ROOTCOUNTER1 0x0020
#define PSX_IRQ_ROOTCOUNTER2 0x0040
#define PSX_IRQ_SIO0 0x0080
#define PSX_IRQ_SIO1 0x0100
#define PSX_IRQ_SPU 0x0200
#define PSX_IRQ_EXTCD 0x0400
#define PSX_IRQ_MASK (PSX_IRQ_VBLANK | PSX_IRQ_CDROM | PSX_IRQ_DMA | PSX_IRQ_ROOTCOUNTER2 | PSX_IRQ_ROOTCOUNTER1 | PSX_IRQ_ROOTCOUNTER0 | PSX_IRQ_SIO0 | PSX_IRQ_SIO1 | PSX_IRQ_SPU | PSX_IRQ_EXTCD)
extern const device_type PSX_IRQ; extern const device_type PSX_IRQ;
class psxirq_device : public device_t class psxirq_device : public device_t
@ -34,6 +22,18 @@ public:
DECLARE_READ32_MEMBER( read ); DECLARE_READ32_MEMBER( read );
DECLARE_WRITE32_MEMBER( write ); DECLARE_WRITE32_MEMBER( write );
DECLARE_WRITE_LINE_MEMBER( intin0 );
DECLARE_WRITE_LINE_MEMBER( intin1 );
DECLARE_WRITE_LINE_MEMBER( intin2 );
DECLARE_WRITE_LINE_MEMBER( intin3 );
DECLARE_WRITE_LINE_MEMBER( intin4 );
DECLARE_WRITE_LINE_MEMBER( intin5 );
DECLARE_WRITE_LINE_MEMBER( intin6 );
DECLARE_WRITE_LINE_MEMBER( intin7 );
DECLARE_WRITE_LINE_MEMBER( intin8 );
DECLARE_WRITE_LINE_MEMBER( intin9 );
DECLARE_WRITE_LINE_MEMBER( intin10 );
void set( UINT32 bitmask ); void set( UINT32 bitmask );
protected: protected:

7
src/emu/cpu/psx/psx.c
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@ -3196,13 +3196,20 @@ WRITE32_HANDLER( psxcpu_device::gpu_w )
static MACHINE_CONFIG_FRAGMENT( psx ) static MACHINE_CONFIG_FRAGMENT( psx )
MCFG_DEVICE_ADD("irq", PSX_IRQ, 0) MCFG_DEVICE_ADD("irq", PSX_IRQ, 0)
MCFG_DEVICE_ADD("dma", PSX_DMA, 0) MCFG_DEVICE_ADD("dma", PSX_DMA, 0)
MCFG_PSX_DMA_IRQ_HANDLER(DEVWRITELINE("irq", psxirq_device, intin3))
MCFG_DEVICE_ADD("mdec", PSX_MDEC, 0) MCFG_DEVICE_ADD("mdec", PSX_MDEC, 0)
MCFG_PSX_DMA_CHANNEL_WRITE( DEVICE_SELF, 0, psx_dma_write_delegate( FUNC( psxmdec_device::dma_write ), (psxmdec_device *) device ) ) MCFG_PSX_DMA_CHANNEL_WRITE( DEVICE_SELF, 0, psx_dma_write_delegate( FUNC( psxmdec_device::dma_write ), (psxmdec_device *) device ) )
MCFG_PSX_DMA_CHANNEL_READ( DEVICE_SELF, 1, psx_dma_read_delegate( FUNC( psxmdec_device::dma_read ), (psxmdec_device *) device ) ) MCFG_PSX_DMA_CHANNEL_READ( DEVICE_SELF, 1, psx_dma_read_delegate( FUNC( psxmdec_device::dma_read ), (psxmdec_device *) device ) )
MCFG_DEVICE_ADD("rcnt", PSX_RCNT, 0) MCFG_DEVICE_ADD("rcnt", PSX_RCNT, 0)
MCFG_PSX_RCNT_IRQ0_HANDLER(DEVWRITELINE("irq", psxirq_device, intin4))
MCFG_PSX_RCNT_IRQ1_HANDLER(DEVWRITELINE("irq", psxirq_device, intin5))
MCFG_PSX_RCNT_IRQ2_HANDLER(DEVWRITELINE("irq", psxirq_device, intin6))
MCFG_DEVICE_ADD("sio", PSX_SIO, 0) MCFG_DEVICE_ADD("sio", PSX_SIO, 0)
MCFG_PSX_SIO_IRQ0_HANDLER(DEVWRITELINE("irq", psxirq_device, intin7))
MCFG_PSX_SIO_IRQ1_HANDLER(DEVWRITELINE("irq", psxirq_device, intin8))
MACHINE_CONFIG_END MACHINE_CONFIG_END
//------------------------------------------------- //-------------------------------------------------

24
src/emu/cpu/psx/rcnt.c
View File

@ -25,8 +25,11 @@ INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level,
const device_type PSX_RCNT = &device_creator<psxrcnt_device>; const device_type PSX_RCNT = &device_creator<psxrcnt_device>;
psxrcnt_device::psxrcnt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) psxrcnt_device::psxrcnt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
: device_t(mconfig, PSX_RCNT, "PSX RCNT", tag, owner, clock) device_t(mconfig, PSX_RCNT, "PSX RCNT", tag, owner, clock),
m_irq0_handler(*this),
m_irq1_handler(*this),
m_irq2_handler(*this)
{ {
} }
@ -47,6 +50,10 @@ void psxrcnt_device::device_start()
{ {
int n; int n;
m_irq0_handler.resolve_safe();
m_irq1_handler.resolve_safe();
m_irq2_handler.resolve_safe();
for( n = 0; n < 3; n++ ) for( n = 0; n < 3; n++ )
{ {
root_counter[ n ].timer = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( psxrcnt_device::root_finished ), this ) ); root_counter[ n ].timer = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( psxrcnt_device::root_finished ), this ) );
@ -232,6 +239,17 @@ TIMER_CALLBACK_MEMBER(psxrcnt_device::root_finished)
if( ( root->n_mode & PSX_RC_IRQOVERFLOW ) != 0 || if( ( root->n_mode & PSX_RC_IRQOVERFLOW ) != 0 ||
( root->n_mode & PSX_RC_IRQTARGET ) != 0 ) ( root->n_mode & PSX_RC_IRQTARGET ) != 0 )
{ {
psx_irq_set( machine(), PSX_IRQ_ROOTCOUNTER0 << n_counter ); switch( n_counter )
{
case 0:
m_irq0_handler(1);
break;
case 1:
m_irq1_handler(1);
break;
case 2:
m_irq2_handler(1);
break;
}
} }
} }

18
src/emu/cpu/psx/rcnt.h
View File

@ -14,6 +14,15 @@
extern const device_type PSX_RCNT; extern const device_type PSX_RCNT;
#define MCFG_PSX_RCNT_IRQ0_HANDLER(_devcb) \
devcb = &psxrcnt_device::set_irq0_handler(*device, DEVCB2_##_devcb); \
#define MCFG_PSX_RCNT_IRQ1_HANDLER(_devcb) \
devcb = &psxrcnt_device::set_irq1_handler(*device, DEVCB2_##_devcb); \
#define MCFG_PSX_RCNT_IRQ2_HANDLER(_devcb) \
devcb = &psxrcnt_device::set_irq2_handler(*device, DEVCB2_##_devcb); \
#define PSX_RC_STOP ( 0x01 ) #define PSX_RC_STOP ( 0x01 )
#define PSX_RC_RESET ( 0x04 ) /* guess */ #define PSX_RC_RESET ( 0x04 ) /* guess */
#define PSX_RC_COUNTTARGET ( 0x08 ) #define PSX_RC_COUNTTARGET ( 0x08 )
@ -37,6 +46,11 @@ class psxrcnt_device : public device_t
public: public:
psxrcnt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); psxrcnt_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// static configuration helpers
template<class _Object> static devcb2_base &set_irq0_handler(device_t &device, _Object object) { return downcast<psxrcnt_device &>(device).m_irq0_handler.set_callback(object); }
template<class _Object> static devcb2_base &set_irq1_handler(device_t &device, _Object object) { return downcast<psxrcnt_device &>(device).m_irq1_handler.set_callback(object); }
template<class _Object> static devcb2_base &set_irq2_handler(device_t &device, _Object object) { return downcast<psxrcnt_device &>(device).m_irq2_handler.set_callback(object); }
DECLARE_WRITE32_MEMBER( write ); DECLARE_WRITE32_MEMBER( write );
DECLARE_READ32_MEMBER( read ); DECLARE_READ32_MEMBER( read );
@ -54,6 +68,10 @@ private:
int root_target( int n_counter ); int root_target( int n_counter );
void root_timer_adjust( int n_counter ); void root_timer_adjust( int n_counter );
TIMER_CALLBACK_MEMBER(root_finished); TIMER_CALLBACK_MEMBER(root_finished);
devcb2_write_line m_irq0_handler;
devcb2_write_line m_irq1_handler;
devcb2_write_line m_irq2_handler;
}; };
#endif #endif

13
src/emu/cpu/psx/sio.c
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@ -25,8 +25,10 @@ INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level,
const device_type PSX_SIO = &device_creator<psxsio_device>; const device_type PSX_SIO = &device_creator<psxsio_device>;
psxsio_device::psxsio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) psxsio_device::psxsio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
: device_t(mconfig, PSX_SIO, "PSX SIO", tag, owner, clock) device_t(mconfig, PSX_SIO, "PSX SIO", tag, owner, clock),
m_irq0_handler(*this),
m_irq1_handler(*this)
{ {
int n; int n;
@ -54,6 +56,9 @@ void psxsio_device::device_start()
{ {
int n; int n;
m_irq0_handler.resolve_safe();
m_irq1_handler.resolve_safe();
for( n = 0; n < 2; n++ ) for( n = 0; n < 2; n++ )
{ {
port[ n ].timer = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( psxsio_device::sio_clock ), this ) ); port[ n ].timer = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( psxsio_device::sio_clock ), this ) );
@ -105,11 +110,11 @@ void psxsio_device::sio_interrupt( int n_port )
sio->n_status |= SIO_STATUS_IRQ; sio->n_status |= SIO_STATUS_IRQ;
if( n_port == 0 ) if( n_port == 0 )
{ {
psx_irq_set( machine(), PSX_IRQ_SIO0 ); m_irq0_handler(1);
} }
else else
{ {
psx_irq_set( machine(), PSX_IRQ_SIO1 ); m_irq1_handler(1);
} }
} }

13
src/emu/cpu/psx/sio.h
View File

@ -16,6 +16,12 @@ extern const device_type PSX_SIO;
typedef void ( *psx_sio_handler )( running_machine &, int ); typedef void ( *psx_sio_handler )( running_machine &, int );
#define MCFG_PSX_SIO_IRQ0_HANDLER(_devcb) \
devcb = &psxsio_device::set_irq0_handler(*device, DEVCB2_##_devcb); \
#define MCFG_PSX_SIO_IRQ1_HANDLER(_devcb) \
devcb = &psxsio_device::set_irq1_handler(*device, DEVCB2_##_devcb); \
#define PSX_SIO_OUT_DATA ( 1 ) /* COMMAND */ #define PSX_SIO_OUT_DATA ( 1 ) /* COMMAND */
#define PSX_SIO_OUT_DTR ( 2 ) /* ATT */ #define PSX_SIO_OUT_DTR ( 2 ) /* ATT */
#define PSX_SIO_OUT_RTS ( 4 ) #define PSX_SIO_OUT_RTS ( 4 )
@ -67,6 +73,10 @@ class psxsio_device : public device_t
public: public:
psxsio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); psxsio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// static configuration helpers
template<class _Object> static devcb2_base &set_irq0_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_irq0_handler.set_callback(object); }
template<class _Object> static devcb2_base &set_irq1_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_irq1_handler.set_callback(object); }
void install_handler( int n_port, psx_sio_handler p_f_sio_handler ); void install_handler( int n_port, psx_sio_handler p_f_sio_handler );
DECLARE_WRITE32_MEMBER( write ); DECLARE_WRITE32_MEMBER( write );
@ -85,6 +95,9 @@ private:
TIMER_CALLBACK_MEMBER(sio_clock); TIMER_CALLBACK_MEMBER(sio_clock);
psx_sio port[2]; psx_sio port[2];
devcb2_write_line m_irq0_handler;
devcb2_write_line m_irq1_handler;
}; };
DECLARE_WRITE32_HANDLER( psx_sio_w ); DECLARE_WRITE32_HANDLER( psx_sio_w );

19
src/emu/machine/am53cf96.c
View File

@ -50,7 +50,7 @@ void am53cf96_device::device_timer(emu_timer &timer, device_timer_id tid, int pa
{ {
scsi_regs[REG_IRQSTATE] = 8; // indicate success scsi_regs[REG_IRQSTATE] = 8; // indicate success
scsi_regs[REG_STATUS] |= 0x80; // indicate IRQ scsi_regs[REG_STATUS] |= 0x80; // indicate IRQ
irq_callback(machine()); m_irq_handler(1);
} }
WRITE8_MEMBER( am53cf96_device::write ) WRITE8_MEMBER( am53cf96_device::write )
@ -157,23 +157,16 @@ WRITE8_MEMBER( am53cf96_device::write )
} }
} }
am53cf96_device::am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) am53cf96_device::am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
: device_t(mconfig, AM53CF96, "53CF96 SCSI", tag, owner, clock) device_t(mconfig, AM53CF96, "53CF96 SCSI", tag, owner, clock),
m_irq_handler(*this)
{ {
} }
void am53cf96_device::device_config_complete()
{
// inherit a copy of the static data
const AM53CF96interface *intf = reinterpret_cast<const AM53CF96interface *>(static_config());
if (intf != NULL)
{
*static_cast<AM53CF96interface *>(this) = *intf;
}
}
void am53cf96_device::device_start() void am53cf96_device::device_start()
{ {
m_irq_handler.resolve_safe();
memset(scsi_regs, 0, sizeof(scsi_regs)); memset(scsi_regs, 0, sizeof(scsi_regs));
memset(devices, 0, sizeof(devices)); memset(devices, 0, sizeof(devices));

19
src/emu/machine/am53cf96.h
View File

@ -8,14 +8,11 @@
#include "machine/scsihle.h" #include "machine/scsihle.h"
struct AM53CF96interface #define MCFG_AM53CF96_ADD( _tag ) \
{ MCFG_DEVICE_ADD( _tag, AM53CF96, 0 )
void (*irq_callback)(running_machine &machine); /* irq callback */
};
#define MCFG_AM53CF96_ADD( _tag, _config ) \ #define MCFG_AM53CF96_IRQ_HANDLER(_devcb) \
MCFG_DEVICE_ADD( _tag, AM53CF96, 0 ) \ devcb = &am53cf96_device::set_irq_handler(*device, DEVCB2_##_devcb); \
MCFG_DEVICE_CONFIG(_config)
// 53CF96 register set // 53CF96 register set
enum enum
@ -39,13 +36,15 @@ enum
REG_DATAALIGN // data alignment (write only) REG_DATAALIGN // data alignment (write only)
}; };
class am53cf96_device : public device_t, class am53cf96_device : public device_t
public AM53CF96interface
{ {
public: public:
// construction/destruction // construction/destruction
am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// static configuration helpers
template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<am53cf96_device &>(device).m_irq_handler.set_callback(object); }
DECLARE_READ8_MEMBER(read); DECLARE_READ8_MEMBER(read);
DECLARE_WRITE8_MEMBER(write); DECLARE_WRITE8_MEMBER(write);
@ -54,7 +53,6 @@ public:
protected: protected:
// device-level overrides // device-level overrides
virtual void device_config_complete();
virtual void device_start(); virtual void device_start();
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr); virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
@ -70,6 +68,7 @@ private:
UINT8 last_id; UINT8 last_id;
emu_timer* m_transfer_timer; emu_timer* m_transfer_timer;
devcb2_write_line m_irq_handler;
}; };
// device type definition // device type definition

19
src/emu/sound/spu.c
View File

@ -954,16 +954,15 @@ static int shift_register15(int &shift)
// spu_device - constructor // spu_device - constructor
//------------------------------------------------- //-------------------------------------------------
spu_device::spu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) spu_device::spu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
: device_t(mconfig, SPU, "SPU", tag, owner, clock), device_t(mconfig, SPU, "SPU", tag, owner, clock),
device_sound_interface(mconfig, *this), device_sound_interface(mconfig, *this),
m_irq_cb(NULL), m_irq_handler(*this),
dirty_flags(-1), dirty_flags(-1),
status_enabled(false), status_enabled(false),
xa_voll(0x8000), xa_voll(0x8000),
xa_volr(0x8000), xa_volr(0x8000),
changed_xa_vol(0) changed_xa_vol(0)
{ {
} }
@ -972,14 +971,10 @@ spu_device::spu_device(const machine_config &mconfig, const char *tag, device_t
// the IRQ callback // the IRQ callback
//------------------------------------------------- //-------------------------------------------------
void spu_device::static_set_irqf(device_t &device, void (*irqf)(device_t *device, UINT32 state))
{
spu_device &spu = downcast<spu_device &>(device);
spu.m_irq_cb = irqf;
}
void spu_device::device_start() void spu_device::device_start()
{ {
m_irq_handler.resolve_safe();
voice=new voiceinfo [24]; voice=new voiceinfo [24];
spu_ram=new unsigned char [spu_ram_size]; spu_ram=new unsigned char [spu_ram_size];
@ -1858,7 +1853,7 @@ bool spu_device::process_voice(const unsigned int v,
if (hitirq) if (hitirq)
{ {
// Went past IRQ address, trigger IRQ // Went past IRQ address, trigger IRQ
m_irq_cb(this, 1); m_irq_handler(1);
vi->samplestoirq=spu_infinity; vi->samplestoirq=spu_infinity;
vi->hitirq=true; vi->hitirq=true;
@ -2656,7 +2651,7 @@ void spu_device::update_irq_event()
{ {
if (voice[i].samplestoirq==0) if (voice[i].samplestoirq==0)
{ {
m_irq_cb(this, 1); m_irq_handler(1);
voice[i].samplestoirq=spu_infinity; voice[i].samplestoirq=spu_infinity;
voice[i].hitirq=true; voice[i].hitirq=true;

20
src/emu/sound/spu.h
View File

@ -9,14 +9,14 @@
// INTERFACE CONFIGURATION MACROS // INTERFACE CONFIGURATION MACROS
//************************************************************************** //**************************************************************************
#define MCFG_SPU_ADD(_tag, _clock, _irqf) \ #define MCFG_SPU_IRQ_HANDLER(_devcb) \
MCFG_DEVICE_ADD(_tag, SPU, _clock) \ devcb = &spu_device::set_irq_handler(*device, DEVCB2_##_devcb);
MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 4, psx_dma_read_delegate( FUNC( spu_device::dma_read ), (spu_device *) device ) ) \
MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 4, psx_dma_write_delegate( FUNC( spu_device::dma_write ), (spu_device *) device ) ) \
MCFG_IRQ_FUNC(_irqf)
#define MCFG_IRQ_FUNC(_irqf) \ #define MCFG_SPU_ADD(_tag, _clock) \
spu_device::static_set_irqf(*device, _irqf); \ MCFG_DEVICE_ADD(_tag, SPU, _clock) \
MCFG_SPU_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin9)) \
MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 4, psx_dma_read_delegate( FUNC( spu_device::dma_read ), (spu_device *) device ) ) \
MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 4, psx_dma_write_delegate( FUNC( spu_device::dma_write ), (spu_device *) device ) )
// ======================> spu_device // ======================> spu_device
@ -49,7 +49,7 @@ protected:
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples); virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
// internal state // internal state
void (*m_irq_cb)(device_t *device, UINT32 state); devcb2_write_line m_irq_handler;
unsigned char *spu_ram; unsigned char *spu_ram;
reverb *rev; reverb *rev;
@ -217,8 +217,8 @@ protected:
public: public:
spu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); spu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// inline configuration helpers // static configuration helpers
static void static_set_irqf(device_t &device, void (*irqf)(device_t *device, UINT32 state)); template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<spu_device &>(device).m_irq_handler.set_callback(object); }
void dma_read( UINT32 n_address, INT32 n_size ); void dma_read( UINT32 n_address, INT32 n_size );
void dma_write( UINT32 n_address, INT32 n_size ); void dma_write( UINT32 n_address, INT32 n_size );

9
src/emu/video/psx.c
View File

@ -19,13 +19,16 @@ const device_type CXD8561BQ = &device_creator<cxd8561bq_device>;
const device_type CXD8561CQ = &device_creator<cxd8561cq_device>; const device_type CXD8561CQ = &device_creator<cxd8561cq_device>;
const device_type CXD8654Q = &device_creator<cxd8654q_device>; const device_type CXD8654Q = &device_creator<cxd8654q_device>;
psxgpu_device::psxgpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) psxgpu_device::psxgpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
: device_t(mconfig, type, name, tag, owner, clock) device_t(mconfig, type, name, tag, owner, clock),
m_vblank_handler(*this)
{ {
} }
void psxgpu_device::device_start( void ) void psxgpu_device::device_start( void )
{ {
m_vblank_handler.resolve_safe();
if( m_type == CXD8538Q ) if( m_type == CXD8538Q )
{ {
psx_gpu_init( 1 ); psx_gpu_init( 1 );
@ -3661,7 +3664,7 @@ void psxgpu_device::vblank(screen_device &screen, bool vblank_state)
#endif #endif
n_gpustatus ^= ( 1L << 31 ); n_gpustatus ^= ( 1L << 31 );
psx_irq_set( machine(), 0x0001 ); m_vblank_handler(1);
} }
} }

10
src/emu/video/psx.h
View File

@ -12,12 +12,16 @@
#include "emu.h" #include "emu.h"
#define MCFG_PSX_GPU_VBLANK_HANDLER(_devcb) \
devcb = &psxgpu_device::set_vblank_handler(*device, DEVCB2_##_devcb);
#define MCFG_PSXGPU_ADD( cputag, tag, type, _vramSize, clock ) \ #define MCFG_PSXGPU_ADD( cputag, tag, type, _vramSize, clock ) \
MCFG_DEVICE_MODIFY( cputag ) \ MCFG_DEVICE_MODIFY( cputag ) \
MCFG_PSX_GPU_READ_HANDLER(DEVREAD32(tag, psxgpu_device, read)) \ MCFG_PSX_GPU_READ_HANDLER(DEVREAD32(tag, psxgpu_device, read)) \
MCFG_PSX_GPU_WRITE_HANDLER(DEVWRITE32(tag, psxgpu_device, write)) \ MCFG_PSX_GPU_WRITE_HANDLER(DEVWRITE32(tag, psxgpu_device, write)) \
MCFG_DEVICE_ADD( tag, type, clock ) \ MCFG_DEVICE_ADD( tag, type, clock ) \
((psxgpu_device *) device)->vramSize = _vramSize; \ ((psxgpu_device *) device)->vramSize = _vramSize; \
MCFG_PSX_GPU_VBLANK_HANDLER(DEVWRITELINE(cputag ":irq", psxirq_device, intin0)) \
MCFG_PSX_DMA_CHANNEL_READ( cputag, 2, psx_dma_write_delegate( FUNC( psxgpu_device::dma_read ), (psxgpu_device *) device ) ) \ MCFG_PSX_DMA_CHANNEL_READ( cputag, 2, psx_dma_write_delegate( FUNC( psxgpu_device::dma_read ), (psxgpu_device *) device ) ) \
MCFG_PSX_DMA_CHANNEL_WRITE( cputag, 2, psx_dma_read_delegate( FUNC( psxgpu_device::dma_write ), (psxgpu_device *) device ) ) MCFG_PSX_DMA_CHANNEL_WRITE( cputag, 2, psx_dma_read_delegate( FUNC( psxgpu_device::dma_write ), (psxgpu_device *) device ) )
@ -27,6 +31,7 @@
MCFG_PSX_GPU_WRITE_HANDLER(DEVWRITE32(tag, psxgpu_device, write)) \ MCFG_PSX_GPU_WRITE_HANDLER(DEVWRITE32(tag, psxgpu_device, write)) \
MCFG_DEVICE_REPLACE( tag, type, clock ) \ MCFG_DEVICE_REPLACE( tag, type, clock ) \
((psxgpu_device *) device)->vramSize = _vramSize; \ ((psxgpu_device *) device)->vramSize = _vramSize; \
MCFG_PSX_GPU_VBLANK_HANDLER(DEVWRITELINE(cputag ":irq", psxirq_device, intin0)) \
MCFG_PSX_DMA_CHANNEL_READ( cputag, 2, psx_dma_write_delegate( FUNC( psxgpu_device::dma_read ), (psxgpu_device *) device ) ) \ MCFG_PSX_DMA_CHANNEL_READ( cputag, 2, psx_dma_write_delegate( FUNC( psxgpu_device::dma_read ), (psxgpu_device *) device ) ) \
MCFG_PSX_DMA_CHANNEL_WRITE( cputag, 2, psx_dma_read_delegate( FUNC( psxgpu_device::dma_write ), (psxgpu_device *) device ) ) MCFG_PSX_DMA_CHANNEL_WRITE( cputag, 2, psx_dma_read_delegate( FUNC( psxgpu_device::dma_write ), (psxgpu_device *) device ) )
@ -186,6 +191,9 @@ public:
psxgpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock); psxgpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
virtual machine_config_constructor device_mconfig_additions() const; virtual machine_config_constructor device_mconfig_additions() const;
// static configuration helpers
template<class _Object> static devcb2_base &set_vblank_handler(device_t &device, _Object object) { return downcast<psxgpu_device &>(device).m_vblank_handler.set_callback(object); }
UINT32 update_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 update_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
DECLARE_WRITE32_MEMBER( write ); DECLARE_WRITE32_MEMBER( write );
DECLARE_READ32_MEMBER( read ); DECLARE_READ32_MEMBER( read );
@ -300,6 +308,8 @@ protected:
UINT16 p_n_b0[ 0x10000 ]; UINT16 p_n_b0[ 0x10000 ];
UINT16 p_n_r1[ 0x10000 ]; UINT16 p_n_r1[ 0x10000 ];
UINT16 p_n_b1g1[ 0x10000 ]; UINT16 p_n_b1g1[ 0x10000 ];
devcb2_write_line m_vblank_handler;
}; };
class cxd8514q_device : public psxgpu_device class cxd8514q_device : public psxgpu_device

15
src/mame/drivers/konamigq.c
View File

@ -303,19 +303,8 @@ static void scsi_dma_write( konamigq_state *state, UINT32 n_address, INT32 n_siz
{ {
} }
static void scsi_irq(running_machine &machine)
{
psx_irq_set(machine, 0x400);
}
static const struct AM53CF96interface am53cf96_intf =
{
&scsi_irq, /* command completion IRQ */
};
DRIVER_INIT_MEMBER(konamigq_state,konamigq) DRIVER_INIT_MEMBER(konamigq_state,konamigq)
{ {
psx_driver_init(machine()); psx_driver_init(machine());
m_p_n_pcmram = memregion( "shared" )->base() + 0x80000; m_p_n_pcmram = memregion( "shared" )->base() + 0x80000;
@ -323,7 +312,6 @@ DRIVER_INIT_MEMBER(konamigq_state,konamigq)
MACHINE_START_MEMBER(konamigq_state,konamigq) MACHINE_START_MEMBER(konamigq_state,konamigq)
{ {
save_pointer(NAME(m_p_n_pcmram), 0x380000); save_pointer(NAME(m_p_n_pcmram), 0x380000);
save_item(NAME(m_sndto000)); save_item(NAME(m_sndto000));
save_item(NAME(m_sndtor3k)); save_item(NAME(m_sndtor3k));
@ -353,7 +341,8 @@ static MACHINE_CONFIG_START( konamigq, konamigq_state )
MCFG_SCSIBUS_ADD("scsi") MCFG_SCSIBUS_ADD("scsi")
MCFG_SCSIDEV_ADD("scsi:disk", SCSIHD, SCSI_ID_0) MCFG_SCSIDEV_ADD("scsi:disk", SCSIHD, SCSI_ID_0)
MCFG_AM53CF96_ADD("scsi:am53cf96", am53cf96_intf) MCFG_AM53CF96_ADD("scsi:am53cf96")
MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
/* video hardware */ /* video hardware */
MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8538Q, 0x200000, XTAL_53_693175MHz ) MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8538Q, 0x200000, XTAL_53_693175MHz )

24
src/mame/drivers/konamigv.c
View File

@ -292,16 +292,6 @@ static void scsi_dma_write( konamigv_state *state, UINT32 n_address, INT32 n_siz
} }
} }
static void scsi_irq(running_machine &machine)
{
psx_irq_set(machine, 0x400);
}
static const struct AM53CF96interface am53cf96_intf =
{
&scsi_irq, /* command completion IRQ */
};
DRIVER_INIT_MEMBER(konamigv_state,konamigv) DRIVER_INIT_MEMBER(konamigv_state,konamigv)
{ {
psx_driver_init(machine()); psx_driver_init(machine());
@ -309,7 +299,6 @@ DRIVER_INIT_MEMBER(konamigv_state,konamigv)
MACHINE_START_MEMBER(konamigv_state,konamigv) MACHINE_START_MEMBER(konamigv_state,konamigv)
{ {
save_item(NAME(m_sector_buffer)); save_item(NAME(m_sector_buffer));
save_item(NAME(m_flash_address)); save_item(NAME(m_flash_address));
save_item(NAME(m_trackball_prev)); save_item(NAME(m_trackball_prev));
@ -318,14 +307,6 @@ MACHINE_START_MEMBER(konamigv_state,konamigv)
save_item(NAME(m_btc_trackball_data)); save_item(NAME(m_btc_trackball_data));
} }
static void spu_irq(device_t *device, UINT32 data)
{
if (data)
{
psx_irq_set(device->machine(), 1<<9);
}
}
static MACHINE_CONFIG_START( konamigv, konamigv_state ) static MACHINE_CONFIG_START( konamigv, konamigv_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD( "maincpu", CXD8530BQ, XTAL_67_7376MHz ) MCFG_CPU_ADD( "maincpu", CXD8530BQ, XTAL_67_7376MHz )
@ -340,7 +321,8 @@ static MACHINE_CONFIG_START( konamigv, konamigv_state )
MCFG_SCSIBUS_ADD("scsi") MCFG_SCSIBUS_ADD("scsi")
MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_4) MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_4)
MCFG_AM53CF96_ADD("scsi:am53cf96", am53cf96_intf) MCFG_AM53CF96_ADD("scsi:am53cf96")
MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
/* video hardware */ /* video hardware */
MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8514Q, 0x100000, XTAL_53_693175MHz ) MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8514Q, 0x100000, XTAL_53_693175MHz )
@ -348,7 +330,7 @@ static MACHINE_CONFIG_START( konamigv, konamigv_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE( 0, "lspeaker", 0.75 ) MCFG_SOUND_ROUTE( 0, "lspeaker", 0.75 )
MCFG_SOUND_ROUTE( 1, "rspeaker", 0.75 ) MCFG_SOUND_ROUTE( 1, "rspeaker", 0.75 )

35
src/mame/drivers/ksys573.c
View File

@ -479,9 +479,14 @@ G: gun mania only, drives air soft gun (this game uses real BB bullet)
class ksys573_state : public psx_state class ksys573_state : public psx_state
{ {
public: public:
ksys573_state(const machine_config &mconfig, device_type type, const char *tag) ksys573_state(const machine_config &mconfig, device_type type, const char *tag) :
: psx_state(mconfig, type, tag), psx_state(mconfig, type, tag),
m_cr589(*this, ":cdrom") { } m_psxirq(*this, ":maincpu:irq"),
m_cr589(*this, ":cdrom")
{
}
required_device<psxirq_device> m_psxirq;
int m_flash_bank; int m_flash_bank;
fujitsu_29f016a_device *m_flash_device[5][16]; fujitsu_29f016a_device *m_flash_device[5][16];
@ -758,7 +763,7 @@ TIMER_CALLBACK_MEMBER(ksys573_state::atapi_xfer_end)
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO | ATAPI_INTREASON_COMMAND; atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO | ATAPI_INTREASON_COMMAND;
} }
psx_irq_set(machine(), 0x400); m_psxirq->intin10(1);
verboselog( machine(), 2, "atapi_xfer_end: %d %d\n", m_atapi_xferlen, m_atapi_xfermod ); verboselog( machine(), 2, "atapi_xfer_end: %d %d\n", m_atapi_xferlen, m_atapi_xfermod );
} }
@ -809,7 +814,7 @@ READ32_MEMBER(ksys573_state::atapi_r)
atapi_regs[ATAPI_REG_COUNTLOW] = m_atapi_xferlen & 0xff; atapi_regs[ATAPI_REG_COUNTLOW] = m_atapi_xferlen & 0xff;
atapi_regs[ATAPI_REG_COUNTHIGH] = (m_atapi_xferlen>>8)&0xff; atapi_regs[ATAPI_REG_COUNTHIGH] = (m_atapi_xferlen>>8)&0xff;
psx_irq_set(machine(), 0x400); m_psxirq->intin10(1);
} }
if( m_atapi_data_ptr < m_atapi_data_len ) if( m_atapi_data_ptr < m_atapi_data_len )
@ -826,7 +831,7 @@ READ32_MEMBER(ksys573_state::atapi_r)
{ {
atapi_regs[ATAPI_REG_CMDSTATUS] = 0; atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO; atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
psx_irq_set(machine(), 0x400); m_psxirq->intin10(1);
} }
} }
} }
@ -910,7 +915,7 @@ WRITE32_MEMBER(ksys573_state::atapi_w)
m_cr589->WriteData( atapi_data, m_atapi_cdata_wait ); m_cr589->WriteData( atapi_data, m_atapi_cdata_wait );
// assert IRQ // assert IRQ
psx_irq_set(machine(), 0x400); m_psxirq->intin10(1);
// not sure here, but clear DRQ at least? // not sure here, but clear DRQ at least?
atapi_regs[ATAPI_REG_CMDSTATUS] = 0; atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
@ -983,7 +988,7 @@ WRITE32_MEMBER(ksys573_state::atapi_w)
} }
// assert IRQ // assert IRQ
psx_irq_set(machine(), 0x400); m_psxirq->intin10(1);
} }
else else
{ {
@ -1100,7 +1105,7 @@ WRITE32_MEMBER(ksys573_state::atapi_w)
atapi_regs[ATAPI_REG_COUNTLOW] = 0; atapi_regs[ATAPI_REG_COUNTLOW] = 0;
atapi_regs[ATAPI_REG_COUNTHIGH] = 2; atapi_regs[ATAPI_REG_COUNTHIGH] = 2;
psx_irq_set(machine(), 0x400); m_psxirq->intin10(1);
break; break;
case 0xef: // SET FEATURES case 0xef: // SET FEATURES
@ -1109,7 +1114,7 @@ WRITE32_MEMBER(ksys573_state::atapi_w)
m_atapi_data_ptr = 0; m_atapi_data_ptr = 0;
m_atapi_data_len = 0; m_atapi_data_len = 0;
psx_irq_set(machine(), 0x400); m_psxirq->intin10(1);
break; break;
default: default:
@ -1408,14 +1413,6 @@ MACHINE_RESET_MEMBER(ksys573_state,konami573)
update_mode(machine()); update_mode(machine());
} }
static void spu_irq(device_t *device, UINT32 data)
{
if (data)
{
psx_irq_set(device->machine(), 1<<9);
}
}
void sys573_vblank(ksys573_state *state, screen_device &screen, bool vblank_state) void sys573_vblank(ksys573_state *state, screen_device &screen, bool vblank_state)
{ {
UINT32 *p_n_psxram = state->m_p_n_psxram; UINT32 *p_n_psxram = state->m_p_n_psxram;
@ -3061,7 +3058,7 @@ static MACHINE_CONFIG_START( konami573, ksys573_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE( 0, "lspeaker", 1.0 ) MCFG_SOUND_ROUTE( 0, "lspeaker", 1.0 )
MCFG_SOUND_ROUTE( 1, "rspeaker", 1.0 ) MCFG_SOUND_ROUTE( 1, "rspeaker", 1.0 )

10
src/mame/drivers/taitogn.c
View File

@ -930,14 +930,6 @@ static ADDRESS_MAP_START( taitogn_map, AS_PROGRAM, 32, taitogn_state )
ADDRESS_MAP_END ADDRESS_MAP_END
static void spu_irq(device_t *device, UINT32 data)
{
if (data)
{
psx_irq_set(device->machine(), 1<<9);
}
}
static const ide_config ide_intf = static const ide_config ide_intf =
{ {
NULL, NULL,
@ -956,7 +948,7 @@ static MACHINE_CONFIG_START( coh3002t, taitogn_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE(0, "lspeaker", 0.35) MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
MCFG_SOUND_ROUTE(1, "rspeaker", 0.35) MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)

23
src/mame/drivers/twinkle.c
View File

@ -849,16 +849,6 @@ static void scsi_dma_write( twinkle_state *state, UINT32 n_address, INT32 n_size
} }
} }
static void scsi_irq(running_machine &machine)
{
psx_irq_set(machine, 0x400);
}
static const struct AM53CF96interface am53cf96_intf =
{
&scsi_irq, /* command completion IRQ */
};
DRIVER_INIT_MEMBER(twinkle_state,twinkle) DRIVER_INIT_MEMBER(twinkle_state,twinkle)
{ {
psx_driver_init(machine()); psx_driver_init(machine());
@ -870,14 +860,6 @@ DRIVER_INIT_MEMBER(twinkle_state,twinkle)
i2cmem_wc_write( i2cmem, 0 ); i2cmem_wc_write( i2cmem, 0 );
} }
static void spu_irq(device_t *device, UINT32 data)
{
if (data)
{
psx_irq_set(device->machine(), 1<<9);
}
}
static const i2cmem_interface i2cmem_interface = static const i2cmem_interface i2cmem_interface =
{ {
I2CMEM_SLAVE_ADDRESS, 0, 0x100 I2CMEM_SLAVE_ADDRESS, 0, 0x100
@ -912,7 +894,8 @@ static MACHINE_CONFIG_START( twinkle, twinkle_state )
MCFG_SCSIBUS_ADD("scsi") MCFG_SCSIBUS_ADD("scsi")
MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_4) MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_4)
MCFG_AM53CF96_ADD("scsi:am53cf96", am53cf96_intf) MCFG_AM53CF96_ADD("scsi:am53cf96")
MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true) MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
MCFG_RTC65271_ADD("rtc", twinkle_rtc) MCFG_RTC65271_ADD("rtc", twinkle_rtc)
@ -923,7 +906,7 @@ static MACHINE_CONFIG_START( twinkle, twinkle_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("speakerleft", "speakerright") MCFG_SPEAKER_STANDARD_STEREO("speakerleft", "speakerright")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE( 0, "speakerleft", 0.75 ) MCFG_SOUND_ROUTE( 0, "speakerleft", 0.75 )
MCFG_SOUND_ROUTE( 1, "speakerright", 0.75 ) MCFG_SOUND_ROUTE( 1, "speakerright", 0.75 )

19
src/mame/drivers/zn.c
View File

@ -538,14 +538,6 @@ static void zn_driver_init( running_machine &machine )
state->m_dip_timer = machine.scheduler().timer_alloc( timer_expired_delegate(FUNC(zn_state::dip_timer_fired),state), NULL ); state->m_dip_timer = machine.scheduler().timer_alloc( timer_expired_delegate(FUNC(zn_state::dip_timer_fired),state), NULL );
} }
static void psx_spu_irq(device_t *device, UINT32 data)
{
if (data)
{
psx_irq_set(device->machine(), 1<<9);
}
}
static void zn_machine_init( running_machine &machine ) static void zn_machine_init( running_machine &machine )
{ {
zn_state *state = machine.driver_data<zn_state>(); zn_state *state = machine.driver_data<zn_state>();
@ -565,7 +557,7 @@ static MACHINE_CONFIG_START( zn1_1mb_vram, zn_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &psx_spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE(0, "lspeaker", 0.35) MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
MCFG_SOUND_ROUTE(1, "rspeaker", 0.35) MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)
@ -587,7 +579,7 @@ static MACHINE_CONFIG_START( zn2, zn_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &psx_spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE(0, "lspeaker", 0.35) MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
MCFG_SOUND_ROUTE(1, "rspeaker", 0.35) MCFG_SOUND_ROUTE(1, "rspeaker", 0.35)
@ -1479,6 +1471,13 @@ Notes:
*2 - Unpopulated DIP28 socket *2 - Unpopulated DIP28 socket
*/ */
/* IRQ */
void psx_irq_set( running_machine &machine, UINT32 data )
{
psxcpu_device::irq_set( *machine.device("maincpu^"), "maincpu", data );
}
static void atpsx_interrupt(device_t *device, int state) static void atpsx_interrupt(device_t *device, int state)
{ {
if (state) if (state)

7
src/mame/machine/psx.c
View File

@ -49,13 +49,6 @@ READ32_HANDLER( psx_com_delay_r )
return p_psx->n_com_delay; return p_psx->n_com_delay;
} }
/* IRQ */
void psx_irq_set( running_machine &machine, UINT32 data )
{
psxcpu_device::irq_set( *machine.device("maincpu^"), "maincpu", data );
}
/* SIO */ /* SIO */
void psx_sio_install_handler( running_machine &machine, int n_port, psx_sio_handler p_f_sio_handler ) void psx_sio_install_handler( running_machine &machine, int n_port, psx_sio_handler p_f_sio_handler )

14
src/mess/drivers/psx.c
View File

@ -754,14 +754,6 @@ static INPUT_PORTS_START( psx )
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON8 ) PORT_PLAYER(2) PORT_NAME("P2 L2") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON8 ) PORT_PLAYER(2) PORT_NAME("P2 L2")
INPUT_PORTS_END INPUT_PORTS_END
static void spu_irq(device_t *device, UINT32 data)
{
if (data)
{
psx_irq_set(device->machine(), 1<<9);
}
}
struct cdrom_interface psx_cdrom = struct cdrom_interface psx_cdrom =
{ {
"psx_cdrom", "psx_cdrom",
@ -780,7 +772,7 @@ static MACHINE_CONFIG_START( psxntsc, psx1_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE( 0, "lspeaker", 1.00 ) MCFG_SOUND_ROUTE( 0, "lspeaker", 1.00 )
MCFG_SOUND_ROUTE( 1, "rspeaker", 1.00 ) MCFG_SOUND_ROUTE( 1, "rspeaker", 1.00 )
@ -791,6 +783,7 @@ static MACHINE_CONFIG_START( psxntsc, psx1_state )
MCFG_SOFTWARE_LIST_ADD("cd_list","psx") MCFG_SOFTWARE_LIST_ADD("cd_list","psx")
MCFG_PSXCD_ADD("cdrom") MCFG_PSXCD_ADD("cdrom")
MCFG_PSXCD_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin2))
MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 3, psx_dma_read_delegate( FUNC( cd_dma_read ), (psxcd_device *) device ) ) MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 3, psx_dma_read_delegate( FUNC( cd_dma_read ), (psxcd_device *) device ) )
MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 3, psx_dma_write_delegate( FUNC( cd_dma_write ), (psxcd_device *) device ) ) MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 3, psx_dma_write_delegate( FUNC( cd_dma_write ), (psxcd_device *) device ) )
@ -811,7 +804,7 @@ static MACHINE_CONFIG_START( psxpal, psx1_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2, &spu_irq ) MCFG_SPU_ADD( "spu", XTAL_67_7376MHz/2 )
MCFG_SOUND_ROUTE( 0, "lspeaker", 1.00 ) MCFG_SOUND_ROUTE( 0, "lspeaker", 1.00 )
MCFG_SOUND_ROUTE( 1, "rspeaker", 1.00 ) MCFG_SOUND_ROUTE( 1, "rspeaker", 1.00 )
@ -822,6 +815,7 @@ static MACHINE_CONFIG_START( psxpal, psx1_state )
MCFG_SOFTWARE_LIST_ADD("cd_list","psx") MCFG_SOFTWARE_LIST_ADD("cd_list","psx")
MCFG_PSXCD_ADD("cdrom") MCFG_PSXCD_ADD("cdrom")
MCFG_PSXCD_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin2))
MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 3, psx_dma_read_delegate( FUNC( cd_dma_read ), (psxcd_device *) device ) ) MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 3, psx_dma_read_delegate( FUNC( cd_dma_read ), (psxcd_device *) device ) )
MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 3, psx_dma_write_delegate( FUNC( cd_dma_write ), (psxcd_device *) device ) ) MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 3, psx_dma_write_delegate( FUNC( cd_dma_write ), (psxcd_device *) device ) )

9
src/mess/machine/psxcd.c
View File

@ -106,13 +106,16 @@ void psxcd_device::static_set_devname(device_t &device, const char *devname)
psxcd.m_devname = devname; psxcd.m_devname = devname;
} }
psxcd_device::psxcd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) psxcd_device::psxcd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
: device_t(mconfig, PSXCD, "PSXCD", tag, owner, clock) device_t(mconfig, PSXCD, "PSXCD", tag, owner, clock),
m_irq_handler(*this)
{ {
} }
void psxcd_device::device_start() void psxcd_device::device_start()
{ {
m_irq_handler.resolve_safe();
unsigned int sysclk=machine().device<cpu_device>("maincpu")->clock()/2; unsigned int sysclk=machine().device<cpu_device>("maincpu")->clock()/2;
start_read_delay=(sysclk/60); start_read_delay=(sysclk/60);
read_sector_cycles=(sysclk/75); read_sector_cycles=(sysclk/75);
@ -891,7 +894,7 @@ void psxcd_device::cmd_complete(command_result *res)
if (doint) if (doint)
{ {
psx_irq_set(machine(), 0x0004); m_irq_handler(1);
} }
add_result(res); add_result(res);

9
src/mess/machine/psxcd.h
View File

@ -28,6 +28,9 @@ const int num_commands=0x20;
MCFG_DEVICE_ADD(PSXCD_TAG, PSXCD, 0) \ MCFG_DEVICE_ADD(PSXCD_TAG, PSXCD, 0) \
MCFG_PSXCD_DEVNAME(_devname) MCFG_PSXCD_DEVNAME(_devname)
#define MCFG_PSXCD_IRQ_HANDLER(_devcb) \
devcb = &psxcd_device::set_irq_handler(*device, DEVCB2_##_devcb);
#define MCFG_PSXCD_DEVNAME(_name) \ #define MCFG_PSXCD_DEVNAME(_name) \
psxcd_device::static_set_devname(*device, _name); \ psxcd_device::static_set_devname(*device, _name); \
@ -41,7 +44,9 @@ class psxcd_device : public device_t,
public: public:
psxcd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); psxcd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// inline configuration helpers
// static configuration helpers
template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<psxcd_device &>(device).m_irq_handler.set_callback(object); }
static void static_set_devname(device_t &device, const char *devname); static void static_set_devname(device_t &device, const char *devname);
private: private:
struct command_result struct command_result
@ -164,6 +169,8 @@ private:
bool m_timerinuse[MAX_PSXCD_TIMERS]; bool m_timerinuse[MAX_PSXCD_TIMERS];
void add_system_event(event *ev); void add_system_event(event *ev);
devcb2_write_line m_irq_handler;
}; };