mirror of
https://github.com/holub/mame
synced 2025-04-20 23:42:22 +03:00
Add a plg100-vl skeleton-ish. We have h8-h8 serial communications
reliability issues to track.
This commit is contained in:
Olivier Galibert
parent
fb3539ce0c
commit
300dcfaf79
@ -5518,3 +5518,18 @@ if (BUSES["PCI"]~=null) then
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MAME_DIR .. "src/devices/bus/pci/zr36057.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/bus/plg100/plg100.h,BUSES["PLG100"] = true
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---------------------------------------------------
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if (BUSES["PLG100"]~=null) then
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files {
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MAME_DIR .. "src/devices/bus/plg100/plg100.cpp",
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MAME_DIR .. "src/devices/bus/plg100/plg100.h",
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MAME_DIR .. "src/devices/bus/plg100/vl.cpp",
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MAME_DIR .. "src/devices/bus/plg100/vl.h",
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}
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end
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49
src/devices/bus/plg100/plg100.cpp
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49
src/devices/bus/plg100/plg100.cpp
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@ -0,0 +1,49 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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#include "emu.h"
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#include "plg100.h"
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#include "vl.h"
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DEFINE_DEVICE_TYPE(PLG100_CONNECTOR, plg100_connector, "plg100_connector", "PLG100 extension connector")
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plg100_connector::plg100_connector(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, PLG100_CONNECTOR, tag, owner, clock),
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device_single_card_slot_interface<device_plg100_interface>(mconfig, *this),
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device_mixer_interface(mconfig, *this, 2),
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m_midi_tx(*this)
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{
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}
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void plg100_connector::device_start()
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{
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save_item(NAME(m_state_system_is_annoying));
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}
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void plg100_connector::midi_rx(int state)
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{
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auto card = get_card_device();
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if(card)
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card->midi_rx(state);
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}
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void plg100_intf(device_slot_interface &device)
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{
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device.option_add("vl", PLG100_VL);
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}
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device_plg100_interface::device_plg100_interface(const machine_config &mconfig, device_t &device) :
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device_interface(device, "plg100"),
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m_connector(nullptr)
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{
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}
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device_plg100_interface::~device_plg100_interface()
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{
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}
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void device_plg100_interface::interface_pre_start()
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{
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m_connector = downcast<plg100_connector *>(device().owner());
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}
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70
src/devices/bus/plg100/plg100.h
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70
src/devices/bus/plg100/plg100.h
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@ -0,0 +1,70 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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// The PLG100 series is a bunch of proprietary plugins for the Yamaha
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// MU series of expanders. It mostly provides two midi-rate (and midi
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// protocol) serial lines (in and out) and two stereo serial sample
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// streams (in and out too).
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// Known existing cards:
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// PLG100-DX: DX7 as a plugin
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// PLG100-SG: Singing speech synthesis, e.g. a Vocaloid before the Vocaloid existed
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// PLG100-VH: Voice Harmonizer, harmony effects on the A/D inputs
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// PLG100-VL: Virtual Acoustic Synthesis, physical-modelling synthesis, a VL70-m on a plugin card
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// PLG100-XG: MU50 as a plugin
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#ifndef MAME_BUS_PLG100_PLG100_H
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#define MAME_BUS_PLG100_PLG100_H
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#pragma once
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class device_plg100_interface;
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class plg100_connector: public device_t, public device_single_card_slot_interface<device_plg100_interface>, public device_mixer_interface
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{
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public:
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template <typename T>
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plg100_connector(const machine_config &mconfig, const char *tag, device_t *owner, T &&opts, const char *dflt)
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: plg100_connector(mconfig, tag, owner, (uint32_t)0)
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{
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option_reset();
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opts(*this);
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set_default_option(dflt);
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set_fixed(false);
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}
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plg100_connector(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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void midi_rx(int state);
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auto midi_tx() { return m_midi_tx.bind(); }
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void do_midi_tx(int state) { m_midi_tx(state); }
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protected:
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bool m_state_system_is_annoying = true;
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devcb_write_line m_midi_tx;
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virtual void device_start() override;
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};
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class device_plg100_interface: public device_interface
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{
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public:
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virtual ~device_plg100_interface();
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virtual void midi_rx(int state) = 0;
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protected:
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plg100_connector *m_connector;
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device_plg100_interface(const machine_config &mconfig, device_t &device);
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virtual void interface_pre_start() override;
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};
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DECLARE_DEVICE_TYPE(PLG100_CONNECTOR, plg100_connector)
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void plg100_intf(device_slot_interface &device);
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#endif // MAME_BUS_PLG100_PLG100_H
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96
src/devices/bus/plg100/vl.cpp
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96
src/devices/bus/plg100/vl.cpp
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@ -0,0 +1,96 @@
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// license:BSD-3-Clause
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// copyright-holders: Olivier Galibert
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// Yamaha PLG100-VL
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// Virtual Acoustic Synthesis, physical-modelling synthesis, VL70-m on a plugin board
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// Build around a h8 for the control and a dsp-v for the synthesis
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#include "emu.h"
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#include "vl.h"
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#include "cpu/h8/h83002.h"
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#include "sound/dspv.h"
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namespace {
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class plg100_vl_device : public device_t, public device_plg100_interface
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{
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public:
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plg100_vl_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
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virtual ~plg100_vl_device();
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virtual void midi_rx(int state) override;
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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const tiny_rom_entry *device_rom_region() const override;
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virtual void device_add_mconfig(machine_config &config) override;
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private:
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required_device<h83002_device> m_cpu;
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required_device<dspv_device> m_dspv;
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void map(address_map &map);
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};
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plg100_vl_device::plg100_vl_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, PLG100_VL, tag, owner, clock),
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device_plg100_interface(mconfig, *this),
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m_cpu(*this, "cpu"),
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m_dspv(*this, "dspv")
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{
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}
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plg100_vl_device::~plg100_vl_device()
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{
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}
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void plg100_vl_device::midi_rx(int state)
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{
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m_cpu->sci_rx_w<0>(state);
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}
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void plg100_vl_device::map(address_map &map)
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{
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map(0x000000, 0x0fffff).rom().region("cpu", 0);
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map(0x400000, 0x40007f).m(m_dspv, FUNC(dspv_device::map));
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map(0x200000, 0x20ffff).ram();
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}
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void plg100_vl_device::device_add_mconfig(machine_config &config)
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{
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H83002(config, m_cpu, 10_MHz_XTAL);
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m_cpu->set_addrmap(AS_PROGRAM, &plg100_vl_device::map);
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m_cpu->write_sci_tx<1>().set([this] (int state) { m_connector->do_midi_tx(state); });
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DSPV(config, m_dspv, 22.5792_MHz_XTAL);
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m_dspv->add_route(0, DEVICE_SELF_OWNER, 1.0, AUTO_ALLOC_INPUT, 0);
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m_dspv->add_route(1, DEVICE_SELF_OWNER, 1.0, AUTO_ALLOC_INPUT, 1);
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}
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ROM_START( plg100_vl )
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ROM_REGION( 0x100000, "cpu", 0 )
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ROM_LOAD16_WORD_SWAP( "xt47810.ic03", 0x000000, 0x100000, CRC(ef472e45) SHA1(13d54c33a4708c77de2dc1e02210da107add6ce6) )
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ROM_END
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void plg100_vl_device::device_start()
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{
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}
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void plg100_vl_device::device_reset()
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{
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// Active-low, wired to gnd
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m_cpu->set_input_line(0, ASSERT_LINE);
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}
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const tiny_rom_entry *plg100_vl_device::device_rom_region() const
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{
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return ROM_NAME(plg100_vl);
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}
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} // anonymous namespace
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DEFINE_DEVICE_TYPE_PRIVATE(PLG100_VL, device_plg100_interface, plg100_vl_device, "plg100_vl", "Yamaha PLG100-VL")
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15
src/devices/bus/plg100/vl.h
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15
src/devices/bus/plg100/vl.h
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@ -0,0 +1,15 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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#ifndef MAME_BUS_PLG100_VL_H
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#define MAME_BUS_PLG100_VL_H
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// Yamaha PLG100-VL
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#pragma once
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#include "plg100.h"
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DECLARE_DEVICE_TYPE(PLG100_VL, device_plg100_interface)
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#endif // MAME_BUS_PLG100_VL_H
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@ -1,3 +1,6 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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#ifndef MAME_BUS_WAVEBLASTER_DB50XG_H
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#define MAME_BUS_WAVEBLASTER_DB50XG_H
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@ -1,3 +1,6 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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#ifndef MAME_BUS_WAVEBLASTER_DB60XG_H
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#define MAME_BUS_WAVEBLASTER_DB60XG_H
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@ -1,3 +1,6 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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#ifndef MAME_BUS_WAVEBLASTER_OMNIWAVE_H
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#define MAME_BUS_WAVEBLASTER_OMNIWAVE_H
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@ -1,3 +1,6 @@
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// license:BSD-3-Clause
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// copyright-holders: Devin Acker
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#ifndef MAME_BUS_WAVEBLASTER_WG130_H
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#define MAME_BUS_WAVEBLASTER_WG130_H
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@ -42,7 +42,7 @@ public:
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m_sci[sci].lookup()->do_set_external_clock_period(period);
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}
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template<int Sci> void sci_rx_w(int state) { m_sci[Sci]->do_rx_w(state); }
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template<int Sci> void sci_rx_w(int state) { if(Sci == 2) logerror("sci2 rx %d\n", state); m_sci[Sci]->do_rx_w(state); }
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template<int Sci> void sci_clk_w(int state) { m_sci[Sci]->do_clk_w(state); }
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void nvram_set_battery(int state) { m_nvram_battery = bool(state); } // default is 1 (nvram_enable_backup needs to be true)
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@ -735,7 +735,7 @@ void swp30_device::keyon_w(u16)
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m_lfo_phase[chan] = 0;
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if(1)
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logerror("[%08d] keyon %02x %08x %08x %08x vol %04x env %04x %04x %04x\n", scount, chan, m_sample_start[chan], m_sample_end[chan], m_sample_address[chan], m_release_glo[chan], m_attack[chan], m_decay1[chan], m_decay2[chan]);
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logerror("[%08d] keyon %02x %08x %08x %08x vol %04x env %04x %04x %04x pitch %04x pmod %04x\n", scount, chan, m_sample_start[chan], m_sample_end[chan], m_sample_address[chan], m_release_glo[chan], m_attack[chan], m_decay1[chan], m_decay2[chan], m_pitch[chan], m_lfo_step_pmod[chan]);
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}
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}
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m_keyon_mask = 0;
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@ -1494,6 +1494,7 @@ void swp30_device::execute_run()
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while(adr <= target_address) {
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m_dpcm_current[chan] = m_dpcm_next[chan];
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s32 sample = m_dpcm_next[chan] + m_dpcm[(m_rom_cache.read_dword(adr >> 2) >> (8*(adr & 3))) & 0xff];
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// logerror("## + sample %08x %02x %d\n", adr, (m_rom_cache.read_dword(adr >> 2) >> (8*(adr & 3))) & 0xff, sample);
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adr ++;
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if(sample < -0x8000)
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sample = -0x8000;
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@ -127,6 +127,7 @@
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#include "cpu/h8/h8s2655.h"
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#include "mulcd.h"
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#include "sound/swp30.h"
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#include "bus/plg100/plg100.h"
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#include "debugger.h"
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#include "speaker.h"
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@ -164,126 +165,34 @@ public:
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, m_maincpu(*this, "maincpu")
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, m_swp30(*this, "swp30")
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, m_lcd(*this, "lcd")
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, m_ext1(*this, "ext1")
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, m_ext2(*this, "ext2")
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, m_ioport_p7(*this, "P7")
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, m_ioport_p8(*this, "P8")
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{ }
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void mu100(machine_config &config);
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void regs_s1_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_s2_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_s3_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_s4a_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_s4b_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_s4c_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_lfo_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_s6_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_fp_read_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_fp_write_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_int_read_tap(offs_t address, u16 data, u16 mem_mask);
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void regs_int_write_tap(offs_t address, u16 data, u16 mem_mask);
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void voice_write_tap(offs_t address, u16 data, u16 mem_mask);
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void voice_read_tap(offs_t address, u16 data, u16 mem_mask);
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void chan_write_tap(offs_t address, u16 data, u16 mem_mask);
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void prg_write_tap(offs_t address, u16 data, u16 mem_mask);
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virtual void machine_reset() override {
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if(0)
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m_maincpu->space(0).install_write_tap(0x214cb8, 0x214cbf, "prg select", [this](offs_t offset, u16 &data, u16 mem_mask) {
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prg_write_tap(offset, data, mem_mask);
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});
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if(0)
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m_maincpu->space(0).install_write_tap(0x20cb10, 0x20cb10 + 0x122*0x22 - 1, "chan debug", [this](offs_t offset, u16 &data, u16 mem_mask) {
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chan_write_tap(offset, data, mem_mask);
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});
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if(0)
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m_maincpu->space(0).install_write_tap(0x20f03e, 0x20f03e + 0x92*0x40 - 1, "voice debug", [this](offs_t offset, u16 &data, u16 mem_mask) {
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voice_write_tap(offset, data, mem_mask);
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});
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if(0)
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m_maincpu->space(0).install_read_tap(0x20f03e, 0x20f03e + 0x92*0x40 - 1, "voice debug", [this](offs_t offset, u16 &data, u16 mem_mask) {
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voice_read_tap(offset, data, mem_mask);
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});
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if(0)
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m_maincpu->space(0).install_readwrite_tap(0x214ca2+0x20, 0x214ca2+0x320-1, "regs fp",
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[this](offs_t offset, u16 &data, u16 mem_mask) {
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regs_fp_read_tap(offset, data, mem_mask);
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},
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[this](offs_t offset, u16 &data, u16 mem_mask) {
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regs_fp_write_tap(offset, data, mem_mask);
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});
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if(0)
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m_maincpu->space(0).install_readwrite_tap(0x214ca2+0x320, 0x214ca2+0x420-1, "regs int",
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[this](offs_t offset, u16 &data, u16 mem_mask) {
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regs_int_read_tap(offset, data, mem_mask);
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},
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[this](offs_t offset, u16 &data, u16 mem_mask) {
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regs_int_write_tap(offset, data, mem_mask);
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});
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if(0)
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m_maincpu->space(0).install_write_tap(0x214ca2+0x420, 0x214ca2+0x440-1, "regs s1", [this](offs_t offset, u16 &data, u16 mem_mask) {
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regs_s1_write_tap(offset, data, mem_mask);
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});
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if(0)
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m_maincpu->space(0).install_write_tap(0x214ca2+0x440, 0x214ca2+0x460-1, "regs s2", [this](offs_t offset, u16 &data, u16 mem_mask) {
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regs_s2_write_tap(offset, data, mem_mask);
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});
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if(0)
|
||||
m_maincpu->space(0).install_write_tap(0x214ca2+0x460, 0x214ca2+0x480-1, "regs s3", [this](offs_t offset, u16 &data, u16 mem_mask) {
|
||||
regs_s3_write_tap(offset, data, mem_mask);
|
||||
});
|
||||
if(0)
|
||||
m_maincpu->space(0).install_write_tap(0x214ca2+0x480, 0x214ca2+0x4a0-1, "regs s4a", [this](offs_t offset, u16 &data, u16 mem_mask) {
|
||||
regs_s4a_write_tap(offset, data, mem_mask);
|
||||
});
|
||||
if(0)
|
||||
m_maincpu->space(0).install_write_tap(0x214ca2+0x4a0, 0x214ca2+0x4c0-1, "regs s4b", [this](offs_t offset, u16 &data, u16 mem_mask) {
|
||||
regs_s4b_write_tap(offset, data, mem_mask);
|
||||
});
|
||||
if(0)
|
||||
m_maincpu->space(0).install_write_tap(0x214ca2+0x4c0, 0x214ca2+0x4e0-1, "regs s4c", [this](offs_t offset, u16 &data, u16 mem_mask) {
|
||||
regs_s4c_write_tap(offset, data, mem_mask);
|
||||
});
|
||||
if(0)
|
||||
m_maincpu->space(0).install_write_tap(0x214ca2+0x4e0, 0x214ca2+0x510-1, "regs lfo", [this](offs_t offset, u16 &data, u16 mem_mask) {
|
||||
regs_lfo_write_tap(offset, data, mem_mask);
|
||||
});
|
||||
if(0)
|
||||
m_maincpu->space(0).install_write_tap(0x214ca2+0x510, 0x214ca2+0x520-1, "regs s6", [this](offs_t offset, u16 &data, u16 mem_mask) {
|
||||
regs_s6_write_tap(offset, data, mem_mask);
|
||||
});
|
||||
}
|
||||
|
||||
protected:
|
||||
virtual u16 adc_type_r();
|
||||
|
||||
private:
|
||||
enum {
|
||||
P2_LCD_RS = 0x01,
|
||||
P2_LCD_RW = 0x02,
|
||||
P2_LCD_ENABLE = 0x04
|
||||
};
|
||||
|
||||
enum {
|
||||
P6_LCD_RS = 0x04,
|
||||
P6_LCD_RW = 0x02,
|
||||
P6_LCD_ENABLE = 0x01
|
||||
};
|
||||
|
||||
enum {
|
||||
PA_LCD_RS = 0x02,
|
||||
PA_LCD_ENABLE = 0x20,
|
||||
PA_LCD_RW = 0x40
|
||||
};
|
||||
|
||||
required_device<h8s2655_device> m_maincpu;
|
||||
required_device<swp30_device> m_swp30;
|
||||
required_device<mulcd_device> m_lcd;
|
||||
required_device<plg100_connector> m_ext1;
|
||||
optional_device<plg100_connector> m_ext2;
|
||||
required_ioport m_ioport_p7;
|
||||
required_ioport m_ioport_p8;
|
||||
|
||||
u8 cur_p1, cur_p2, cur_p3, cur_p5, cur_p6, cur_pa, cur_pb, cur_pc, cur_pf, cur_pg;
|
||||
u8 cur_ic32;
|
||||
u8 m_cur_p1, m_cur_p2, m_cur_p3, m_cur_p5, m_cur_p6, m_cur_pa, m_cur_pb, m_cur_pc, m_cur_pf, m_cur_pg;
|
||||
u8 m_cur_ic32, m_cur_sw;
|
||||
int m_h8_tx, m_e1_tx, m_e2_tx;
|
||||
|
||||
u16 adc_ar_r();
|
||||
u16 adc_al_r();
|
||||
@ -304,7 +213,14 @@ private:
|
||||
void pf_w(u16 data);
|
||||
void pg_w(u16 data);
|
||||
|
||||
void ext_serial_update();
|
||||
void h8_tx(int state);
|
||||
void e1_tx(int state);
|
||||
void e2_tx(int state);
|
||||
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
||||
void mu100_map(address_map &map);
|
||||
void swp30_map(address_map &map);
|
||||
};
|
||||
@ -315,220 +231,36 @@ public:
|
||||
: mu100_state(mconfig, type, tag)
|
||||
{ }
|
||||
|
||||
void mu100r(machine_config &config);
|
||||
|
||||
private:
|
||||
virtual u16 adc_type_r() override;
|
||||
};
|
||||
|
||||
void mu100_state::prg_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
if(mem_mask == 0x00ff) {
|
||||
static const char *names[4] = { "chorus", "variation", "insertion1", "insertion2" };
|
||||
logerror("prg_select %s %d\n", names[(address - 0x214cb8)/2], data);
|
||||
}
|
||||
}
|
||||
|
||||
void mu100_state::regs_s1_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x420)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_s1_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_s2_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x440)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_s2_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_s3_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x460)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_s3_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_s4a_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x480)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_s4a_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_s4b_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x4a0)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_s4b_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_s4c_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x4c0)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_s4c_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_lfo_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x4e0)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_lfo_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_s6_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x510)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_s6_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_fp_read_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x20)/2;
|
||||
if(pc != 0x72912)
|
||||
logerror("regs_fp_r %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_fp_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x20)/2;
|
||||
logerror("regs_fp_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_int_read_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x320)/2;
|
||||
if(pc != 0x729c6)
|
||||
logerror("regs_int_r %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
void mu100_state::regs_int_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t reg = (address - 0x214ca2-0x320)/2;
|
||||
logerror("regs_int_w %03x, %04x @ %04x (%06x)\n", reg, data, mem_mask, pc);
|
||||
}
|
||||
|
||||
struct xmap {
|
||||
int slot;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
static xmap vmap[] = {
|
||||
{ 0x00, "instrumenthi" },
|
||||
{ 0x02, "instrumentlo" },
|
||||
{ 0x04, "midi_channelhi" },
|
||||
{ 0x06, "midi_channello" },
|
||||
{ 0x0c, "lpf_cutoff" },
|
||||
{ 0x42, "delay_time" },
|
||||
{ 0x48, "active" },
|
||||
{ 0x4a, "velocity" },
|
||||
{ 0x51, "inverse_velocity" },
|
||||
{ -1, "" },
|
||||
};
|
||||
|
||||
void mu100_state::voice_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t off = address - 0x20f03e;
|
||||
int voice = off / 0x92;
|
||||
int slot = off % 0x92;
|
||||
|
||||
if(mem_mask == 0xff00)
|
||||
data >>= 8;
|
||||
else if(mem_mask == 0x00ff)
|
||||
slot++;
|
||||
|
||||
std::string slotname = util::string_format("%02x", slot);
|
||||
for(int i=0; vmap[i].slot != -1; i++)
|
||||
if(vmap[i].slot == slot)
|
||||
slotname = vmap[i].name;
|
||||
|
||||
if(mem_mask == 0xffff) {
|
||||
logerror("voice_w %02x:%s, %04x (%06x)\n", voice, slotname, data, pc);
|
||||
} else {
|
||||
logerror("voice_w %02x:%s, %02x (%06x)\n", voice, slotname, data, pc);
|
||||
}
|
||||
}
|
||||
|
||||
void mu100_state::voice_read_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t off = address - 0x20f03e;
|
||||
int voice = off / 0x92;
|
||||
int slot = off % 0x92;
|
||||
|
||||
logerror("off %x voice %x slot %x mask %04x\n", off, voice, slot, mem_mask);
|
||||
data &= mem_mask;
|
||||
if(mem_mask == 0xff00)
|
||||
data >>= 8;
|
||||
else if(mem_mask == 0x00ff)
|
||||
slot++;
|
||||
|
||||
std::string slotname = util::string_format("%02x", slot);
|
||||
for(int i=0; vmap[i].slot != -1; i++)
|
||||
if(vmap[i].slot == slot)
|
||||
slotname = vmap[i].name;
|
||||
|
||||
if(mem_mask == 0xffff) {
|
||||
logerror("voice_r %02x:%s, %04x (%06x)\n", voice, slotname, data, pc);
|
||||
} else {
|
||||
logerror("voice_r %02x:%s, %02x (%06x)\n", voice, slotname, data, pc);
|
||||
}
|
||||
}
|
||||
|
||||
void mu100_state::chan_write_tap(offs_t address, u16 data, u16 mem_mask)
|
||||
{
|
||||
offs_t pc = m_maincpu->pc();
|
||||
offs_t off = address - 0x20cb10;
|
||||
int voice = off / 0x112;
|
||||
int slot = off % 0x112;
|
||||
if(mem_mask == 0xffff) {
|
||||
if(slot == 0x102 && data == 0)
|
||||
return;
|
||||
if(slot == 0x100 && data == 0)
|
||||
return;
|
||||
if(slot == 0x0fe && data == 0)
|
||||
return;
|
||||
logerror("chan_w %02x:%03x, %04x (%06x)\n", voice, slot, data, pc);
|
||||
} else {
|
||||
if(mem_mask == 0xff00)
|
||||
data >>= 8;
|
||||
else
|
||||
slot++;
|
||||
if(slot == 0x106 && data == 0)
|
||||
return;
|
||||
if(slot == 0x108 && data == 0)
|
||||
return;
|
||||
if(slot == 0x105) // volume
|
||||
return;
|
||||
if(slot == 0x109 && data == 0)
|
||||
return;
|
||||
if(slot == 0x0e7 && data == 0)
|
||||
return;
|
||||
if(slot == 0x0e5 && data == 0)
|
||||
return;
|
||||
if(slot == 0x111 && data == 0x40)
|
||||
return;
|
||||
logerror("chan_w %02x:%03x, %02x (%06x)\n", voice, slot, data, pc);
|
||||
}
|
||||
}
|
||||
|
||||
void mu100_state::machine_start()
|
||||
{
|
||||
cur_p1 = cur_p2 = cur_p3 = cur_p5 = cur_p6 = cur_pa = cur_pc = cur_pf = cur_pg = cur_ic32 = 0xff;
|
||||
save_item(NAME(m_cur_p1));
|
||||
save_item(NAME(m_cur_p2));
|
||||
save_item(NAME(m_cur_p3));
|
||||
save_item(NAME(m_cur_p5));
|
||||
save_item(NAME(m_cur_p6));
|
||||
save_item(NAME(m_cur_pa));
|
||||
save_item(NAME(m_cur_pc));
|
||||
save_item(NAME(m_cur_pf));
|
||||
save_item(NAME(m_cur_pg));
|
||||
save_item(NAME(m_cur_ic32));
|
||||
save_item(NAME(m_cur_sw));
|
||||
save_item(NAME(m_h8_tx));
|
||||
save_item(NAME(m_e1_tx));
|
||||
save_item(NAME(m_e2_tx));
|
||||
}
|
||||
|
||||
void mu100_state::machine_reset()
|
||||
{
|
||||
m_cur_p1 = m_cur_p2 = m_cur_p3 = m_cur_p5 = m_cur_p6 = m_cur_pa = m_cur_pc = m_cur_pf = m_cur_pg = m_cur_ic32 = 0xff;
|
||||
m_cur_sw = 0;
|
||||
m_h8_tx = m_e1_tx = m_e2_tx = 1;
|
||||
ext_serial_update();
|
||||
}
|
||||
|
||||
void mu100_state::mu100_map(address_map &map)
|
||||
@ -575,14 +307,14 @@ u16 mu100r_state::adc_type_r()
|
||||
|
||||
void mu100_state::p1_w(u16 data)
|
||||
{
|
||||
cur_p1 = data;
|
||||
m_cur_p1 = data;
|
||||
}
|
||||
|
||||
u16 mu100_state::p1_r()
|
||||
{
|
||||
if((cur_p2 & P2_LCD_ENABLE)) {
|
||||
if(cur_p2 & P2_LCD_RW) {
|
||||
if(cur_p2 & P2_LCD_RS)
|
||||
if((m_cur_p2 & P2_LCD_ENABLE)) {
|
||||
if(m_cur_p2 & P2_LCD_RW) {
|
||||
if(m_cur_p2 & P2_LCD_RS)
|
||||
return m_lcd->data_read();
|
||||
else
|
||||
return m_lcd->control_read();
|
||||
@ -590,11 +322,11 @@ u16 mu100_state::p1_r()
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
if(!(cur_pf & 0x02)) {
|
||||
if(!(m_cur_pf & 0x02)) {
|
||||
u8 val = 0xff;
|
||||
if(!(cur_ic32 & 0x20))
|
||||
if(!(m_cur_ic32 & 0x20))
|
||||
val &= m_ioport_p7->read();
|
||||
if(!(cur_ic32 & 0x40))
|
||||
if(!(m_cur_ic32 & 0x40))
|
||||
val &= m_ioport_p8->read();
|
||||
return val;
|
||||
}
|
||||
@ -605,34 +337,35 @@ u16 mu100_state::p1_r()
|
||||
void mu100_state::p2_w(u16 data)
|
||||
{
|
||||
// LCB enable edge
|
||||
if(!(cur_p2 & P2_LCD_ENABLE) && (data & P2_LCD_ENABLE)) {
|
||||
if(!(cur_p2 & P2_LCD_RW)) {
|
||||
if(cur_p2 & P2_LCD_RS)
|
||||
m_lcd->data_write(cur_p1);
|
||||
if(!(m_cur_p2 & P2_LCD_ENABLE) && (data & P2_LCD_ENABLE)) {
|
||||
if(!(m_cur_p2 & P2_LCD_RW)) {
|
||||
if(m_cur_p2 & P2_LCD_RS)
|
||||
m_lcd->data_write(m_cur_p1);
|
||||
else
|
||||
m_lcd->control_write(cur_p1);
|
||||
m_lcd->control_write(m_cur_p1);
|
||||
}
|
||||
}
|
||||
m_lcd->set_contrast((data >> 3) & 7);
|
||||
cur_p2 = data;
|
||||
m_cur_p2 = data;
|
||||
}
|
||||
|
||||
void mu100_state::p3_w(u16 data)
|
||||
{
|
||||
cur_p3 = data;
|
||||
m_cur_p3 = data;
|
||||
logerror("A/D gain control %d\n", (data >> 4) & 3);
|
||||
}
|
||||
|
||||
void mu100_state::p5_w(u16 data)
|
||||
{
|
||||
cur_p5 = data;
|
||||
m_cur_p5 = data;
|
||||
logerror("Rotary reset %d\n", (data >> 3) & 1);
|
||||
}
|
||||
|
||||
void mu100_state::p6_w(u16 data)
|
||||
{
|
||||
cur_p6 = data;
|
||||
logerror("pbsel %d pbreset %d soundreset %d\n", (data >> 2) & 3, (data >> 4) & 1, (data >> 5) & 1);
|
||||
m_cur_p6 = data;
|
||||
m_cur_sw = (m_cur_sw & 0xc) | BIT(m_cur_pf, 2, 2);
|
||||
ext_serial_update();
|
||||
}
|
||||
|
||||
u16 mu100_state::p6_r()
|
||||
@ -643,7 +376,7 @@ u16 mu100_state::p6_r()
|
||||
|
||||
void mu100_state::pa_w(u16 data)
|
||||
{
|
||||
cur_pa = data;
|
||||
m_cur_pa = data;
|
||||
logerror("rotary encoder %d\n", (data >> 6) & 3);
|
||||
}
|
||||
|
||||
@ -655,17 +388,56 @@ u16 mu100_state::pa_r()
|
||||
|
||||
void mu100_state::pf_w(u16 data)
|
||||
{
|
||||
if(!(cur_pf & 0x01) && (data & 0x01)) {
|
||||
cur_ic32 = cur_p1;
|
||||
m_lcd->set_leds((cur_p1 & 0x1f) | ((cur_p1 & 0x80) >> 2));
|
||||
if(!(m_cur_pf & 0x01) && (data & 0x01)) {
|
||||
m_cur_ic32 = m_cur_p1;
|
||||
m_lcd->set_leds((m_cur_p1 & 0x1f) | ((m_cur_p1 & 0x80) >> 2));
|
||||
}
|
||||
cur_pf = data;
|
||||
m_cur_pf = data;
|
||||
m_cur_sw = (m_cur_sw & 0x7) | (BIT(m_cur_pf, 2) << 3);
|
||||
ext_serial_update();
|
||||
}
|
||||
|
||||
void mu100_state::pg_w(u16 data)
|
||||
{
|
||||
cur_pg = data;
|
||||
logerror("pbsel3 %d\n", data & 1);
|
||||
m_cur_pg = data;
|
||||
m_cur_sw = (m_cur_sw & 0xb) | (BIT(m_cur_pg, 0) << 2);
|
||||
ext_serial_update();
|
||||
}
|
||||
|
||||
void mu100_state::ext_serial_update()
|
||||
{
|
||||
m_ext1->midi_rx(BIT(m_cur_sw, 3) ? m_h8_tx : 1);
|
||||
if(m_ext2)
|
||||
m_ext2->midi_rx(BIT(m_cur_sw, 1) ? m_h8_tx : 1);
|
||||
if(BIT(m_cur_sw, 2))
|
||||
if(BIT(m_cur_sw, 0))
|
||||
m_maincpu->sci_rx_w<2>(m_e1_tx && m_e2_tx);
|
||||
else
|
||||
m_maincpu->sci_rx_w<2>(m_e1_tx);
|
||||
else
|
||||
if(BIT(m_cur_sw, 0))
|
||||
m_maincpu->sci_rx_w<2>(m_e2_tx);
|
||||
else
|
||||
m_maincpu->sci_rx_w<2>(1);
|
||||
}
|
||||
|
||||
void mu100_state::h8_tx(int state)
|
||||
{
|
||||
m_h8_tx = state;
|
||||
ext_serial_update();
|
||||
}
|
||||
|
||||
void mu100_state::e1_tx(int state)
|
||||
{
|
||||
logerror("e1 tx %d\n", state);
|
||||
m_e1_tx = state;
|
||||
ext_serial_update();
|
||||
}
|
||||
|
||||
void mu100_state::e2_tx(int state)
|
||||
{
|
||||
m_e2_tx = state;
|
||||
ext_serial_update();
|
||||
}
|
||||
|
||||
void mu100_state::swp30_map(address_map &map)
|
||||
@ -698,9 +470,13 @@ void mu100_state::mu100(machine_config &config)
|
||||
m_maincpu->write_porta().set(FUNC(mu100_state::pa_w));
|
||||
m_maincpu->write_portf().set(FUNC(mu100_state::pf_w));
|
||||
m_maincpu->write_portg().set(FUNC(mu100_state::pg_w));
|
||||
m_maincpu->write_sci_tx<2>().set(FUNC(mu100_state::h8_tx));
|
||||
|
||||
MULCD(config, m_lcd);
|
||||
|
||||
PLG100_CONNECTOR(config, m_ext1, plg100_intf, "vl");
|
||||
m_ext1->midi_tx().set(FUNC(mu100_state::e1_tx));
|
||||
|
||||
SPEAKER(config, "lspeaker").front_left();
|
||||
SPEAKER(config, "rspeaker").front_right();
|
||||
|
||||
@ -722,6 +498,14 @@ void mu100_state::mu100(machine_config &config)
|
||||
m_maincpu->write_sci_tx<0>().set(mdout, FUNC(midi_port_device::write_txd));
|
||||
}
|
||||
|
||||
void mu100r_state::mu100r(machine_config &config)
|
||||
{
|
||||
mu100(config);
|
||||
|
||||
PLG100_CONNECTOR(config, m_ext2, plg100_intf, nullptr);
|
||||
m_ext2->midi_tx().set(FUNC(mu100r_state::e2_tx));
|
||||
}
|
||||
|
||||
#define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \
|
||||
ROMX_LOAD(name, offset, length, hash, ROM_GROUPWORD | ROM_REVERSE | ROM_BIOS(bios))
|
||||
|
||||
@ -746,7 +530,7 @@ ROM_START( mu100 )
|
||||
ROM_LOAD32_WORD( "xt463a0.ic38", 0x1000002, 0x400000, CRC(cce5f8d3) SHA1(bdca8c5158f452f2b5535c7d658c9b22c6d66048) )
|
||||
ROM_END
|
||||
|
||||
// mu100r is identical to the mu100
|
||||
// mu100r roms are identical to the mu100
|
||||
#define rom_mu100r rom_mu100
|
||||
|
||||
ROM_START( mu100b )
|
||||
@ -766,6 +550,6 @@ ROM_END
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
SYST( 1997, mu100, 0, 0, mu100, mu100, mu100_state, empty_init, "Yamaha", "MU100", MACHINE_NOT_WORKING )
|
||||
SYST( 1997, mu100r, mu100, 0, mu100, mu100, mu100r_state, empty_init, "Yamaha", "MU100 Rackable version", MACHINE_NOT_WORKING )
|
||||
SYST( 1998, mu100b, mu100, 0, mu100, mu100, mu100_state, empty_init, "Yamaha", "MU100B", MACHINE_NOT_WORKING )
|
||||
SYST( 1997, mu100, 0, 0, mu100, mu100, mu100_state, empty_init, "Yamaha", "MU100", MACHINE_NOT_WORKING )
|
||||
SYST( 1997, mu100r, mu100, 0, mu100r, mu100, mu100r_state, empty_init, "Yamaha", "MU100 Rackable version", MACHINE_NOT_WORKING )
|
||||
SYST( 1998, mu100b, mu100, 0, mu100, mu100, mu100_state, empty_init, "Yamaha", "MU100 Screenless version", MACHINE_NOT_WORKING )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user