From 1459d8316c63ec25625a6c3577d6c4298f6d24eb Mon Sep 17 00:00:00 2001 From: Joakim Larsson Edstrom Date: Wed, 6 Jul 2016 20:45:59 +0200 Subject: [PATCH 1/4] New device: FGA-002 Force Gate Array, splitted out from fccpu30 driver, mostly a skeleton but most registers can be written and read back, 8 bit timer is implemented --- scripts/src/machine.lua | 12 + scripts/target/mame/mess.lua | 1 + src/devices/machine/fga002.cpp | 512 +++++++++++++++++++++++++++++++++ src/devices/machine/fga002.h | 181 ++++++++++++ 4 files changed, 706 insertions(+) create mode 100644 src/devices/machine/fga002.cpp create mode 100644 src/devices/machine/fga002.h diff --git a/scripts/src/machine.lua b/scripts/src/machine.lua index 7ddf031d76d..a4e3a9032cc 100644 --- a/scripts/src/machine.lua +++ b/scripts/src/machine.lua @@ -794,6 +794,18 @@ if (MACHINES["F3853"]~=null) then } end +--------------------------------------------------- +-- +--@src/devices/machine/fga002.h,MACHINES["FGA002"] = true +--------------------------------------------------- + +if (MACHINES["FGA002"]~=null) then + files { + MAME_DIR .. "src/devices/machine/fga002.cpp", + MAME_DIR .. "src/devices/machine/fga002.h", + } +end + --------------------------------------------------- -- --@src/devices/machine/hd63450.h,MACHINES["HD63450"] = true diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua index 3532f4d5ad7..6e35904c56b 100644 --- a/scripts/target/mame/mess.lua +++ b/scripts/target/mame/mess.lua @@ -585,6 +585,7 @@ MACHINES["APPLE_DRIVE"] = true MACHINES["APPLE_FDC"] = true MACHINES["SONY_DRIVE"] = true MACHINES["SCNXX562"] = true +MACHINES["FGA002"] = true -------------------------------------------------- -- specify available bus cores diff --git a/src/devices/machine/fga002.cpp b/src/devices/machine/fga002.cpp new file mode 100644 index 00000000000..4cd77414612 --- /dev/null +++ b/src/devices/machine/fga002.cpp @@ -0,0 +1,512 @@ +// license:BSD-3-Clause +// copyright-holders:Joakim Larsson Edstrom +/********************************************************************** +* +* Force Computer FGA-002 Force Gate Array +* +* Documetation: http://bitsavers.informatik.uni-stuttgart.de/pdf/forceComputers/201559_FGA-002_Nov96.pdf +* +* The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and containing 24,000 gates in a 281 pin PGA +* package. It provides interfaces to the 68020/30 microprocessor as well as a VMEbus compatible interface. +* The auxilary interface of the gate array is a high speed data channel used by the internal 32 bit DMA controller. The interface +* allows data transfer rates of up to 6 MByte/second. The timing of the local I/O interface is programmable and provides +* easy interfacing of local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly connected or +* connected via buffers to the gate array allowing easy implementation and usage. The gate array registers are programmed by the local CPU. +* +* FEATURES: +* - Programmable decoding for CPU and VME access to the local main memory +* - Interrupt management for internal and external interrupt sources +* - 32 bit multi-port DMA Controller +* - FORCE Message Broadcast slave interface with 2 message channels +* - 8 interrupt capable MAILBOXES +* - 8 bit TIMER with 16 selectable internal source clocks +* +* +* CAUTION (from the documentation - no unducumented registers are currently emulated ) +* The FGA-002 gate array contains registers, which are used to configure the gate array for special external hardware +* requirements. These registers are reserved and will be setup by the boot software according to the hardware environment in which the gate array is +* implemented. These registers must not be changed by the user. Some of these hardware configuration registers also contain user selectable bits. +* Programming the contents of these registers has to be done carefully without changing the bits initialized by the boot software. +* Registers not described must not be programmed. Unqualified changes of register bits may have unpredictable consequences for the gate array and +* external hardware. It is expressly forbidden to change register bits, except those defined for the user. +* +*/ +#include "fga002.h" + +#define VERBOSE 0 + +#define LOG(x) do { if (VERBOSE) logerror x; } while (0) +#define LOGR(x) +#if VERBOSE == 2 +#define logerror printf +#endif + +#ifdef _MSC_VER +#define FUNCNAME __func__ +#define LLFORMAT "%I64%" +#else +#define FUNCNAME __PRETTY_FUNCTION__ +#define LLFORMAT "%lld" +#endif + +//************************************************************************** +// DEVICE DEFINITIONS +//************************************************************************** +// device type definition +const device_type FGA002 = &device_creator; + +//************************************************************************** +// LIVE DEVICE +//************************************************************************** + +//------------------------------------------------- +// fga002_device - constructor +//------------------------------------------------- + +fga002_device::fga002_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source) + : device_t(mconfig, type, name, tag, owner, clock, shortname, source) +{ +} + +fga002_device::fga002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : device_t(mconfig, FGA002, "FGA-002", tag, owner, clock, "fga002", __FILE__) +{ +} + +void fga002_device::device_start() +{ + LOG(("%s\n", FUNCNAME)); + + // Timers + fga_timer = timer_alloc(TIMER_ID_FGA); + + save_pointer (NAME (m_fga002), sizeof(m_fga002)); +} + +void fga002_device::device_reset() +{ + LOG(("%s\n", FUNCNAME)); + /* Reset values for the FGA-002 */ + memset(&m_fga002[0], 0, sizeof(m_fga002)); + m_fga002[FGA_RSVMECALL] = 0x80; + m_fga002[FGA_RSKEYRES] = 0x80; + m_fga002[FGA_RSCPUCALL] = 0x80; + m_fga002[FGA_RSLOCSW] = 0x80; + m_fga002[FGA_ISTIM0] = 0x80; + m_fga002[FGA_ISDMANORM] = 0x80; + m_fga002[FGA_ISDMAERR] = 0x80; + m_fga002[FGA_ISFMB0REF] = 0x80; + m_fga002[FGA_ISFMB1REF] = 0x80; + m_fga002[FGA_ISPARITY] = 0x80; + m_fga002[FGA_ISABORT] = 0x80; + m_fga002[FGA_ISACFAIL] = 0x80; + m_fga002[FGA_ISSYSFAIL] = 0x80; + m_fga002[FGA_ISFMB0MES] = 0x80; + m_fga002[FGA_ISFMB1MES] = 0x80; +} + +//------------------------------------------------- +// device_timer - handler timer events +//------------------------------------------------- +void fga002_device::device_timer (emu_timer &timer, device_timer_id id, INT32 param, void *ptr) +{ + switch(id) + { + case TIMER_ID_FGA: + if (m_tim0count-- == 0) // Zero detect + { + if ((m_fga002[FGA_TIM0CTL] & REG_TIM0CTL_ZERO_STOP) == 0) + { + fga_timer->adjust(attotime::never, TIMER_ID_FGA, attotime::never); + } + else + { + if ((m_fga002[FGA_TIM0CTL] & REG_TIM0CTL_AUTOPRELOAD) == 0) + m_tim0count &= 0xff; + else + m_tim0count = m_fga002[FGA_TIM0PRELOAD]; + } + } + break; + default: + LOG(("Unhandled Timer ID %d\n", id)); + break; + } +} + + + +/* The FGA002 Timer + + FEATURES + - 8 bit Synchronous Counter + - 16 selectable clocks with frequencies from 1MHz to 0.5 Hz + - Autopreload and Zerostop operating modes + - Watchdog Timer operation + - SYSFAIL and/or interrupt generation + - Vectored interrupt + - Interrupt levels selectable by software +*/ + +/* Timer Preload Register TIM0PRELOAD + The Timer Preload Register TIM0PRELOAD contains the preset value which can be loaded into the counter circuit. The default + value of this register after reset is $00. The TIM0PRELOAD register can be read at any time but must not be altered if the + timer is running. + [7:0] The Timer Preload register contains the 8 bit value that is loaded into the counter if the + Autopreload option in the TIM0CTL register is selected and the counter reaches the value zero. + Also, if a write access to the TIM0COUNT register is performed, the counter is loaded with the value + stored in the Timer Preload Register. +*/ +void fga002_device::do_fga002reg_tim0preload_w(UINT8 data) +{ + LOG(("%s(%02x)\n", FUNCNAME, data)); + m_fga002[FGA_TIM0PRELOAD] = data; +} + +UINT8 fga002_device::do_fga002reg_tim0preload_r() +{ + LOG(("%s() %02x\n", FUNCNAME, m_fga002[FGA_TIM0PRELOAD])); + return m_fga002[FGA_TIM0PRELOAD]; +} + +/* Timer Control Register TIM0CTL + In the Timer Control Register TIM0CTL the operating mode and the clock source of the timer can be selected. The Timer + Control Register is grouped into two major fields. Bits 7-4 define the operating mode of the timer and the sysfail option. + Bits 3-0 select the source clock applied to the timer. The TIM0CTL register is cleared to $00 after any reset operation. + [7] Zerostop This bit selects whether the counter stops when reaching zero count or continues counting down. The value the + counter will decrement to next depends on the setting of bit 6 of this register, which is the Autopreload bit. + 1 = The counter continues counting down. + 0 = The counter stops on zero count. + [6] Autopreload This bit selects whether the counter rolls over from $00 to the value $FF and continues counting down or is + preset by the contents of the timer preload register after reaching the zero count. The Autopreload option may be + ignored if the counter is programmed to stop on zero count. + 1 The Autopreload option is enabled. When the counter has passed from $01 to $00, the value stored in the Preload + register will be transferred to the counter on the first clock edge following the zero count clock. After + that transfer the counter continues decrementing from the new value. + 0 The Autopreload option is disabled. After the counter has reached zero it will roll over to the value $FF and + continue counting down. + [5] Sysfail This bit enables/disables the sysfail generation by the timer. If this option is enabled, the SFAILO output pin of the FGA-002 + gate array will be asserted low when the timer triggers the timer interrupt. The sysfail signal is negated when the timer + interrupt is cleared. 1 = enabled 0 = disabled + [4] Start/Stop: This bit controls the timer start and stop operation. 1 = start 0 = stop + [3:0] Clock select This bitfield provides selection of the source clock for timer operation. + 3..0 source clock period + 0000 1 microsecond + 0001 2 microseconds + 0010 4 microseconds + 0011 8 microseconds + 0100 16 microseconds + 0101 32 microseconds + 0110 64 microseconds + 0111 128 microseconds + 1000 256 microseconds + 1001 512 microseconds + 1010 2 milliseconds + 1011 8 milliseconds + 1100 32 milliseconds + 1101 125 milliseconds + 1110 500 milliseconds + 1111 2 seconds +*/ + +void fga002_device::do_fga002reg_tim0ctl_w(UINT8 data) +{ + LOG(("%s(%02x)\n", FUNCNAME, data)); + if ((data & REG_TIM0CTL_START_STOP) != (m_fga002[FGA_TIM0CTL] & REG_TIM0CTL_START_STOP)) + { + if ((data & REG_TIM0CTL_START_STOP) == 0) + fga_timer->adjust(attotime::never, TIMER_ID_FGA, attotime::never); + else + { + switch (data & REG_TIM0CTL_CLK_MSK) + { + case REG_TIM0CTL_CLK_1_MIC: fga_timer->adjust(attotime::from_usec(1), TIMER_ID_FGA, attotime::from_usec(1)); break; + case REG_TIM0CTL_CLK_2_MIC: fga_timer->adjust(attotime::from_usec(2), TIMER_ID_FGA, attotime::from_usec(2)); break; + case REG_TIM0CTL_CLK_4_MIC: fga_timer->adjust(attotime::from_usec(4), TIMER_ID_FGA, attotime::from_usec(4)); break; + case REG_TIM0CTL_CLK_8_MIC: fga_timer->adjust(attotime::from_usec(8), TIMER_ID_FGA, attotime::from_usec(8)); break; + case REG_TIM0CTL_CLK_16_MIC: fga_timer->adjust(attotime::from_usec(16), TIMER_ID_FGA, attotime::from_usec(16)); break; + case REG_TIM0CTL_CLK_32_MIC: fga_timer->adjust(attotime::from_usec(32), TIMER_ID_FGA, attotime::from_usec(32)); break; + case REG_TIM0CTL_CLK_64_MIC: fga_timer->adjust(attotime::from_usec(64), TIMER_ID_FGA, attotime::from_usec(64)); break; + case REG_TIM0CTL_CLK_128_MIC: fga_timer->adjust(attotime::from_usec(128), TIMER_ID_FGA, attotime::from_usec(128)); break; + case REG_TIM0CTL_CLK_256_MIC: fga_timer->adjust(attotime::from_usec(256), TIMER_ID_FGA, attotime::from_usec(256)); break; + case REG_TIM0CTL_CLK_512_MIC: fga_timer->adjust(attotime::from_usec(512), TIMER_ID_FGA, attotime::from_usec(512)); break; + case REG_TIM0CTL_CLK_2_MIL: fga_timer->adjust(attotime::from_msec(2), TIMER_ID_FGA, attotime::from_msec(2)); break; + case REG_TIM0CTL_CLK_8_MIL: fga_timer->adjust(attotime::from_msec(8), TIMER_ID_FGA, attotime::from_msec(8)); break; + case REG_TIM0CTL_CLK_32_MIL: fga_timer->adjust(attotime::from_msec(32), TIMER_ID_FGA, attotime::from_msec(32)); break; + case REG_TIM0CTL_CLK_125_MIL: fga_timer->adjust(attotime::from_msec(125), TIMER_ID_FGA, attotime::from_msec(125)); break; + case REG_TIM0CTL_CLK_500_MIL: fga_timer->adjust(attotime::from_msec(500), TIMER_ID_FGA, attotime::from_msec(500)); break; + case REG_TIM0CTL_CLK_2_SEC: fga_timer->adjust(attotime::from_seconds(2), TIMER_ID_FGA, attotime::from_seconds(2)); break; + default: logerror("REG_TIM0CTL programmer error, please report\n"); break; // Should never happen + } + } + } + // TODO: Support SYSFAIL flag on interrupt + m_fga002[FGA_TIM0CTL] = data; +} + +UINT8 fga002_device::do_fga002reg_tim0ctl_r() +{ + LOG(("%s() %02x\n", FUNCNAME, m_fga002[FGA_TIM0CTL])); + return m_fga002[FGA_TIM0CTL]; +} + +/* Timer Count Register TIM0COUNT + The Timer Count Register TIM0COUNT contains the current value of the timer/counter. A write access to this register will + load the counter with the value stored in the Timer Preload Register. The written data will be ignored. + It is permitted to perform read/write accesses to the Timer Count Register when the timer is running. + The Timer Count Register is initialized to the value $FF after reset. + [7:0] Timer Count Value +*/ +void fga002_device::do_fga002reg_tim0count_w(UINT8 data) +{ + LOG(("%s(%02x)\n", FUNCNAME, data)); + m_tim0count = m_fga002[FGA_TIM0PRELOAD]; +} + +UINT8 fga002_device::do_fga002reg_tim0count_r() +{ + LOG(("%s() %02x\n", FUNCNAME, m_tim0count)); + return m_tim0count; +} + +/* Timer Interrupt Control Register ICRTIM0 + Timer Interrupt Control is performed by the Timer Interrupt Control Register ICRTIM0 which enables/disables the interrupt + and selects the interrupt level. + [3] IRQ enable, 1 = timer interrupt channel enabled, 0 = disabled + [2:0] IRQ level 000 = interrupt disabled 001-111 = Level 1 to 7 interrupt +*/ +void fga002_device::do_fga002reg_icrtim0_w(UINT8 data) +{ + LOG(("%s(%02x)\n", FUNCNAME, data)); + m_fga002[FGA_ICRTIM0] = data; +} + +UINT8 fga002_device::do_fga002reg_icrtim0_r() +{ + LOG(("%s() %02x\n", FUNCNAME, m_fga002[FGA_ICRTIM0])); + return m_fga002[FGA_ICRTIM0]; +} + +/* Timer Interrupt Status Register ISTIM0 + ISTIM0 displays a pending timer interrupt. This bit is always readable and indicates 0 if the timer interrupt has been triggered. A write access to the + ISTIM0 register clears the timer interrupt. The data written to this register will be ignored. + [7] The IRQ Status register bit displays if a timer interrupt request is pending. 1 = no interrupt is pending. 0 = interrupt is pending + [6:0] not used +*/ +void fga002_device::do_fga002reg_istim0_w(UINT8 data) +{ + LOG(("%s(%02x)\n", FUNCNAME, data)); + m_fga002[FGA_ISTIM0] &= ~REG_ISTIM0_TIM_INT; // Clear timer interrupt status +} + +UINT8 fga002_device::do_fga002reg_istim0_r() +{ + LOG(("%s() %02x\n", FUNCNAME, m_fga002[FGA_ISTIM0])); + return m_fga002[FGA_ISTIM0]; +} + + +WRITE8_MEMBER (fga002_device::write){ + LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data)); + switch(offset) + { + case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break; + case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break; + case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break; + case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break; + case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break; + case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break; + case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break; + case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break; + case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break; + case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break; + case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break; + case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break; + case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break; + case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break; + case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break; + case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break; + case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break; + case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break; + case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break; + case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break; + case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break; + case FGA_ICRTIM0 : do_fga002reg_icrtim0_w(data); break; + case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break; + case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break; + case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break; + case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break; + case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break; + case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break; + case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break; + case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break; + case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break; + case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break; + case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break; + case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break; + case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break; + case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break; + case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break; + case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break; + case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break; + case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break; + case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break; + case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break; + case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break; + case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break; + case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break; + case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break; + case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break; + case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break; + case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break; + case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break; + case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break; + case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break; + case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break; + case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break; + case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break; + case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break; + case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break; + case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break; + case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break; + case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break; + case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break; + case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break; + case FGA_TIM0PRELOAD : do_fga002reg_tim0preload_w(data); break; + case FGA_TIM0CTL : do_fga002reg_tim0ctl_w(data); break; + case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break; + case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break; + case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break; + case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break; + case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break; + case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break; + case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break; + case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break; + case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break; + case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break; + case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break; + case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break; + case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break; + case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break; + case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break; + case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break; + case FGA_ISTIM0 : do_fga002reg_istim0_w(data); break; + case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break; + case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break; + case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break; + case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break; + case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break; + case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break; + case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break; + case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break; + case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break; + case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break; + case FGA_TIM0COUNT : do_fga002reg_tim0count_w(data); break; + default: + LOG(("Unsupported register %04x\n", offset)); + } +} + +READ8_MEMBER (fga002_device::read){ + UINT8 ret = 0; + + LOG(("%s[%04x] ", FUNCNAME, offset)); + switch(offset) + { + case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break; + case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break; + case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break; + case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break; + case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break; + case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break; + case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break; + case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break; + case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break; + case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break; + case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break; + case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break; + case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break; + case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break; + case FGA_ICRTIM0 : ret = do_fga002reg_icrtim0_r(); break; + case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break; + case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break; + case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break; + case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break; + case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break; + case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break; + case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break; + case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break; + case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break; + case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break; + case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break; + case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break; + case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break; + case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break; + case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break; + case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break; + case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break; + case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break; + case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break; + case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break; + case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break; + case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break; + case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break; + case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break; + case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break; + case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break; + case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break; + case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break; + case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break; + case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break; + case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break; + case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break; + case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break; + case FGA_TIM0PRELOAD : ret = do_fga002reg_tim0preload_r(); break; + case FGA_TIM0CTL : ret = do_fga002reg_tim0ctl_r(); break; + case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break; + case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break; + case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break; + case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break; + case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break; + case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break; + case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break; + case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break; + case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break; + case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break; + case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break; + case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break; + case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break; + case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break; + case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break; + case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break; + case FGA_ISTIM0 : ret = do_fga002reg_istim0_r(); break; + case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break; + case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break; + case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break; + case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break; + case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break; + case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break; + case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break; + case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break; + case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break; + case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break; + case FGA_TIM0COUNT : ret = do_fga002reg_tim0count_r(); break; + default: + LOG(("Unsupported register %04x\n", offset)); + } + return ret; +} diff --git a/src/devices/machine/fga002.h b/src/devices/machine/fga002.h new file mode 100644 index 00000000000..80401da5b84 --- /dev/null +++ b/src/devices/machine/fga002.h @@ -0,0 +1,181 @@ +// license:BSD-3-Clause +// copyright-holders:Joakim Larsson Edstrom +#ifndef __FGA002_H__ +#define __FGA002_H__ + +#include "emu.h" + +#define MCFG_FGA002_ADD(_tag, _clock) MCFG_DEVICE_ADD(_tag, FGA002, _clock) + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +// ======================> fga002_device + +class fga002_device : public device_t +{ + public: + // construction/destruction + fga002_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source); + fga002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + DECLARE_WRITE8_MEMBER (write); + DECLARE_READ8_MEMBER (read); + protected: + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr) override; + private: + UINT8 m_tim0count; + UINT8 m_fga002[0x500]; + + /* Timer functions */ + UINT8 do_fga002reg_tim0preload_r(); + void do_fga002reg_tim0preload_w(UINT8 data); + UINT8 do_fga002reg_tim0ctl_r(); + void do_fga002reg_tim0ctl_w(UINT8 data); + UINT8 do_fga002reg_tim0count_r(); + void do_fga002reg_tim0count_w(UINT8 data); + UINT8 do_fga002reg_icrtim0_r(); + void do_fga002reg_icrtim0_w(UINT8 data); + UINT8 do_fga002reg_istim0_r(); + void do_fga002reg_istim0_w(UINT8 data); + emu_timer *fga_timer; + enum + { + TIMER_ID_FGA + }; + enum { + REG_TIM0CTL_ZERO_STOP = 0x80, + REG_TIM0CTL_AUTOPRELOAD = 0x40, + REG_TIM0CTL_SYSFAIL = 0x20, + REG_TIM0CTL_START_STOP = 0x10, + REG_TIM0CTL_CLK_MSK = 0x0f, + REG_TIM0CTL_CLK_1_MIC = 0x00, + REG_TIM0CTL_CLK_2_MIC = 0x01, + REG_TIM0CTL_CLK_4_MIC = 0x02, + REG_TIM0CTL_CLK_8_MIC = 0x03, + REG_TIM0CTL_CLK_16_MIC = 0x04, + REG_TIM0CTL_CLK_32_MIC = 0x05, + REG_TIM0CTL_CLK_64_MIC = 0x06, + REG_TIM0CTL_CLK_128_MIC = 0x07, + REG_TIM0CTL_CLK_256_MIC = 0x08, + REG_TIM0CTL_CLK_512_MIC = 0x09, + REG_TIM0CTL_CLK_2_MIL = 0x0a, + REG_TIM0CTL_CLK_8_MIL = 0x0b, + REG_TIM0CTL_CLK_32_MIL = 0x0c, + REG_TIM0CTL_CLK_125_MIL = 0x0d, + REG_TIM0CTL_CLK_500_MIL = 0x0e, + REG_TIM0CTL_CLK_2_SEC = 0x0f, + }; + enum { + REG_ISTIM0_TIM_INT = 0x80, + }; + + /* Register offsets */ + enum { + FGA_ICRMBOX0 = 0x0000, + FGA_ICRMBOX1 = 0x0004, + FGA_ICRMBOX2 = 0x0008, + FGA_ICRMBOX3 = 0x000c, + FGA_ICRMBOX4 = 0x0010, + FGA_ICRMBOX5 = 0x0014, + FGA_ICRMBOX6 = 0x0018, + FGA_ICRMBOX7 = 0x001C, + FGA_VMEPAGE = 0x0200, + FGA_ICRVME1 = 0x0204, + FGA_ICRVME2 = 0x0208, + FGA_ICRVME3 = 0x020c, + FGA_ICRVME4 = 0x0210, + FGA_ICRVME5 = 0x0214, + FGA_ICRVME6 = 0x0218, + FGA_ICRVME7 = 0x021c, + FGA_ICRTIM0 = 0x0220, + FGA_ICRDMANORM = 0x0230, + FGA_ICRDMAERR = 0x0234, + FGA_CTL1 = 0x0238, + FGA_CTL2 = 0x023c, + FGA_ICRFMB0REF = 0x0240, + FGA_ICRFMB1REF = 0x0244, + FGA_ICRFMB0MES = 0x0248, + FGA_ICRFMB1MES = 0x024c, + FGA_CTL3 = 0x0250, + FGA_CTL4 = 0x0254, + FGA_ICRPARITY = 0x0258, + FGA_AUXPINCTL = 0x0260, + FGA_CTL5 = 0x0264, + FGA_AUXFIFWEX = 0x0268, + FGA_AUXFIFREX = 0x026c, + FGA_CTL6 = 0x0270, + FGA_CTL7 = 0x0274, + FGA_CTL8 = 0x0278, + FGA_CTL9 = 0x027c, + FGA_ICRABORT = 0x0280, + FGA_ICRACFAIL = 0x0284, + FGA_ICRSYSFAIL = 0x0288, + FGA_ICRLOCAL0 = 0x028c, + FGA_ICRLOCAL1 = 0x0290, + FGA_ICRLOCAL2 = 0x0294, + FGA_ICRLOCAL3 = 0x0298, + FGA_ICRLOCAL4 = 0x029c, + FGA_ICRLOCAL5 = 0x02a0, + FGA_ICRLOCAL6 = 0x02a4, + FGA_ICRLOCAL7 = 0x02a8, + FGA_ENAMCODE = 0x02b4, + FGA_CTL10 = 0x02c0, + FGA_CTL11 = 0x02c4, + FGA_MAINUM = 0x02c8, + FGA_MAINUU = 0x02cc, + FGA_BOTTOMPAGEU = 0x02d0, + FGA_BOTTOMPAGEL = 0x02d4, + FGA_TOPPAGEU = 0x02d8, + FGA_TOPPAGEL = 0x02dc, + FGA_MYVMEPAGE = 0x02fc, + FGA_TIM0PRELOAD = 0x0300, + FGA_TIM0CTL = 0x0310, + FGA_DMASRCATT = 0x0320, + FGA_DMADSTATT = 0x0324, + FGA_DMA_GENERAL = 0x0328, + FGA_CTL12 = 0x032c, + FGA_LIOTIMING = 0x0330, + FGA_LOCALIACK = 0x0334, + FGA_FMBCTL = 0x0338, + FGA_FMBAREA = 0x033c, + FGA_AUXSRCSTART = 0x0340, + FGA_AUXDSTSTART = 0x0344, + FGA_AUXSRCTERM = 0x0348, + FGA_AUXDSTTERM = 0x034c, + FGA_CTL13 = 0x0350, + FGA_CTL14 = 0x0354, + FGA_CTL15 = 0x0358, + FGA_CTL16 = 0x035c, + FGA_SPECIALENA = 0x0424, + FGA_ISTIM0 = 0x04a0, + FGA_ISDMANORM = 0x04b0, + FGA_ISDMAERR = 0x04b4, + FGA_ISFMB0REF = 0x04b8, + FGA_ISFMB1REF = 0x04bc, + FGA_ISPARITY = 0x04c0, + FGA_DMARUNCTL = 0x04c4, + FGA_ISABORT = 0x04c8, + FGA_ISACFAIL = 0x04cc, + FGA_ISFMB0MES = 0x04e0, + FGA_ISFMB1MES = 0x04e4, + FGA_ISSYSFAIL = 0x04d0, + FGA_ABORTPIN = 0x04d4, + FGA_RSVMECALL = 0x04f0, + FGA_RSKEYRES = 0x04f4, + FGA_RSCPUCALL = 0x04f8, + FGA_RSLOCSW = 0x04fc, + FGA_TIM0COUNT = 0x0c00, + }; + +}; + + +// device type definition +extern const device_type FGA002; +#endif // __FGA002_H__ + From 998c1358b4c2f143cb8ff424d137f6cbc81d9d09 Mon Sep 17 00:00:00 2001 From: Joakim Larsson Edstrom Date: Wed, 6 Jul 2016 20:48:33 +0200 Subject: [PATCH 2/4] Added support for the 24 bit timer --- src/devices/machine/68230pit.cpp | 1 + src/devices/machine/68230pit.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/devices/machine/68230pit.cpp b/src/devices/machine/68230pit.cpp index 7398543dd52..3354738f954 100644 --- a/src/devices/machine/68230pit.cpp +++ b/src/devices/machine/68230pit.cpp @@ -433,6 +433,7 @@ void pit68230_device::wr_pitreg_tcr(UINT8 data) } else { + pit_timer->adjust(attotime::never, TIMER_ID_PIT, attotime::never); m_tcr = tout + tiack + irq + sqr; // remove this when the variables are used for the different modes!! Just here to to avoid warnings } } diff --git a/src/devices/machine/68230pit.h b/src/devices/machine/68230pit.h index ae71b0ba1ee..0c304bd1970 100644 --- a/src/devices/machine/68230pit.h +++ b/src/devices/machine/68230pit.h @@ -197,7 +197,7 @@ protected: virtual void device_start () override; virtual void device_reset () override; virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr) override; - // virtual void execute_run () override; + int m_icount; devcb_write8 m_pa_out_cb; From d9b44f49361984647bcf7cb1d4cfcafef439fdb9 Mon Sep 17 00:00:00 2001 From: Joakim Larsson Edstrom Date: Wed, 6 Jul 2016 20:50:16 +0200 Subject: [PATCH 3/4] Added support for the 16-bit timer and for clock output mode callbacks on RTXC and TRXC pins --- src/devices/machine/scnxx562.cpp | 331 +++++++++++++++++++++++++------ src/devices/machine/scnxx562.h | 44 +++- 2 files changed, 308 insertions(+), 67 deletions(-) diff --git a/src/devices/machine/scnxx562.cpp b/src/devices/machine/scnxx562.cpp index ca217d61d1d..cbd3f67a861 100644 --- a/src/devices/machine/scnxx562.cpp +++ b/src/devices/machine/scnxx562.cpp @@ -150,10 +150,14 @@ duscc_device::duscc_device(const machine_config &mconfig, device_type type, cons m_out_dtra_cb(*this), m_out_rtsa_cb(*this), m_out_synca_cb(*this), + m_out_rtxca_cb(*this), + m_out_trxca_cb(*this), m_out_txdb_cb(*this), m_out_dtrb_cb(*this), m_out_rtsb_cb(*this), m_out_syncb_cb(*this), + m_out_rtxcb_cb(*this), + m_out_trxcb_cb(*this), m_out_int_cb(*this), m_variant(variant), m_gsr(0), @@ -174,10 +178,14 @@ duscc_device::duscc_device(const machine_config &mconfig, const char *tag, devic m_out_dtra_cb(*this), m_out_rtsa_cb(*this), m_out_synca_cb(*this), + m_out_rtxca_cb(*this), + m_out_trxca_cb(*this), m_out_txdb_cb(*this), m_out_dtrb_cb(*this), m_out_rtsb_cb(*this), m_out_syncb_cb(*this), + m_out_rtxcb_cb(*this), + m_out_trxcb_cb(*this), m_out_int_cb(*this), m_variant(TYPE_DUSCC), m_gsr(0), @@ -208,16 +216,22 @@ duscc68C562_device::duscc68C562_device(const machine_config &mconfig, const char void duscc_device::device_start() { LOG(("%s\n", FUNCNAME)); + // resolve callbacks m_out_txda_cb.resolve_safe(); m_out_dtra_cb.resolve_safe(); m_out_rtsa_cb.resolve_safe(); m_out_synca_cb.resolve_safe(); + m_out_rtxca_cb.resolve_safe(); + m_out_trxca_cb.resolve_safe(); m_out_txdb_cb.resolve_safe(); m_out_dtrb_cb.resolve_safe(); m_out_rtsb_cb.resolve_safe(); m_out_syncb_cb.resolve_safe(); + m_out_rtxcb_cb.resolve_safe(); + m_out_trxcb_cb.resolve_safe(); + m_out_int_cb.resolve_safe(); // state saving - stuff with runtime values @@ -531,6 +545,10 @@ duscc_channel::duscc_channel(const machine_config &mconfig, const char *tag, dev = m_cid = /*m_ivr = m_icr = m_sea = m_ivrm = */ m_mrr = m_ier1 = m_ier2 = m_ier3 = m_trcr = m_rflr = m_ftlr = m_trmsr = m_telr = 0; + // Reset all states + m_rtxc = 0; + m_trxc = 0; + for (auto & elem : m_rx_data_fifo) elem = 0; for (auto & elem : m_rx_error_fifo) @@ -559,6 +577,11 @@ void duscc_channel::device_start() m_cid = (m_uart->m_variant & SET_CMOS) ? 0x7f : 0xff; // TODO: support CMOS rev A = 0xbf + // Timers + duscc_timer = timer_alloc(TIMER_ID); + rtxc_timer = timer_alloc(TIMER_ID_RTXC); + trxc_timer = timer_alloc(TIMER_ID_TRXC); + // state saving save_item(NAME(m_cmr1)); save_item(NAME(m_cmr2)); @@ -600,6 +623,8 @@ void duscc_channel::device_start() save_item(NAME(m_ftlr)); save_item(NAME(m_trmsr)); save_item(NAME(m_telr)); + save_item(NAME(m_rtxc)); + save_item(NAME(m_trxc)); save_item(NAME(m_rx_data_fifo)); save_item(NAME(m_rx_error_fifo)); save_item(NAME(m_rx_fifo_rp)); @@ -665,6 +690,9 @@ void duscc_channel::device_reset() m_ftlr =0x33; m_trmsr =0x00; m_telr =0x10; + m_rtxc =0x00; + m_trxc =0x00; + // reset external lines TODO: check relation to control bits and reset set_rts(1); @@ -681,10 +709,220 @@ void duscc_channel::device_reset() void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) { + switch(id) + { + case TIMER_ID: + if (m_ct-- == 0) // Zero detect + { + m_ictsr |= REG_ICTSR_ZERO_DET; // set zero detection bit + + // Generate interrupt? + if ( ( (m_ctcr & REG_CTCR_ZERO_DET_INT) == 1 ) && + ( (m_uart->m_icr & (m_index == duscc_device::CHANNEL_A ? duscc_device::REG_ICR_CHA : duscc_device::REG_ICR_CHB) ) != 0) ) + { + //trigger_interrupt(); + } + + // Preload or rollover? + if (( m_ctcr & REG_CTCR_ZERO_DET_CTL) == 0) + { + m_ct = m_ctpr; + } + else + { + m_ct = 0xffff; + } + + // Is Counter/Timer output on the RTxC pin? + if (( m_pcr & REG_PCR_RTXC_MASK) == REG_PCR_RTXC_CNTR_OUT) + { + if ((m_ctcr & REG_CTCR_TIM_OC) == 0) // Toggle? + { + m_rtxc = (~m_rtxc) & 1; + } + else // Pulse! + { + m_rtxc = 1; + rtxc_timer->adjust(attotime::from_hz(clock()), TIMER_ID_RTXC, attotime::from_hz(clock())); + } + if (m_index == duscc_device::CHANNEL_A) + m_uart->m_out_rtxca_cb(m_rtxc); + else + m_uart->m_out_rtxcb_cb(m_rtxc); + } + + // Is Counter/Timer output on the TRXC pin? + if (( m_pcr & REG_PCR_TRXC_MASK) == REG_PCR_TRXC_CNTR_OUT) + { + if ((m_ctcr & REG_CTCR_TIM_OC) == 0) // Toggle? + { + m_trxc = (~m_trxc) & 1; + } + else // Pulse! + { + m_trxc = 1; + trxc_timer->adjust(attotime::from_hz(clock()), TIMER_ID_TRXC, attotime::from_hz(clock())); + } + if (m_index == duscc_device::CHANNEL_A) + m_uart->m_out_trxca_cb(m_trxc); + else + m_uart->m_out_trxcb_cb(m_trxc); + } + } + else + { // clear zero detection bit + m_ictsr &= ~REG_ICTSR_ZERO_DET; + } + break; + case TIMER_ID_RTXC: // Terminate zero detection pulse + m_rtxc = 0; + rtxc_timer->adjust(attotime::never); + if (m_index == duscc_device::CHANNEL_A) + m_uart->m_out_rtxca_cb(m_rtxc); + else + m_uart->m_out_rtxcb_cb(m_rtxc); + break; + case TIMER_ID_TRXC: // Terminate zero detection pulse + m_trxc = 0; + trxc_timer->adjust(attotime::never); + if (m_index == duscc_device::CHANNEL_A) + m_uart->m_out_trxca_cb(m_trxc); + else + m_uart->m_out_trxcb_cb(m_trxc); + break; + default: + LOGR(("Unhandled Timer ID %d\n", id)); + break; + } // LOG(("%s %d\n", FUNCNAME, id)); device_serial_interface::device_timer(timer, id, param, ptr); } +/* The DUSCC 16 bit Timer + Counter/Timer Control and Value Registers + There are five registers in this set consisting of the following: + 1. Counterltimer control register (CTCRAlB). + 2. Counterltimer preset Highland Low registers (CTPRHAlB, CTPRLAlB). + 3. Counter/bmer (current value) High and Low registers (CTHAlB, CTLAlB) + The control register contains the operational information for the counterltimer. The preset registers contain the count which is + loaded into the counterltimer circuits. The third group contains the current value of the counterltimer as it operates. +*/ +/* Counter/Timer Control Register (CTCRA/CTCRB) + [7] Zero Detect Interrupt - This bit determines whether the assertion of the CIT ZERO COUNT status bit (ICTSR[6)) causes an + interrupt to be generated if set to 1 and the Master interrupt control bit (ICR[0:1]) is set + [6] Zero Detect Control - his bit determines the action of the counter upon reaching zero count + 0 - The counter/timer is preset to the value contained in the counterltimer preset registers (CTPRL, CTPRH) at the next clock edge. + 1 - The counterltimer continues counting without preset. The value at the next clock edge will be H'FFFF'. + [5] CounterlTimer Output Control - This bit selects the output waveform when the counterltimer is selected to be output on TRxC or RTxC. + 0 - The output toggles each time the CIT reaches zero count. The output is cleared to Low by either of the preset counterltimer commands. + 1 - The output is a single clock positive width pulse each time the CIT reaches zero count. (The duration of this pulse is one clock period.) + [4:3] Clock Select - This field selects whether the clock selected by [2:0J is prescaled prior to being applied to the input of the CIT. + 0 0 No prescaling. + 0 1 Divide clock by 16. + 1 0 Divide clock by 32. + 1 1 Divide clock by 64. + [2:0] Clock Source - This field selects the clock source for the counterltimer. + 000 RTxC pin. Pin must be programmed as input. + 001 TRxC pin. Pin must be programmed as input. + 010 Source is the crystal oscillator or system clock input divided by four. + 011 This selects a special mode of operation. In this mode the counter, after receiving the 'start CIT' command, delays the + start of counting until the RxD input goes Low. It continues counting until the RxD input goes High, then stops and sets + the CIT zero count status bit. The CPU can use the value in the CIT to determine the bit rate of the incoming data. + The clock is the crystal oscillator or system clock input divided by four. + 100 Source is the 32X BRG output selected by RTR[3:0J of own channel. + 101 Source is the 32X BRG output selected by TTR[3:0J of own channel. + 110 Source is the internal signal which loads received characters from the receive shift register into the receiver + FIFO. When operating in this mode, the FIFOed EOM status bit (RSR[7)) shall be set when the character which + causes the count to go to zero is loaded into the receive FIFO. + 111 Source is the internal signal which transfers characters from the data bus into the transmit FIFO. When operating in this + mode, and if the TEOM on zero count or done control bit (TPR[4)) is asserted, the FIFOed send EOM command will + be automatically asserted when the character which causes the count to go to zero is loaded into the transmit FIFO. +*/ +UINT8 duscc_channel::do_dusccreg_ctcr_r() +{ + LOG(("%s(%02x)\n", FUNCNAME, m_ctcr)); + return m_ctcr; +} + +void duscc_channel::do_dusccreg_ctcr_w(UINT8 data) +{ + LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data)); + m_ctcr = data; + return; +} + +/* Counterrrimer Preset High Register (CTPRHA, CTPRHB) + [7:0) MSB - This register contains the eight most significant bits of the value loaded into the counter/timer upon receipt of the load CIT + from preset regsiter command or when.the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated. + The minimum 16-bit counter/timer preset value is H'0002'. +*/ +UINT8 duscc_channel::do_dusccreg_ctprh_r() +{ + UINT8 ret = ((m_ctpr >> 8) & 0xff ); + LOG(("%s(%02x)\n", FUNCNAME, ret)); + + // return m_ctprh; + return ret; +} + +void duscc_channel::do_dusccreg_ctprh_w(UINT8 data) +{ + LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data)); + // m_ctprh = data; + m_ctpr &= ~0x0000ff00; + m_ctpr |= ((data << 8) & 0x0000ff00); + return; +} + +/* CounterfTimer Preset Low Register (CTPRLA, CTPRLB) + [7:0) lSB - This register contains the eight least significant bits of the value loaded into the counter/timer upon receipt of the load CIT + from preset register command or when the counter/timer reaches zero count and the zero detect control bit (CTCR[6]) is negated. + The minimum 16-bit counter/timer preset value is H'0002'. +*/ +UINT8 duscc_channel::do_dusccreg_ctprl_r() +{ + UINT8 ret = (m_ctpr & 0xff); + LOG(("%s(%02x)\n", FUNCNAME, ret)); + // return m_ctprl; + return ret; +} + +void duscc_channel::do_dusccreg_ctprl_w(UINT8 data) +{ + LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data)); + // m_ctprl = data; + m_ctpr &= ~0x000000ff; + m_ctpr |= (data & 0x000000ff); + return; +} + +/* Counter/Timer High Register (CTHA, CTHB) Read only + [7:0] MSB - A read of this 'register' provides the eight most significant bits of the current value of the counter/timer. it is + recommended that the CIT be stopped via a stop counter command before it is read in order to prevent errors which may occur due to + the read being performed while the CIT is changing. This count may be continued after the register is read. +*/ + +UINT8 duscc_channel::do_dusccreg_cth_r() +{ + UINT8 ret = ((m_ct >> 8) & 0xff ); + LOG(("%s(%02x)\n", FUNCNAME, ret)); + + return ret; +} + + +/* Counter/Timer Low Register (CTLA, CTLB) Read only + [7:0] lSB - A read of this 'register' provides the eight least significant bits of the current value of the counter/timer. It is + recommended that the CIT be stopped via a stop counter command before it is read, in order to prevent errors which may occur due to + the read being performed while the CIT is changing. This count may be continued after the register is read. +*/ +UINT8 duscc_channel::do_dusccreg_ctl_r() +{ + UINT8 ret = (m_ct & 0xff); + LOG(("%s(%02x)\n", FUNCNAME, ret)); + // return m_ctl; + return ret; +} //------------------------------------------------- // tra_callback - @@ -943,51 +1181,12 @@ UINT8 duscc_channel::do_dusccreg_rtr_r() return m_rtr; } -UINT8 duscc_channel::do_dusccreg_ctprh_r() -{ - UINT8 ret = ((m_ctpr >> 8) & 0xff ); - LOG(("%s(%02x)\n", FUNCNAME, ret)); - - // return m_ctprh; - return ret; -} - -UINT8 duscc_channel::do_dusccreg_ctprl_r() -{ - UINT8 ret = (m_ctpr & 0xff); - LOG(("%s(%02x)\n", FUNCNAME, ret)); - // return m_ctprl; - return ret; -} - -UINT8 duscc_channel::do_dusccreg_ctcr_r() -{ - LOG(("%s(%02x)\n", FUNCNAME, m_ctcr)); - return m_ctcr; -} - UINT8 duscc_channel::do_dusccreg_omr_r() { LOG(("%s(%02x)\n", FUNCNAME, m_omr)); return m_omr; } -UINT8 duscc_channel::do_dusccreg_cth_r() -{ - UINT8 ret = ((m_ct >> 8) & 0xff ); - LOG(("%s(%02x)\n", FUNCNAME, ret)); - - return ret; -} - -UINT8 duscc_channel::do_dusccreg_ctl_r() -{ - UINT8 ret = (m_ct & 0xff); - LOG(("%s(%02x)\n", FUNCNAME, ret)); - // return m_ctl; - return ret; -} - UINT8 duscc_channel::do_dusccreg_pcr_r() { LOG(("%s(%02x)\n", FUNCNAME, m_pcr)); @@ -1595,31 +1794,6 @@ void duscc_channel::do_dusccreg_rtr_w(UINT8 data) return; } -void duscc_channel::do_dusccreg_ctprh_w(UINT8 data) -{ - LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data)); - // m_ctprh = data; - m_ctpr &= ~0x0000ff00; - m_ctpr |= ((data << 8) & 0x0000ff00); - return; -} - -void duscc_channel::do_dusccreg_ctprl_w(UINT8 data) -{ - LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data)); - // m_ctprl = data; - m_ctpr &= ~0x000000ff; - m_ctpr |= (data & 0x000000ff); - return; -} - -void duscc_channel::do_dusccreg_ctcr_w(UINT8 data) -{ - LOG(("%s(%02x) - not supported yet\n", FUNCNAME, data)); - m_ctcr = data; - return; -} - /* Output and Miscellaneous Register (OMRA, OMRB) [7:5] Transmitted Residual Character Length - In BOP modes, this field determines the number of bits transmitted for the last character in the information field. This length applies to: @@ -1744,6 +1918,8 @@ void duscc_channel::do_dusccreg_pcr_w(UINT8 data) */ void duscc_channel::do_dusccreg_ccr_w(UINT8 data) { + int rate; + m_ccr = data; LOG(("%s\n", FUNCNAME)); switch(m_ccr) @@ -1810,6 +1986,33 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data) m_rcv = 0; m_uart->m_gsr &= ~(m_index == duscc_device::CHANNEL_A ? REG_GSR_CHAN_A_RXREADY : REG_GSR_CHAN_B_RXREADY); break; + + // COUNTER/TIMER COMMANDS + + /* Start. Starts the counteritimer and prescaler. */ + case REG_CCR_START_TIMER: LOG(("- Start Counter/Timer\n")); + rate = 100; // TODO: calculate correct rate + duscc_timer->adjust(attotime::from_hz(rate), TIMER_ID_RTXC, attotime::from_hz(rate)); + break; + + /* Stop. Stops the counter/timer and prescaler. Since the command may be asynchronous with the selected clock source, + the counter/timer and/or prescaler may count one or more additional cycles before stopping.. */ + case REG_CCR_STOP_TIMER: LOG(("- Stop Counter/Timer\n")); + duscc_timer->adjust(attotime::never); + break; + + /* Preset to FFFF. Presets the counter timer to H'FFFF' and the prescaler to its initial value. This command causes the + C/T output to go Low.*/ + case REG_CCR_PRST_FFFF: LOG(("- Preset 0xffff to Counter/Timer\n")); + m_ct = 0xffff; + break; + + /* Preset from CTPRH/CTPRL. Transfers the current value in the counter/timer preset registers to the counter/timer and + presets the prescaler to its initial value. This command causes the C/T output to go Low. */ + case REG_CCR_PRST_CTPR: LOG(("- Preset CTPR to Counter/Timer\n")); + m_ct = m_ctpr; + break; + default: LOG((" - command %02x not implemented yet\n", data)); } return; diff --git a/src/devices/machine/scnxx562.h b/src/devices/machine/scnxx562.h index 636122aa665..ee07df1b124 100644 --- a/src/devices/machine/scnxx562.h +++ b/src/devices/machine/scnxx562.h @@ -87,6 +87,12 @@ #define MCFG_DUSCC_OUT_SYNCA_CB(_devcb) \ devcb = &duscc_device::set_out_synca_callback(*device, DEVCB_##_devcb); +#define MCFG_DUSCC_OUT_TRXCA_CB(_devcb) \ + devcb = &duscc_device::set_out_trxca_callback(*device, DEVCB_##_devcb); + +#define MCFG_DUSCC_OUT_RTXCA_CB(_devcb) \ + devcb = &duscc_device::set_out_rtxca_callback(*device, DEVCB_##_devcb); + // Port B callbacks #define MCFG_DUSCC_OUT_TXDB_CB(_devcb) \ devcb = &duscc_device::set_out_txdb_callback(*device, DEVCB_##_devcb); @@ -100,7 +106,11 @@ #define MCFG_DUSCC_OUT_SYNCB_CB(_devcb) \ devcb = &duscc_device::set_out_syncb_callback(*device, DEVCB_##_devcb); +#define MCFG_DUSCC_OUT_TRXCB_CB(_devcb) \ + devcb = &duscc_device::set_out_trxcb_callback(*device, DEVCB_##_devcb); +#define MCFG_DUSCC_OUT_RTXCB_CB(_devcb) \ + devcb = &duscc_device::set_out_rtxcb_callback(*device, DEVCB_##_devcb); //************************************************************************** // TYPE DEFINITIONS @@ -280,7 +290,11 @@ protected: REG_CCR_DISABLE_TX = 0x03, REG_CCR_RESET_RX = 0x40, REG_CCR_ENABLE_RX = 0x42, - REG_CCR_DISABLE_RX = 0x43 + REG_CCR_DISABLE_RX = 0x43, + REG_CCR_START_TIMER = 0x80, + REG_CCR_STOP_TIMER = 0x81, + REG_CCR_PRST_FFFF = 0x82, + REG_CCR_PRST_CTPR = 0x83, }; enum @@ -406,6 +420,7 @@ protected: enum { + REG_ICTSR_ZERO_DET = 0x40, REG_ICTSR_DELTA_CTS = 0x10, REG_ICTSR_DCD = 0x08, REG_ICTSR_CTS = 0x04, @@ -472,10 +487,25 @@ protected: REG_TELR = 0x5f, }; + // Timers + emu_timer *duscc_timer; + emu_timer *rtxc_timer; + emu_timer *trxc_timer; + + UINT8 m_rtxc; + UINT8 m_trxc; + + enum { - TIMER_ID_BAUD, - TIMER_ID_XTAL, + REG_CTCR_ZERO_DET_INT = 0x80, + REG_CTCR_ZERO_DET_CTL = 0x40, + REG_CTCR_TIM_OC = 0x20, + }; + + enum + { + TIMER_ID, TIMER_ID_RTXC, TIMER_ID_TRXC }; @@ -581,11 +611,15 @@ public: template static devcb_base &set_out_dtra_callback(device_t &device, _Object object) { return downcast(device).m_out_dtra_cb.set_callback(object); } template static devcb_base &set_out_rtsa_callback(device_t &device, _Object object) { return downcast(device).m_out_rtsa_cb.set_callback(object); } template static devcb_base &set_out_synca_callback(device_t &device, _Object object) { return downcast(device).m_out_synca_cb.set_callback(object); } + template static devcb_base &set_out_rtxca_callback(device_t &device, _Object object) { return downcast(device).m_out_rtxca_cb.set_callback(object); } + template static devcb_base &set_out_trxca_callback(device_t &device, _Object object) { return downcast(device).m_out_trxca_cb.set_callback(object); } template static devcb_base &set_out_txdb_callback(device_t &device, _Object object) { return downcast(device).m_out_txdb_cb.set_callback(object); } template static devcb_base &set_out_dtrb_callback(device_t &device, _Object object) { return downcast(device).m_out_dtrb_cb.set_callback(object); } template static devcb_base &set_out_rtsb_callback(device_t &device, _Object object) { return downcast(device).m_out_rtsb_cb.set_callback(object); } template static devcb_base &set_out_syncb_callback(device_t &device, _Object object) { return downcast(device).m_out_syncb_cb.set_callback(object); } + template static devcb_base &set_out_rtxcb_callback(device_t &device, _Object object) { return downcast(device).m_out_rtxcb_cb.set_callback(object); } + template static devcb_base &set_out_trxcb_callback(device_t &device, _Object object) { return downcast(device).m_out_trxcb_cb.set_callback(object); } static void configure_channels(device_t &device, int rxa, int txa, int rxb, int txb) { @@ -674,11 +708,15 @@ protected: devcb_write_line m_out_dtra_cb; devcb_write_line m_out_rtsa_cb; devcb_write_line m_out_synca_cb; + devcb_write_line m_out_rtxca_cb; + devcb_write_line m_out_trxca_cb; devcb_write_line m_out_txdb_cb; devcb_write_line m_out_dtrb_cb; devcb_write_line m_out_rtsb_cb; devcb_write_line m_out_syncb_cb; + devcb_write_line m_out_rtxcb_cb; + devcb_write_line m_out_trxcb_cb; devcb_write_line m_out_int_cb; From e7fc2fe0db8e8313b963922279a58ee54819fc94 Mon Sep 17 00:00:00 2001 From: Joakim Larsson Edstrom Date: Wed, 6 Jul 2016 20:53:04 +0200 Subject: [PATCH 4/4] Splitted out FGA-002 as its own device, Added CPU-33 roms, Added CPU-30 board layout --- src/mame/drivers/fccpu30.cpp | 475 ++++++----------------------------- 1 file changed, 77 insertions(+), 398 deletions(-) diff --git a/src/mame/drivers/fccpu30.cpp b/src/mame/drivers/fccpu30.cpp index 37e293e5098..cfef6508309 100644 --- a/src/mame/drivers/fccpu30.cpp +++ b/src/mame/drivers/fccpu30.cpp @@ -19,52 +19,52 @@ * ||||--||_____________________________________________________________ * ||||--|| | * || || _ |__ - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || | |VME| - * || | | | - * || | |P1 | - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || |_| | - * || |___| - * || | - * || | - * || | - * || | - * || | - * || | - * || | - * || | - * || |___ - * || _| | - * || | | | - * || | | | - * || | | | - * || | | | - * || | |VME| - * || | | | - * || | |P2 | - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || | | | - * || |_| | - * || |___| - * || || + - * ||||--|| | + * || +----------------+ | | | + * RST O=== | | | | | + * || | | | | | + * ABT O=== | FGA-002 | | | | + RUN/HLT C| GREEN/RED +------------+ | | | | | + BUS MST C| GREEN/unlit |System flash| | | | | | + * || +------------+ | | | |VME| + * rot [O SW4 +------------+ +----------------+ | | | + * swtshs|| |System Flash| | |P1 | + * [O SW3 +------------+ +----------+ | | | + * || +------------+ | | | | | + * || |System Flash| | 68030 | | | | + * | || +------------+ | | | | | + * |--| +------------+ | | | | | + * AUI | | |System Flash| +----------+ | | | + * eth| | +------------+ |_| | + * | | +----------+ |___| + * | | +-----+ | | | + * |--| |SIA | | 68882 | | + * | || |7992 | | | | + * || +-----+ J28 | | | + * || +------+ +----------+ | + * || | Opt | | + * ||| | Boot | | + * +---+ | PROM | | + * Ser | = +----------+ +------+ +--------+ |___ + * #3 | = | LANCE | +------+ | SCSI | _ _| | + * | = | 7970 | | Def | | 87034 | | | | + * +---+ | | | Boot | | | | | | + * ||| | | | PROM | +--------+ | | | + * || +----------+ +------+ | | | + * ||| +----+ J36 +------+ | |VME| + * +---+ |NV- | | FDC | | | | + * Ser | = | RAM| |37C65C| | |P2 | + * #2 | = | | +------+ | | | + * | = +----+ | 5 row | + * +---+ +--------+ +--------+ | conn- | + * ||| +-----+ | DUSCC1 | | PIT1 | | ector| + * || | OPT | | 68562 | | 68230 | | | | + * ||| |NVRAM| | | | | | | | + * +---+ | | +--------+ +--------+ | | | + * Ser | = | | ____ +--------+ +--------+ | | | + * #1 | = | | / \ | DUSCC2 | | PIT2 | |_ _| | + * | = | | BATTERY | 68562 | | 68230 | |___| + * || +---+ +-----+ \____/ | | | | + + * ||||--|| +--------+ +--------+ | * ||||--||--------------------------------------------------------------+ * || * @@ -160,6 +160,7 @@ #include "cpu/m68000/m68000.h" #include "machine/scnxx562.h" #include "machine/68230pit.h" +#include "machine/fga002.h" #include "machine/nvram.h" #include "bus/rs232/rs232.h" #include "machine/clock.h" @@ -189,14 +190,12 @@ fccpu30_state(const machine_config &mconfig, device_type type, const char *tag) , m_dusccterm(*this, "duscc") , m_pit1 (*this, "pit1") , m_pit2 (*this, "pit2") + , m_fga002 (*this, "fga002") { } DECLARE_READ32_MEMBER (bootvect_r); DECLARE_WRITE32_MEMBER (bootvect_w); - /* FGA-002 - Force Gate Array */ - DECLARE_READ8_MEMBER (fga8_r); - DECLARE_WRITE8_MEMBER (fga8_w); /* Rotary switch PIT input */ DECLARE_READ8_MEMBER (rotary_rd); @@ -218,12 +217,11 @@ private: required_device m_pit1; required_device m_pit2; + required_device m_fga002; + // Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses UINT32 *m_sysrom; UINT32 m_sysram[2]; - - // FGA-002 - UINT8 m_fga002[0x500]; }; static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state) @@ -236,7 +234,7 @@ static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state) AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit1", pit68230_device, read, write, 0xffffffff) AM_RANGE (0xff800e00, 0xff800fff) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xffffffff) AM_RANGE (0xffc00000, 0xffcfffff) AM_RAM AM_SHARE ("nvram") /* On-board SRAM with battery backup (nvram) */ - AM_RANGE (0xffd00000, 0xffd004ff) AM_READWRITE8(fga8_r, fga8_w, 0xffffffff) /* FGA-002 Force Gate Array */ + AM_RANGE (0xffd00000, 0xffdfffff) AM_DEVREADWRITE8("fga002", fga002_device, read, write, 0xffffffff) /* FGA-002 Force Gate Array */ AM_RANGE (0xffe00000, 0xffefffff) AM_ROM AM_REGION("roms", 0x800000) //AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */ @@ -247,100 +245,6 @@ ADDRESS_MAP_END static INPUT_PORTS_START (fccpu30) INPUT_PORTS_END -#define FGA_ICRMBOX0 0x0000 -#define FGA_ICRMBOX1 0x0004 -#define FGA_ICRMBOX2 0x0008 -#define FGA_ICRMBOX3 0x000c -#define FGA_ICRMBOX4 0x0010 -#define FGA_ICRMBOX5 0x0014 -#define FGA_ICRMBOX6 0x0018 -#define FGA_ICRMBOX7 0x001C -#define FGA_VMEPAGE 0x0200 -#define FGA_ICRVME1 0x0204 -#define FGA_ICRVME2 0x0208 -#define FGA_ICRVME3 0x020c -#define FGA_ICRVME4 0x0210 -#define FGA_ICRVME5 0x0214 -#define FGA_ICRVME6 0x0218 -#define FGA_ICRVME7 0x021c -#define FGA_ICRTIM0 0x0220 -#define FGA_ICRDMANORM 0x0230 -#define FGA_ICRDMAERR 0x0234 -#define FGA_CTL1 0x0238 -#define FGA_CTL2 0x023c -#define FGA_ICRFMB0REF 0x0240 -#define FGA_ICRFMB1REF 0x0244 -#define FGA_ICRFMB0MES 0x0248 -#define FGA_ICRFMB1MES 0x024c -#define FGA_CTL3 0x0250 -#define FGA_CTL4 0x0254 -#define FGA_ICRPARITY 0x0258 -#define FGA_AUXPINCTL 0x0260 -#define FGA_CTL5 0x0264 -#define FGA_AUXFIFWEX 0x0268 -#define FGA_AUXFIFREX 0x026c -#define FGA_CTL6 0x0270 -#define FGA_CTL7 0x0274 -#define FGA_CTL8 0x0278 -#define FGA_CTL9 0x027c -#define FGA_ICRABORT 0x0280 -#define FGA_ICRACFAIL 0x0284 -#define FGA_ICRSYSFAIL 0x0288 -#define FGA_ICRLOCAL0 0x028c -#define FGA_ICRLOCAL1 0x0290 -#define FGA_ICRLOCAL2 0x0294 -#define FGA_ICRLOCAL3 0x0298 -#define FGA_ICRLOCAL4 0x029c -#define FGA_ICRLOCAL5 0x02a0 -#define FGA_ICRLOCAL6 0x02a4 -#define FGA_ICRLOCAL7 0x02a8 -#define FGA_ENAMCODE 0x02b4 -#define FGA_CTL10 0x02c0 -#define FGA_CTL11 0x02c4 -#define FGA_MAINUM 0x02c8 -#define FGA_MAINUU 0x02cc -#define FGA_BOTTOMPAGEU 0x02d0 -#define FGA_BOTTOMPAGEL 0x02d4 -#define FGA_TOPPAGEU 0x02d8 -#define FGA_TOPPAGEL 0x02dc -#define FGA_MYVMEPAGE 0x02fc -#define FGA_TIM0PRELOAD 0x0300 -#define FGA_TIM0CTL 0x0310 -#define FGA_DMASRCATT 0x0320 -#define FGA_DMADSTATT 0x0324 -#define FGA_DMA_GENERAL 0x0328 -#define FGA_CTL12 0x032c -#define FGA_LIOTIMING 0x0330 -#define FGA_LOCALIACK 0x0334 -#define FGA_FMBCTL 0x0338 -#define FGA_FMBAREA 0x033c -#define FGA_AUXSRCSTART 0x0340 -#define FGA_AUXDSTSTART 0x0344 -#define FGA_AUXSRCTERM 0x0348 -#define FGA_AUXDSTTERM 0x034c -#define FGA_CTL13 0x0350 -#define FGA_CTL14 0x0354 -#define FGA_CTL15 0x0358 -#define FGA_CTL16 0x035c -#define FGA_SPECIALENA 0x0424 -#define FGA_ISTIM0 0x04a0 -#define FGA_ISDMANORM 0x04b0 -#define FGA_ISDMAERR 0x04b4 -#define FGA_ISFMB0REF 0x04b8 -#define FGA_ISFMB1REF 0x04bc -#define FGA_ISPARITY 0x04c0 -#define FGA_DMARUNCTL 0x04c4 -#define FGA_ISABORT 0x04c8 -#define FGA_ISACFAIL 0x04cc -#define FGA_ISFMB0MES 0x04e0 -#define FGA_ISFMB1MES 0x04e4 -#define FGA_ISSYSFAIL 0x04d0 -#define FGA_ABORTPIN 0x04d4 -#define FGA_RSVMECALL 0x04f0 -#define FGA_RSKEYRES 0x04f4 -#define FGA_RSCPUCALL 0x04f8 -#define FGA_RSLOCSW 0x04fc - /* Start it up */ void fccpu30_state::machine_start () { @@ -348,7 +252,6 @@ void fccpu30_state::machine_start () save_pointer (NAME (m_sysrom), sizeof(m_sysrom)); save_pointer (NAME (m_sysram), sizeof(m_sysram)); - save_pointer (NAME (m_fga002), sizeof(m_fga002)); /* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */ m_sysrom = (UINT32*)(memregion ("roms")->base () + 0x800000); @@ -361,24 +264,6 @@ void fccpu30_state::machine_reset () /* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */ if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */ m_sysrom = (UINT32*)(memregion ("roms")->base () + 0x800000); - - /* Reset values for the FGA-002 */ - memset(&m_fga002[0], 0, sizeof(m_fga002)); - m_fga002[FGA_RSVMECALL] = 0x80; - m_fga002[FGA_RSKEYRES] = 0x80; - m_fga002[FGA_RSCPUCALL] = 0x80; - m_fga002[FGA_RSLOCSW] = 0x80; - m_fga002[FGA_ISTIM0] = 0x80; - m_fga002[FGA_ISDMANORM] = 0x80; - m_fga002[FGA_ISDMAERR] = 0x80; - m_fga002[FGA_ISFMB0REF] = 0x80; - m_fga002[FGA_ISFMB1REF] = 0x80; - m_fga002[FGA_ISPARITY] = 0x80; - m_fga002[FGA_ISABORT] = 0x80; - m_fga002[FGA_ISACFAIL] = 0x80; - m_fga002[FGA_ISSYSFAIL] = 0x80; - m_fga002[FGA_ISFMB0MES] = 0x80; - m_fga002[FGA_ISFMB1MES] = 0x80; } /* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/ @@ -392,229 +277,6 @@ WRITE32_MEMBER (fccpu30_state::bootvect_w){ m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset. } -/* - * FGA-002 driver, might deserve its own driver but will rest here until another board wants it - * -The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and -containing 24,000 gates in a 281 pin PGA package. It provides interfaces to the 68020/30 microprocessor -as well as a VMEbus compatible interface. The auxilary interface of the gate array is a high speed data -channel used by the internal 32 bit DMA controller. The interface allows data transfer rates of up to -6 MByte/second. The timing of the local I/O interface is programmable and provides easy interfacing of -local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly -connected or connected via buffers to the gate array allowing easy implementation and usage. -The gate array registers are programmed by the local CPU. - -FEATURES: -- Programmable decoding for CPU and VME access to the local main memory -- Interrupt management for internal and external interrupt sources -- 32 bit multi-port DMA Controller -- FORCE Message Broadcast slave interface with 2 message channels -- 8 interrupt capable MAILBOXES -- 8 bit TIMER with 16 selectable internal source clocks -*/ -WRITE8_MEMBER (fccpu30_state::fga8_w){ - LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data)); - switch(offset) - { - case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break; - case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break; - case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break; - case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break; - case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break; - case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break; - case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break; - case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break; - case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break; - case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break; - case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break; - case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break; - case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break; - case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break; - case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break; - case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break; - case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break; - case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break; - case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break; - case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break; - case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break; - case FGA_ICRTIM0 : LOG(("FGA_ICRTIM0 - not implemented\n")); m_fga002[FGA_ICRTIM0] = data; break; - case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break; - case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break; - case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break; - case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break; - case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break; - case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break; - case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break; - case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break; - case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break; - case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break; - case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break; - case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break; - case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break; - case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break; - case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break; - case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break; - case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break; - case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break; - case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break; - case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break; - case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break; - case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break; - case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break; - case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break; - case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break; - case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break; - case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break; - case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break; - case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break; - case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break; - case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break; - case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break; - case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break; - case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break; - case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break; - case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break; - case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break; - case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break; - case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break; - case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break; - case FGA_TIM0PRELOAD : LOG(("FGA_TIM0PRELOAD - not implemented\n")); m_fga002[FGA_TIM0PRELOAD] = data; break; - case FGA_TIM0CTL : LOG(("FGA_TIM0CTL - not implemented\n")); m_fga002[FGA_TIM0CTL] = data; break; - case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break; - case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break; - case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break; - case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break; - case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break; - case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break; - case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break; - case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break; - case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break; - case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break; - case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break; - case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break; - case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break; - case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break; - case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break; - case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break; - case FGA_ISTIM0 : LOG(("FGA_ISTIM0 - not implemented\n")); m_fga002[FGA_ISTIM0] = data; break; - case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break; - case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break; - case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break; - case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break; - case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break; - case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break; - case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break; - case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break; - case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break; - case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break; - default: - LOG(("Unsupported register %04x\n", offset)); - } -} - -READ8_MEMBER (fccpu30_state::fga8_r){ - UINT8 ret = 0; - - LOG(("%s[%04x] ", FUNCNAME, offset)); - switch(offset) - { - case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break; - case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break; - case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break; - case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break; - case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break; - case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break; - case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break; - case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break; - case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break; - case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break; - case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break; - case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break; - case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break; - case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break; - case FGA_ICRTIM0 : ret = m_fga002[FGA_ICRTIM0]; LOG(("FGA_ICRTIM0 returns %02x - not implemented\n", ret)); break; - case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break; - case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break; - case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break; - case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break; - case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break; - case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break; - case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break; - case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break; - case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break; - case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break; - case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break; - case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break; - case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break; - case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break; - case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break; - case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break; - case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break; - case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break; - case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break; - case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break; - case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break; - case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break; - case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break; - case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break; - case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break; - case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break; - case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break; - case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break; - case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break; - case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break; - case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break; - case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break; - case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break; - case FGA_TIM0PRELOAD : ret = m_fga002[FGA_TIM0PRELOAD]; LOG(("FGA_TIM0PRELOAD returns %02x - not implemented\n", ret)); break; - case FGA_TIM0CTL : ret = m_fga002[FGA_TIM0CTL]; LOG(("FGA_TIM0CTL returns %02x - not implemented\n", ret)); break; - case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break; - case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break; - case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break; - case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break; - case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break; - case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break; - case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break; - case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break; - case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break; - case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break; - case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break; - case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break; - case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break; - case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break; - case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break; - case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break; - case FGA_ISTIM0 : ret = m_fga002[FGA_ISTIM0]; LOG(("FGA_ISTIM0 returns %02x - not implemented\n", ret)); break; - case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break; - case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break; - case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break; - case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break; - case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break; - case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break; - case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break; - case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break; - case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break; - case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break; - default: - LOG(("Unsupported register %04x\n", offset)); - } - return ret; -} - /* * Rotary Switches - to configure the board * @@ -690,7 +352,11 @@ READ8_MEMBER (fccpu30_state::rotary_rd){ */ READ8_MEMBER (fccpu30_state::board_mem_id_rd){ LOG(("%s\n", FUNCNAME)); - return 0x6A; // CPU-30 R4 with 4Mb of shared RAM. TODO: make this configurable from commandline or artwork + // return 0x6A; // CPU-30 R4 with 4Mb of shared RAM. TODO: make this configurable from commandline or artwork + // return 0x57; // blankt 53 56 + // return 0x36; // CPU-26 1Mb 36 MHz + // return 0x35; // CPU-26 1Mb 36 MHz + return 0x36; // CPU-26 1Mb 36 MHz } #if 0 @@ -719,7 +385,7 @@ WRITE16_MEMBER (fccpu30_state::vme_a16_w){ */ static MACHINE_CONFIG_START (fccpu30, fccpu30_state) /* basic machine hardware */ - MCFG_CPU_ADD ("maincpu", M68030, XTAL_16MHz) + MCFG_CPU_ADD ("maincpu", M68030, XTAL_25MHz) MCFG_CPU_PROGRAM_MAP (fccpu30_mem) MCFG_NVRAM_ADD_0FILL("nvram") @@ -733,22 +399,35 @@ static MACHINE_CONFIG_START (fccpu30, fccpu30_state) MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, rxa_w)) MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, ctsa_w)) -// MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 ) + MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 ) /* PIT Parallel Interface and Timer device, assuming strapped for on board clock */ - MCFG_DEVICE_ADD ("pit1", PIT68230, XTAL_16MHz / 2) + MCFG_DEVICE_ADD ("pit1", PIT68230, XTAL_16MHz / 2) // The PIT clock is not verified on schema but reversed from behaviour MCFG_PIT68230_PA_INPUT_CB(READ8(fccpu30_state, rotary_rd)) - MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_16MHz / 2) + MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_16MHz / 2) // Th PIT clock is not verified on schema but reversed from behaviour MCFG_PIT68230_PB_INPUT_CB(READ8(fccpu30_state, board_mem_id_rd)) + + /* FGA-002, Force Gate Array */ + MCFG_FGA002_ADD("fga002", 0) MACHINE_CONFIG_END /* ROM definitions */ ROM_START (fccpu30) ROM_REGION32_BE(0x900000, "roms", 0) - ROM_LOAD32_BYTE("CPU30UU.bin", 0x000000, 0x20000, CRC(66e95cc2) SHA1(acdb468a3a5974295b81271d617de7f101098891) ) - ROM_LOAD32_BYTE("CPU30UP.bin", 0x000001, 0x20000, CRC(dfed1f68) SHA1(71478a77d5ab5da0fabcd78e69537919b560e3b8) ) - ROM_LOAD32_BYTE("CPU30LO.bin", 0x000002, 0x20000, CRC(fefa88ed) SHA1(71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9) ) - ROM_LOAD32_BYTE("CPU30LL.bin", 0x000003, 0x20000, CRC(a03ebf46) SHA1(48fa0268cb10e20679c093e02574dbd9925f95d1) ) + +// Boots with Board ID set to: 0x36 + ROM_LOAD16_BYTE("CPU33LO.BIN", 0x000001, 0x40000, CRC (49895fdf) SHA1 (733abd144c95225a2faf920490e31df2a27f8e03)) + ROM_LOAD16_BYTE("CPU33UP.BIN", 0x000000, 0x40000, CRC (cfe75e94) SHA1 (d40e0635a48607be25f7c58c74b53b7e58fe735d)) + +// Boots with Board ID set to: 0x36 (no display yet) +#if 0 + ROM_LOAD32_BYTE("CPU30LL.BIN", 0x000003, 0x20000, CRC (a03ebf46) SHA1 (48fa0268cb10e20679c093e02574dbd9925f95d1)) + ROM_LOAD32_BYTE("CPU30LO.BIN", 0x000002, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9)) + ROM_LOAD32_BYTE("CPU30UP.BIN", 0x000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8)) + ROM_LOAD32_BYTE("CPU30UU.BIN", 0x000000, 0x20000, CRC (66e95cc2) SHA1 (acdb468a3a5974295b81271d617de7f101098891)) +#endif + +// Same binary for many boards, attempts to detect CPU speed etc, currently failing detection but boots system roms anyway ROM_LOAD ("PGA-002.bin", 0x800000, 0x10000, CRC(faa38972) SHA1(651dfc2f9a865fc6adf49dad90f9e705f2889919) ) ROM_END