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https://github.com/holub/mame
synced 2025-04-22 08:22:15 +03:00
Check-point
This commit is contained in:
Angelo Salese
parent
a41a17c4b5
commit
30346a8b60
@ -28,6 +28,8 @@ public:
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UINT8 *m_work_ram;
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UINT8 *m_shared_ram;
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UINT8 m_ma,m_mo,m_ms,m_me2,m_me1;
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DECLARE_READ8_MEMBER(mz3500_master_mem_r);
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DECLARE_WRITE8_MEMBER(mz3500_master_mem_w);
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DECLARE_READ8_MEMBER(mz3500_ipl_r);
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@ -36,6 +38,8 @@ public:
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DECLARE_WRITE8_MEMBER(mz3500_work_ram_w);
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DECLARE_READ8_MEMBER(mz3500_shared_ram_r);
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DECLARE_WRITE8_MEMBER(mz3500_shared_ram_w);
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DECLARE_READ8_MEMBER(mz3500_io_r);
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DECLARE_WRITE8_MEMBER(mz3500_io_w);
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// screen updates
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UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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@ -81,26 +85,121 @@ WRITE8_MEMBER(mz3500_state::mz3500_work_ram_w)
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READ8_MEMBER(mz3500_state::mz3500_master_mem_r)
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{
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if((offset & 0xe000) == 0x0000) { return mz3500_ipl_r(space,(offset & 0xfff) | 0x1000); }
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if((offset & 0xe000) == 0x2000) { return mz3500_basic_r(space,offset & 0x1fff); }
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if((offset & 0xe000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x4000); }
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if((offset & 0xe000) == 0x6000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x6000); }
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if((offset & 0xe000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0x8000); }
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if((offset & 0xe000) == 0xa000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xa000); }
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if((offset & 0xe000) == 0xc000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xc000); }
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if((offset & 0xe000) == 0xe000) { return mz3500_work_ram_r(space,(offset & 0x1fff) | 0xe000); }
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if(m_ms == 0)
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{
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if((offset & 0xe000) == 0x0000) { return mz3500_ipl_r(space,(offset & 0xfff) | 0x1000); }
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if((offset & 0xe000) == 0x2000) { return mz3500_basic_r(space,(offset & 0x1fff) | 0x2000); }
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if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x4000); }
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if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x8000); }
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if((offset & 0xc000) == 0xc000)
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{
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if(m_ma == 0x0) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0xc000); }
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if(m_ma == 0x1) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x0000); }
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if(m_ma == 0xf) { return mz3500_shared_ram_r(space,(offset & 0x7ff)); }
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}
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printf("Error: read with unmapped memory bank offset %04x MS %02x MA %02x\n",offset,m_ms,m_ma);
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}
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else if(m_ms == 1)
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{
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return ((offset & 0xf800) == 0xf800) ? mz3500_shared_ram_r(space,(offset & 0x7ff)) : mz3500_work_ram_r(space,offset);
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}
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else if(m_ms == 2) // ROM based BASIC
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{
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if((offset & 0xe000) == 0x0000) { return mz3500_basic_r(space,offset & 0x1fff); }
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if((offset & 0xe000) == 0x2000)
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{
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switch(m_mo)
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{
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case 0x0: return mz3500_basic_r(space,(offset & 0x1fff) | 0x2000);
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case 0x1: return mz3500_basic_r(space,(offset & 0x1fff) | 0x4000);
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case 0x2: return mz3500_basic_r(space,(offset & 0x1fff) | 0x6000);
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}
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printf("Error: read with unmapped memory bank offset %04x MS %02x MO %02x\n",offset,m_ms,m_mo);
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}
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if((offset & 0xc000) == 0x4000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x4000); }
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if((offset & 0xc000) == 0x8000) { return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x8000); }
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if((offset & 0xc000) == 0xc000)
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{
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switch(m_ma)
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{
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case 0x0: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x0c000);
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case 0x1: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x00000);
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case 0x2: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x10000);
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case 0x3: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x14000);
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case 0x4: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x18000);
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case 0x5: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x1c000);
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case 0x6: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x20000);
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case 0x7: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x24000);
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case 0x8: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x28000);
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case 0x9: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x2c000);
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case 0xa: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x30000);
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case 0xb: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x34000);
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case 0xc: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x38000);
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case 0xd: return mz3500_work_ram_r(space,(offset & 0x3fff) | 0x3c000);
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case 0xf: return mz3500_shared_ram_r(space,(offset & 0x7ff));
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}
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}
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printf("Error: read with unmapped memory bank offset %04x MS %02x MA %02x\n",offset,m_ms,m_ma);
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}
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return 0xff;
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}
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WRITE8_MEMBER(mz3500_state::mz3500_master_mem_w)
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{
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if((offset & 0xe000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x4000,data); return; }
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if((offset & 0xe000) == 0x6000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x6000,data); return; }
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if((offset & 0xe000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0x8000,data); return; }
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if((offset & 0xe000) == 0xa000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xa000,data); return; }
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if((offset & 0xe000) == 0xc000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xc000,data); return; }
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if((offset & 0xe000) == 0xe000) { mz3500_work_ram_w(space,(offset & 0x1fff) | 0xe000,data); return; }
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if(m_ms == 0) // Initialize State
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{
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if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x4000,data); return; }
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if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x8000,data); return; }
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if((offset & 0xc000) == 0xc000)
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{
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if(m_ma == 0x0) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0xc000,data); return; }
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if(m_ma == 0x1) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x0000,data); return; }
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if(m_ma == 0xf) { mz3500_shared_ram_w(space,(offset & 0x7ff),data); return; }
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}
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printf("Error: write with unmapped memory bank offset %04x data %02x MS %02x MA %02x\n",offset,data,m_ms,m_ma);
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}
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else if(m_ms == 1) // System Loading & CP/M
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{
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if((offset & 0xf800) == 0xf800)
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mz3500_shared_ram_w(space,(offset & 0x7ff),data);
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else
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mz3500_work_ram_w(space,offset,data);
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return;
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}
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else if(m_ms == 2) // ROM based BASIC
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{
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if((offset & 0xc000) == 0x4000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x4000,data); return; }
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if((offset & 0xc000) == 0x8000) { mz3500_work_ram_w(space,(offset & 0x3fff) | 0x8000,data); return; }
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if((offset & 0xc000) == 0xc000)
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{
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switch(m_ma)
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{
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case 0x0: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x0c000,data); return;
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case 0x1: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x00000,data); return;
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case 0x2: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x10000,data); return;
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case 0x3: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x14000,data); return;
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case 0x4: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x18000,data); return;
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case 0x5: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x1c000,data); return;
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case 0x6: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x20000,data); return;
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case 0x7: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x24000,data); return;
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case 0x8: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x28000,data); return;
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case 0x9: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x2c000,data); return;
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case 0xa: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x30000,data); return;
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case 0xb: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x34000,data); return;
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case 0xc: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x38000,data); return;
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case 0xd: mz3500_work_ram_w(space,(offset & 0x3fff) | 0x3c000,data); return;
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case 0xf: mz3500_shared_ram_w(space,(offset & 0x7ff),data); return;
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}
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}
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printf("Error: write with unmapped memory bank offset %04x data %02x MS %02x MA %02x\n",offset,data,m_ms,m_ma);
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}
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}
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@ -114,6 +213,55 @@ WRITE8_MEMBER(mz3500_state::mz3500_shared_ram_w)
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m_shared_ram[offset] = data;
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}
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READ8_MEMBER(mz3500_state::mz3500_io_r)
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{
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/*
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[2]
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---x xxx- system assign switch
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---- ---x "SEC" FD assign
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[3]
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xxx- ---- FD assign
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---x ---- slave CPU Ready signal
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---- x--- slave CPU ack signal
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---- -xxx interrupt status
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*/
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return 0;
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}
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WRITE8_MEMBER(mz3500_state::mz3500_io_w)
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{
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/*
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[0]
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---- --x- SRQ bus request from master to slave
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---- ---x E1
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[1]
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x--- ---- slave reset signal
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---- --xx memory system define
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[2]
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xxxx ---- ma bank (memory 0xc000-0xffff)
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---- -xxx mo bank (memory 0x2000-0x3fff)
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[3]
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x--- ---- me2 bank (memory 0x8000-0xbfff)
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-x-- ---- me1 bank (memory 0x4000-0x7fff)
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*/
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switch(offset)
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{
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case 1:
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m_ms = data & 3;
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break;
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case 2:
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m_ma = (data & 0xf0) >> 4;
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m_mo = (data & 0x07);
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break;
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case 3:
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m_me2 = (data & 0x80) >> 7;
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m_me1 = (data & 0x40) >> 6;
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break;
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}
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}
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static ADDRESS_MAP_START( mz3500_master_map, AS_PROGRAM, 8, mz3500_state )
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AM_RANGE(0x0000, 0xffff) AM_READWRITE(mz3500_master_mem_r,mz3500_master_mem_w)
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ADDRESS_MAP_END
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@ -125,7 +273,7 @@ static ADDRESS_MAP_START( mz3500_master_io, AS_IO, 8, mz3500_state )
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// AM_RANGE(0xec, 0xef) irq signal from slave to master CPU
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// AM_RANGE(0xf4, 0xf7) MFD upd765
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// AM_RANGE(0xf8, 0xfb) MFD I/O port
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// AM_RANGE(0xfc, 0xff) memory mapper
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AM_RANGE(0xfc, 0xff) AM_READWRITE(mz3500_io_r,mz3500_io_w) // memory mapper
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( mz3500_slave_map, AS_PROGRAM, 8, mz3500_state )
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@ -228,6 +376,13 @@ void mz3500_state::machine_start()
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void mz3500_state::machine_reset()
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{
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/* init memory bank states */
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m_ms = 0;
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m_ma = 0;
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m_mo = 0;
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m_me1 = 0;
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m_me2 = 0;
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m_slave->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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}
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