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Fuck, I missed the last commit (nw)

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This commit is contained in:
Olivier Galibert 2018-01-23 14:01:20 +01:00
parent c6c295748b
commit 30add0e064
5 changed files with 45 additions and 17 deletions
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8
src/emu/xtal.cpp
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@ -31,9 +31,11 @@
tolerance so be sure to reference existing parts only and not just
accept direct readings as 100% true.
MAME doesn't yet support fractions in crystal frequencies. For example,
XTAL(3'579'545) should actually be 3579545.454545...Hz (39375000/11).
This is no problem though: see above note about tolerance.
MAME supports fractions in crystal frequencies, but for historical
and readability reasons we tend to write the closest integer
value. For example, XTAL(3'579'545) should actually be
3579545.454545...Hz (39375000/11). This is no problem though: see
above note about tolerance.
In the "Examples" column, please don't add 1000 examples, this is just
for interest, so two or three examples is enough.

44
src/emu/xtal.h
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@ -1,11 +1,37 @@
// license:BSD-3-Clause
// copyright-holders:Nicola Salmoria
// copyright-holders:Olivier Galibert
/*************************************************************************
xtal.h
Documentation and consistent naming for known existing crystals.
See the .cpp file for details
Documentation for known existing crystals.
See the .cpp file for the crystal list
Usage:
When you're 100% sure there is a given crystal or resonator on a
PCB, use XTAL(frequency) to document so. That xtal object then
collates multiplies or divides done to the base frequency to
compute the final one.
If you recieve a XTAL object and want to turn it to a final
frequency, use value() to get an integer or dvalue() to get a
double.
If you recieve a XTAL object and want to check if the initial
crystal value is sane, use check(context message). It will
fatalerror if the value is not in the authorized value list. It
has a (small) cost, so don't do it in a hot path.
Remember that with PLLs it is perfectly normal to multiply
frequencies by a rational. For instance the 315-5746 in the Sega
Saturn generates two dotclocks at 57.27MHz and 53.69MHz as needed
from a single 13.32MHz crystal. Banks of oscillators connected to
a chip usually don't exist. So if you're doing a switch to select
a frequency between multiple XTAL() ones, you're probably doing it
wrong. If you're selecting multipliers on a single crystal otoh,
that's perfectly normal. I'm looking at you, VGA pixel clock
generators.
***************************************************************************/
@ -53,11 +79,11 @@ private:
static void check_ordering();
};
inline constexpr XTAL operator /(int div, const XTAL &xtal) { return XTAL(xtal.base(), div / xtal.dvalue()); }
inline constexpr XTAL operator /(unsigned int div, const XTAL &xtal) { return XTAL(xtal.base(), div / xtal.dvalue()); }
inline constexpr XTAL operator /(double div, const XTAL &xtal) { return XTAL(xtal.base(), div / xtal.dvalue()); }
inline constexpr XTAL operator *(int mult, const XTAL &xtal) { return XTAL(xtal.base(), mult * xtal.dvalue()); }
inline constexpr XTAL operator *(unsigned int mult, const XTAL &xtal) { return XTAL(xtal.base(), mult * xtal.dvalue()); }
inline constexpr XTAL operator *(double mult, const XTAL &xtal) { return XTAL(xtal.base(), mult * xtal.dvalue()); }
constexpr XTAL operator /(int div, const XTAL &xtal) { return XTAL(xtal.base(), div / xtal.dvalue()); }
constexpr XTAL operator /(unsigned int div, const XTAL &xtal) { return XTAL(xtal.base(), div / xtal.dvalue()); }
constexpr XTAL operator /(double div, const XTAL &xtal) { return XTAL(xtal.base(), div / xtal.dvalue()); }
constexpr XTAL operator *(int mult, const XTAL &xtal) { return XTAL(xtal.base(), mult * xtal.dvalue()); }
constexpr XTAL operator *(unsigned int mult, const XTAL &xtal) { return XTAL(xtal.base(), mult * xtal.dvalue()); }
constexpr XTAL operator *(double mult, const XTAL &xtal) { return XTAL(xtal.base(), mult * xtal.dvalue()); }
#endif // MAME_EMU_DRIVERS_XTAL_H

2
src/mame/drivers/nes_vt.cpp
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@ -1064,7 +1064,7 @@ MACHINE_CONFIG_DERIVED(nes_vt_state::nes_vt_dg, nes_vt_xx)
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_REFRESH_RATE(50.0070)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK/1000000)) * (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)))
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC((106.53/(PAL_APU_CLOCK.dvalue()/1000000)) * (ppu2c0x_device::VBLANK_LAST_SCANLINE_PAL-ppu2c0x_device::VBLANK_FIRST_SCANLINE+1+2)))
MCFG_SCREEN_SIZE(32*8, 312)
MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 0*8, 30*8-1)
MACHINE_CONFIG_END

4
src/mame/drivers/tr175.cpp
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@ -83,10 +83,10 @@ MACHINE_CONFIG_START(tr175_state::tr175)
MCFG_CPU_PROGRAM_MAP(mem_map)
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(XTAL_28_322MHz, 900, 0, 720, 449, 0, 416) // guess
MCFG_SCREEN_RAW_PARAMS(XTAL(28'322'000), 900, 0, 720, 449, 0, 416) // guess
MCFG_SCREEN_UPDATE_DEVICE("avdc", scn2674_device, screen_update)
MCFG_DEVICE_ADD("avdc", SCN2674, XTAL_28_322MHz / 18) // guess
MCFG_DEVICE_ADD("avdc", SCN2674, XTAL(28'322'000) / 18) // guess
MCFG_SCN2674_INTR_CALLBACK(INPUTLINE("maincpu", M68K_IRQ_2))
MCFG_SCN2674_TEXT_CHARACTER_WIDTH(18) // guess
MCFG_SCN2674_GFX_CHARACTER_WIDTH(18) // guess

4
src/mame/drivers/vp122.cpp
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@ -72,10 +72,10 @@ MACHINE_CONFIG_START(vp122_state::vp122)
MCFG_NVRAM_ADD_0FILL("nvram") // MK48Z02
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(XTAL_14_916MHz, 960, 0, 800, 259, 0, 240)
MCFG_SCREEN_RAW_PARAMS(XTAL(14'916'000), 960, 0, 800, 259, 0, 240)
MCFG_SCREEN_UPDATE_DEVICE("avdc", scn2674_device, screen_update)
MCFG_DEVICE_ADD("avdc", SCN2674, XTAL_14_916MHz / 10)
MCFG_DEVICE_ADD("avdc", SCN2674, XTAL(14'916'000) / 10)
MCFG_SCN2674_INTR_CALLBACK(INPUTLINE("maincpu", I8085_RST65_LINE))
MCFG_SCN2674_TEXT_CHARACTER_WIDTH(10)
MCFG_SCN2674_GFX_CHARACTER_WIDTH(10)