mirror of
https://github.com/holub/mame
synced 2025-06-30 16:00:01 +03:00
(nw) aussiebyte: don't write to regions
This commit is contained in:
Robbbert
parent
e7d7489361
commit
30c89549f8
@ -43,15 +43,15 @@
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************************************************************/
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void aussiebyte_state::aussiebyte_map(address_map &map)
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void aussiebyte_state::mem_map(address_map &map)
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{
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map(0x0000, 0x3fff).bankr("bankr0").bankw("bankw0");
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map(0x4000, 0x7fff).bankrw("bank1");
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map(0x8000, 0xbfff).bankrw("bank2");
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map(0xc000, 0xffff).ram().region("mram", 0x0000);
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map(0xc000, 0xffff).bankrw("bank3");
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}
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void aussiebyte_state::aussiebyte_io(address_map &map)
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void aussiebyte_state::io_map(address_map &map)
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{
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map.global_mask(0xff);
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map.unmap_value_high();
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@ -97,7 +97,7 @@ INPUT_PORTS_END
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I/O Ports
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************************************************************/
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void aussiebyte_state::port15_w(uint8_t data)
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void aussiebyte_state::port15_w(u8 data)
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{
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membank("bankr0")->set_entry(m_port15); // point at ram
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m_port15 = true;
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@ -115,7 +115,7 @@ void aussiebyte_state::port15_w(uint8_t data)
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5 Disable 5.25 inch floppy spindle motors.
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6 Unused.
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7 Enable write precompensation on WD2797 controller. */
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void aussiebyte_state::port16_w(uint8_t data)
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void aussiebyte_state::port16_w(u8 data)
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{
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floppy_image_device *m_floppy = nullptr;
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if ((data & 15) == 0)
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@ -142,7 +142,7 @@ void aussiebyte_state::port16_w(uint8_t data)
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5 - SIO Ch D
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6 - Ext ready 1
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7 - Ext ready 2 */
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void aussiebyte_state::port17_w(uint8_t data)
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void aussiebyte_state::port17_w(u8 data)
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{
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m_port17 = data & 7;
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m_dma->rdy_w(BIT(m_port17_rdy, data));
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@ -151,19 +151,19 @@ void aussiebyte_state::port17_w(uint8_t data)
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/* FDC params
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2 EXC: WD2797 clock frequency. H = 5.25"; L = 8"
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3 WIEN: WD2797 Double density select. */
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void aussiebyte_state::port18_w(uint8_t data)
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void aussiebyte_state::port18_w(u8 data)
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{
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m_fdc->set_unscaled_clock(BIT(data, 2) ? 1e6 : 2e6);
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m_fdc->dden_w(BIT(data, 3));
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}
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uint8_t aussiebyte_state::port19_r()
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u8 aussiebyte_state::port19_r()
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{
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return m_port19;
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}
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// Memory banking
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void aussiebyte_state::port1a_w(uint8_t data)
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void aussiebyte_state::port1a_w(u8 data)
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{
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data &= 7;
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switch (data)
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@ -208,23 +208,23 @@ void aussiebyte_state::port1a_w(uint8_t data)
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}
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// Winchester control
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void aussiebyte_state::port1b_w(uint8_t data)
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void aussiebyte_state::port1b_w(u8 data)
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{
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}
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// GPEHB control
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void aussiebyte_state::port1c_w(uint8_t data)
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void aussiebyte_state::port1c_w(u8 data)
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{
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}
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void aussiebyte_state::port20_w(uint8_t data)
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void aussiebyte_state::port20_w(u8 data)
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{
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m_speaker->level_w(BIT(data, 7));
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m_rtc->cs_w(BIT(data, 0));
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m_rtc->hold_w(BIT(data, 0));
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}
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uint8_t aussiebyte_state::port28_r()
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u8 aussiebyte_state::port28_r()
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{
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return m_port28;
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}
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@ -234,16 +234,16 @@ uint8_t aussiebyte_state::port28_r()
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RTC
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************************************************************/
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uint8_t aussiebyte_state::rtc_r(offs_t offset)
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u8 aussiebyte_state::rtc_r(offs_t offset)
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{
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m_rtc->read_w(1);
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m_rtc->address_w(offset);
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uint8_t data = m_rtc->data_r();
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u8 data = m_rtc->data_r();
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m_rtc->read_w(0);
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return data;
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}
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void aussiebyte_state::rtc_w(offs_t offset, uint8_t data)
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void aussiebyte_state::rtc_w(offs_t offset, u8 data)
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{
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m_rtc->address_w(offset);
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m_rtc->data_w(data);
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@ -256,25 +256,25 @@ void aussiebyte_state::rtc_w(offs_t offset, uint8_t data)
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DMA
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************************************************************/
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uint8_t aussiebyte_state::memory_read_byte(offs_t offset)
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u8 aussiebyte_state::memory_read_byte(offs_t offset)
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{
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address_space& prog_space = m_maincpu->space(AS_PROGRAM);
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return prog_space.read_byte(offset);
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}
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void aussiebyte_state::memory_write_byte(offs_t offset, uint8_t data)
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void aussiebyte_state::memory_write_byte(offs_t offset, u8 data)
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{
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address_space& prog_space = m_maincpu->space(AS_PROGRAM);
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prog_space.write_byte(offset, data);
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}
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uint8_t aussiebyte_state::io_read_byte(offs_t offset)
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u8 aussiebyte_state::io_read_byte(offs_t offset)
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{
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address_space& prog_space = m_maincpu->space(AS_IO);
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return prog_space.read_byte(offset);
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}
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void aussiebyte_state::io_write_byte(offs_t offset, uint8_t data)
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void aussiebyte_state::io_write_byte(offs_t offset, u8 data)
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{
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address_space& prog_space = m_maincpu->space(AS_IO);
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prog_space.write_byte(offset, data);
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@ -294,28 +294,28 @@ WRITE_LINE_MEMBER( aussiebyte_state::busreq_w )
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************************************************************/
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WRITE_LINE_MEMBER( aussiebyte_state::sio1_rdya_w )
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{
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m_port17_rdy = (m_port17_rdy & 0xfd) | (uint8_t)(state << 1);
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m_port17_rdy = (m_port17_rdy & 0xfd) | (u8)(state << 1);
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if (m_port17 == 1)
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m_dma->rdy_w(state);
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}
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WRITE_LINE_MEMBER( aussiebyte_state::sio1_rdyb_w )
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{
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m_port17_rdy = (m_port17_rdy & 0xfb) | (uint8_t)(state << 2);
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m_port17_rdy = (m_port17_rdy & 0xfb) | (u8)(state << 2);
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if (m_port17 == 2)
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m_dma->rdy_w(state);
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}
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WRITE_LINE_MEMBER( aussiebyte_state::sio2_rdya_w )
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{
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m_port17_rdy = (m_port17_rdy & 0xef) | (uint8_t)(state << 4);
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m_port17_rdy = (m_port17_rdy & 0xef) | (u8)(state << 4);
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if (m_port17 == 4)
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m_dma->rdy_w(state);
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}
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WRITE_LINE_MEMBER( aussiebyte_state::sio2_rdyb_w )
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{
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m_port17_rdy = (m_port17_rdy & 0xdf) | (uint8_t)(state << 5);
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m_port17_rdy = (m_port17_rdy & 0xdf) | (u8)(state << 5);
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if (m_port17 == 5)
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m_dma->rdy_w(state);
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}
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@ -363,40 +363,6 @@ static const z80_daisy_config daisy_chain_intf[] =
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};
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/***********************************************************
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CTC
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************************************************************/
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// baud rate generator. All inputs are 1.2288MHz.
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WRITE_LINE_MEMBER( aussiebyte_state::ctc_z2_w )
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{
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m_ctc->trg3(1);
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m_ctc->trg3(0);
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}
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/***********************************************************
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Centronics ack
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************************************************************/
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WRITE_LINE_MEMBER( aussiebyte_state::write_centronics_busy )
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{
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m_centronics_busy = state;
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}
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/***********************************************************
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Speech ack
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************************************************************/
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WRITE_LINE_MEMBER( aussiebyte_state::votrax_w )
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{
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m_port28 = state;
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}
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/***********************************************************
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Floppy Disk
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@ -405,16 +371,16 @@ WRITE_LINE_MEMBER( aussiebyte_state::votrax_w )
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WRITE_LINE_MEMBER( aussiebyte_state::fdc_intrq_w )
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{
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uint8_t data = (m_port19 & 0xbf) | (state ? 0x40 : 0);
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u8 data = (m_port19 & 0xbf) | (state ? 0x40 : 0);
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m_port19 = data;
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}
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WRITE_LINE_MEMBER( aussiebyte_state::fdc_drq_w )
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{
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uint8_t data = (m_port19 & 0x7f) | (state ? 0x80 : 0);
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u8 data = (m_port19 & 0x7f) | (state ? 0x80 : 0);
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m_port19 = data;
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state ^= 1; // inverter on pin38 of fdc
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m_port17_rdy = (m_port17_rdy & 0xfe) | (uint8_t)state;
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m_port17_rdy = (m_port17_rdy & 0xfe) | (u8)state;
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if (m_port17 == 0)
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m_dma->rdy_w(state);
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}
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@ -457,9 +423,9 @@ QUICKLOAD_LOAD_MEMBER(aussiebyte_state::quickload_cb)
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}
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/* Load image to the TPA (Transient Program Area) */
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for (uint16_t i = 0; i < quickload_size; i++)
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for (u16 i = 0; i < quickload_size; i++)
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{
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uint8_t data;
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u8 data;
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if (image.fread( &data, 1) != 1)
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return image_init_result::FAIL;
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prog_space.write_byte(i+0x100, data);
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@ -492,15 +458,52 @@ void aussiebyte_state::machine_reset()
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membank("bankw0")->set_entry(1); // always write to ram
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membank("bank1")->set_entry(2);
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membank("bank2")->set_entry(3);
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membank("bank3")->set_entry(0);
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m_maincpu->reset();
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}
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void aussiebyte_state::machine_start()
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{
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m_vram = std::make_unique<u8[]>(0x10000);
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m_aram = std::make_unique<u8[]>(0x800);
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m_ram = make_unique_clear<u8[]>(0x40000);
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save_pointer(NAME(m_vram), 0x10000);
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save_pointer(NAME(m_aram), 0x800);
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save_pointer(NAME(m_ram), 0x40000);
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save_item(NAME(m_port15));
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save_item(NAME(m_port17));
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save_item(NAME(m_port17_rdy));
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save_item(NAME(m_port19));
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save_item(NAME(m_port1a));
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save_item(NAME(m_port28));
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save_item(NAME(m_port34));
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save_item(NAME(m_port35));
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save_item(NAME(m_video_index));
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save_item(NAME(m_cnt));
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save_item(NAME(m_alpha_address));
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save_item(NAME(m_graph_address));
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save_item(NAME(m_centronics_busy));
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// Main ram is divided into 16k blocks (0-15). The boot rom is block number 16.
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// For convenience, bank 0 is permanently assigned to C000-FFFF
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u8 *main = memregion("roms")->base();
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u8 *ram = m_ram.get();
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membank("bankr0")->configure_entries(0, 16, ram, 0x4000);
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membank("bankw0")->configure_entries(0, 16, ram, 0x4000);
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membank("bank1")->configure_entries(0, 16, ram, 0x4000);
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membank("bank2")->configure_entries(0, 16, ram, 0x4000);
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membank("bank3")->configure_entries(0, 1, ram, 0x4000);
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membank("bankr0")->configure_entry(16, &main[0x0000]);
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}
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void aussiebyte_state::aussiebyte(machine_config &config)
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{
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/* basic machine hardware */
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Z80(config, m_maincpu, 16_MHz_XTAL / 4);
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m_maincpu->set_addrmap(AS_PROGRAM, &aussiebyte_state::aussiebyte_map);
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m_maincpu->set_addrmap(AS_IO, &aussiebyte_state::aussiebyte_io);
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m_maincpu->set_addrmap(AS_PROGRAM, &aussiebyte_state::mem_map);
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m_maincpu->set_addrmap(AS_IO, &aussiebyte_state::io_map);
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m_maincpu->set_daisy_config(daisy_chain_intf);
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/* video hardware */
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@ -515,13 +518,13 @@ void aussiebyte_state::aussiebyte(machine_config &config)
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SPEAKER(config, "mono").front_center();
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SPEAKER_SOUND(config, m_speaker).add_route(ALL_OUTPUTS, "mono", 0.50);
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VOTRAX_SC01(config, m_votrax, 720000); // 720kHz? needs verify
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m_votrax->ar_callback().set(FUNC(aussiebyte_state::votrax_w));
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m_votrax->ar_callback().set([this] (bool state) { m_port28 = state ? 0 : 1; });
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m_votrax->add_route(ALL_OUTPUTS, "mono", 1.00);
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/* devices */
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CENTRONICS(config, m_centronics, centronics_devices, "printer");
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m_centronics->set_data_input_buffer("cent_data_in");
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m_centronics->busy_handler().set(FUNC(aussiebyte_state::write_centronics_busy));
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m_centronics->busy_handler().set([this] (bool state) { m_centronics_busy = state; });
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INPUT_BUFFER(config, "cent_data_in");
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output_latch_device ¢_data_out(OUTPUT_LATCH(config, "cent_data_out"));
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m_centronics->set_output_latch(cent_data_out);
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@ -536,7 +539,7 @@ void aussiebyte_state::aussiebyte(machine_config &config)
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m_ctc->zc_callback<1>().set("sio1", FUNC(z80sio_device::rxtxcb_w));
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m_ctc->zc_callback<1>().append("sio2", FUNC(z80sio_device::rxca_w));
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m_ctc->zc_callback<1>().append("sio2", FUNC(z80sio_device::txca_w));
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m_ctc->zc_callback<2>().set(FUNC(aussiebyte_state::ctc_z2_w)); // SIO2 Ch B, CTC Ch 3
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m_ctc->zc_callback<2>().set("ctc", FUNC(z80ctc_device::trg3));
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m_ctc->zc_callback<2>().append("sio2", FUNC(z80sio_device::rxtxcb_w));
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Z80DMA(config, m_dma, 16_MHz_XTAL / 4);
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@ -597,21 +600,6 @@ void aussiebyte_state::aussiebyte(machine_config &config)
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}
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void aussiebyte_state::machine_start()
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{
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// Main ram is divided into 16k blocks (0-15). The boot rom is block number 16.
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// For convenience, bank 0 is permanently assigned to C000-FFFF
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uint8_t *main = memregion("roms")->base();
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uint8_t *ram = memregion("mram")->base();
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membank("bankr0")->configure_entries(0, 16, &ram[0x0000], 0x4000);
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membank("bankw0")->configure_entries(0, 16, &ram[0x0000], 0x4000);
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membank("bank1")->configure_entries(0, 16, &ram[0x0000], 0x4000);
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membank("bank2")->configure_entries(0, 16, &ram[0x0000], 0x4000);
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membank("bankr0")->configure_entry(16, &main[0x0000]);
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}
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/***********************************************************
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Game driver
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@ -625,11 +613,7 @@ ROM_START(aussieby)
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ROM_REGION(0x800, "chargen", 0)
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ROM_LOAD( "8002.bin", 0x0000, 0x0800, CRC(fdd6eb13) SHA1(a094d416e66bdab916e72238112a6265a75ca690) )
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ROM_REGION(0x40000, "mram", ROMREGION_ERASE00) // main ram, 256k dynamic
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ROM_REGION(0x10000, "vram", ROMREGION_ERASEFF) // video ram, 64k dynamic
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ROM_REGION(0x00800, "aram", ROMREGION_ERASEFF) // attribute ram, 2k static
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ROM_END
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// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
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COMP( 1984, aussieby, 0, 0, aussiebyte, aussiebyte, aussiebyte_state, empty_init, "SME Systems", "Aussie Byte II", MACHINE_IMPERFECT_GRAPHICS )
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COMP( 1984, aussieby, 0, 0, aussiebyte, aussiebyte, aussiebyte_state, empty_init, "SME Systems", "Aussie Byte II", MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
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@ -48,8 +48,6 @@ public:
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, m_palette(*this, "palette")
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, m_maincpu(*this, "maincpu")
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, m_p_chargen(*this, "chargen")
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, m_p_videoram(*this, "vram")
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, m_p_attribram(*this, "aram")
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, m_ctc(*this, "ctc")
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, m_dma(*this, "dma")
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, m_pio1(*this, "pio1")
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@ -69,68 +67,65 @@ public:
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DECLARE_QUICKLOAD_LOAD_MEMBER(quickload_cb);
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protected:
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uint8_t memory_read_byte(offs_t offset);
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void memory_write_byte(offs_t offset, uint8_t data);
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uint8_t io_read_byte(offs_t offset);
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void io_write_byte(offs_t offset, uint8_t data);
|
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DECLARE_WRITE_LINE_MEMBER(write_centronics_busy);
|
||||
void port15_w(uint8_t data);
|
||||
void port16_w(uint8_t data);
|
||||
void port17_w(uint8_t data);
|
||||
void port18_w(uint8_t data);
|
||||
uint8_t port19_r();
|
||||
void port1a_w(uint8_t data);
|
||||
void port1b_w(uint8_t data);
|
||||
void port1c_w(uint8_t data);
|
||||
void port20_w(uint8_t data);
|
||||
uint8_t port28_r();
|
||||
uint8_t port33_r();
|
||||
void port34_w(uint8_t data);
|
||||
void port35_w(uint8_t data);
|
||||
uint8_t port36_r();
|
||||
uint8_t port37_r();
|
||||
uint8_t rtc_r(offs_t offset);
|
||||
void rtc_w(offs_t offset, uint8_t data);
|
||||
private:
|
||||
u8 memory_read_byte(offs_t offset);
|
||||
void memory_write_byte(offs_t offset, u8 data);
|
||||
u8 io_read_byte(offs_t offset);
|
||||
void io_write_byte(offs_t offset, u8 data);
|
||||
void port15_w(u8 data);
|
||||
void port16_w(u8 data);
|
||||
void port17_w(u8 data);
|
||||
void port18_w(u8 data);
|
||||
u8 port19_r();
|
||||
void port1a_w(u8 data);
|
||||
void port1b_w(u8 data);
|
||||
void port1c_w(u8 data);
|
||||
void port20_w(u8 data);
|
||||
u8 port28_r();
|
||||
u8 port33_r();
|
||||
void port34_w(u8 data);
|
||||
void port35_w(u8 data);
|
||||
u8 port36_r();
|
||||
u8 port37_r();
|
||||
u8 rtc_r(offs_t offset);
|
||||
void rtc_w(offs_t offset, u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_intrq_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(busreq_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(votrax_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(sio1_rdya_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(sio1_rdyb_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(sio2_rdya_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(sio2_rdyb_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(ctc_z2_w);
|
||||
void address_w(uint8_t data);
|
||||
void register_w(uint8_t data);
|
||||
void address_w(u8 data);
|
||||
void register_w(u8 data);
|
||||
MC6845_UPDATE_ROW(crtc_update_row);
|
||||
MC6845_ON_UPDATE_ADDR_CHANGED(crtc_update_addr);
|
||||
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
void aussiebyte_io(address_map &map);
|
||||
void aussiebyte_map(address_map &map);
|
||||
void io_map(address_map &map);
|
||||
void mem_map(address_map &map);
|
||||
|
||||
private:
|
||||
uint8_t crt8002(uint8_t ac_ra, uint8_t ac_chr, uint8_t ac_attr, uint16_t ac_cnt, bool ac_curs);
|
||||
u8 crt8002(u8 ac_ra, u8 ac_chr, u8 ac_attr, u16 ac_cnt, bool ac_curs);
|
||||
bool m_port15; // rom switched in (0), out (1)
|
||||
uint8_t m_port17;
|
||||
uint8_t m_port17_rdy;
|
||||
uint8_t m_port19;
|
||||
uint8_t m_port1a; // bank to switch to when write to port 15 happens
|
||||
uint8_t m_port28;
|
||||
uint8_t m_port34;
|
||||
uint8_t m_port35; // byte to be written to vram or aram
|
||||
uint8_t m_video_index;
|
||||
uint16_t m_cnt;
|
||||
uint16_t m_alpha_address;
|
||||
uint16_t m_graph_address;
|
||||
int m_centronics_busy;
|
||||
u8 m_port17;
|
||||
u8 m_port17_rdy;
|
||||
u8 m_port19;
|
||||
u8 m_port1a; // bank to switch to when write to port 15 happens
|
||||
u8 m_port28;
|
||||
u8 m_port34;
|
||||
u8 m_port35; // byte to be written to vram or aram
|
||||
u8 m_video_index;
|
||||
u16 m_cnt;
|
||||
u16 m_alpha_address;
|
||||
u16 m_graph_address;
|
||||
bool m_centronics_busy;
|
||||
std::unique_ptr<u8[]> m_vram; // video ram, 64k dynamic
|
||||
std::unique_ptr<u8[]> m_aram; // attribute ram, 2k static
|
||||
std::unique_ptr<u8[]> m_ram; // main ram, 256k dynamic
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<z80_device> m_maincpu;
|
||||
required_region_ptr<u8> m_p_chargen;
|
||||
required_region_ptr<u8> m_p_videoram;
|
||||
required_region_ptr<u8> m_p_attribram;
|
||||
required_device<z80ctc_device> m_ctc;
|
||||
required_device<z80dma_device> m_dma;
|
||||
required_device<z80pio_device> m_pio1;
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
************************************************************/
|
||||
|
||||
// dummy read port, forces requested action to happen
|
||||
uint8_t aussiebyte_state::port33_r()
|
||||
u8 aussiebyte_state::port33_r()
|
||||
{
|
||||
return 0xff;
|
||||
}
|
||||
@ -34,30 +34,30 @@ d5 - /SRRD - controls write of data to either vram or aram (1=vram, 0=aram)
|
||||
d6 - /VWR - 0 = enable write vdata to vram, read from aram to vdata ; 1 = enable write to aram from vdata
|
||||
d7 - OE on port 35
|
||||
*/
|
||||
void aussiebyte_state::port34_w(uint8_t data)
|
||||
void aussiebyte_state::port34_w(u8 data)
|
||||
{
|
||||
m_port34 = data;
|
||||
}
|
||||
|
||||
void aussiebyte_state::port35_w(uint8_t data)
|
||||
void aussiebyte_state::port35_w(u8 data)
|
||||
{
|
||||
m_port35 = data;
|
||||
}
|
||||
|
||||
uint8_t aussiebyte_state::port36_r()
|
||||
u8 aussiebyte_state::port36_r()
|
||||
{
|
||||
if (BIT(m_port34, 5))
|
||||
{
|
||||
if (BIT(m_p_attribram[m_alpha_address & 0x7ff], 7))
|
||||
return m_p_videoram[m_alpha_address];
|
||||
if (BIT(m_aram[m_alpha_address & 0x7ff], 7))
|
||||
return m_vram[m_alpha_address];
|
||||
else
|
||||
return m_p_videoram[m_graph_address];
|
||||
return m_vram[m_graph_address];
|
||||
}
|
||||
else
|
||||
return m_p_attribram[m_alpha_address & 0x7ff];
|
||||
return m_aram[m_alpha_address & 0x7ff];
|
||||
}
|
||||
|
||||
uint8_t aussiebyte_state::port37_r()
|
||||
u8 aussiebyte_state::port37_r()
|
||||
{
|
||||
return m_crtc->de_r() ? 0xff : 0xfe;
|
||||
}
|
||||
@ -74,7 +74,7 @@ MC6845_ON_UPDATE_ADDR_CHANGED( aussiebyte_state::crtc_update_addr )
|
||||
// m_video_address = address;// & 0x7ff;
|
||||
}
|
||||
|
||||
void aussiebyte_state::address_w(uint8_t data)
|
||||
void aussiebyte_state::address_w(u8 data)
|
||||
{
|
||||
m_crtc->address_w(data);
|
||||
|
||||
@ -88,20 +88,20 @@ void aussiebyte_state::address_w(uint8_t data)
|
||||
|
||||
if (BIT(m_port34, 5))
|
||||
{
|
||||
if (BIT(m_p_attribram[m_alpha_address & 0x7ff], 7))
|
||||
m_p_videoram[m_alpha_address] = m_port35;
|
||||
if (BIT(m_aram[m_alpha_address & 0x7ff], 7))
|
||||
m_vram[m_alpha_address] = m_port35;
|
||||
else
|
||||
m_p_videoram[m_graph_address] = m_port35;
|
||||
m_vram[m_graph_address] = m_port35;
|
||||
}
|
||||
else
|
||||
m_p_attribram[m_alpha_address & 0x7ff] = m_port35;
|
||||
m_aram[m_alpha_address & 0x7ff] = m_port35;
|
||||
}
|
||||
}
|
||||
|
||||
void aussiebyte_state::register_w(uint8_t data)
|
||||
void aussiebyte_state::register_w(u8 data)
|
||||
{
|
||||
m_crtc->register_w(data);
|
||||
uint16_t temp = m_alpha_address;
|
||||
u16 temp = m_alpha_address;
|
||||
|
||||
// Get transparent address
|
||||
if (m_video_index == 18)
|
||||
@ -111,9 +111,9 @@ void aussiebyte_state::register_w(uint8_t data)
|
||||
m_alpha_address = data | (temp & 0xff00);
|
||||
}
|
||||
|
||||
uint8_t aussiebyte_state::crt8002(uint8_t ac_ra, uint8_t ac_chr, uint8_t ac_attr, uint16_t ac_cnt, bool ac_curs)
|
||||
u8 aussiebyte_state::crt8002(u8 ac_ra, u8 ac_chr, u8 ac_attr, u16 ac_cnt, bool ac_curs)
|
||||
{
|
||||
uint8_t gfx = 0;
|
||||
u8 gfx = 0;
|
||||
switch (ac_attr & 3)
|
||||
{
|
||||
case 0: // lores gfx
|
||||
@ -167,20 +167,20 @@ uint8_t aussiebyte_state::crt8002(uint8_t ac_ra, uint8_t ac_chr, uint8_t ac_attr
|
||||
MC6845_UPDATE_ROW( aussiebyte_state::crtc_update_row )
|
||||
{
|
||||
const rgb_t *palette = m_palette->palette()->entry_list_raw();
|
||||
uint8_t chr,gfx,attr;
|
||||
uint16_t mem,x;
|
||||
uint32_t *p = &bitmap.pix32(y);
|
||||
u8 chr,gfx,attr;
|
||||
u16 mem,x;
|
||||
u32 *p = &bitmap.pix32(y);
|
||||
ra &= 15;
|
||||
m_cnt++;
|
||||
|
||||
for (x = 0; x < x_count; x++)
|
||||
{
|
||||
mem = ma + x;
|
||||
attr = m_p_attribram[mem & 0x7ff];
|
||||
attr = m_aram[mem & 0x7ff];
|
||||
if (BIT(attr, 7))
|
||||
chr = m_p_videoram[mem & 0x3fff]; // alpha
|
||||
chr = m_vram[mem & 0x3fff]; // alpha
|
||||
else
|
||||
chr = m_p_videoram[(mem << 4) | ra]; // gfx
|
||||
chr = m_vram[(mem << 4) | ra]; // gfx
|
||||
|
||||
gfx = crt8002(ra, chr, attr, m_cnt, (x==cursor_x));
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user