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Convert kidniki netlist into an external one.

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This commit is contained in:
couriersud 2016-04-17 22:21:33 +02:00
parent 162033204f
commit 31325d6599
4 changed files with 103 additions and 105 deletions
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1
scripts/target/mame/arcade.lua
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@ -1902,6 +1902,7 @@ files {
MAME_DIR .. "src/mame/machine/irem_cpu.h",
MAME_DIR .. "src/mame/audio/irem.cpp",
MAME_DIR .. "src/mame/audio/irem.h",
MAME_DIR .. "src/mame/audio/nl_kidniki.cpp",
}
createMAMEProjects(_target, _subtarget, "itech")

1
scripts/target/mame/nl.lua
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@ -118,6 +118,7 @@ files{
MAME_DIR .. "src/mame/includes/m62.h",
MAME_DIR .. "src/mame/video/m62.cpp",
MAME_DIR .. "src/mame/audio/irem.cpp",
MAME_DIR .. "src/mame/audio/nl_kidniki.cpp",
MAME_DIR .. "src/mame/audio/irem.h",
}

102
src/mame/audio/irem.cpp
View File

@ -10,12 +10,14 @@
#include "cpu/m6800/m6800.h"
#include "sound/discrete.h"
#include "audio/irem.h"
#include "netlist/devices/net_lib.h"
const device_type IREM_M62_AUDIO = &device_creator<m62_audio_device>;
const device_type IREM_M52_SOUNDC_AUDIO = &device_creator<m52_soundc_audio_device>;
const device_type IREM_M52_LARGE_AUDIO = &device_creator<m52_large_audio_device>;
NETLIST_EXTERNAL(kidniki)
irem_audio_device::irem_audio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
m_port1(0),
@ -406,102 +408,6 @@ ADDRESS_MAP_END
*
*/
#define USE_FRONTIERS 1
#define USE_FIXED_STV 1
#include "nl_kidniki.inc"
NETLIST_START(kidniki_interface)
#if (USE_FRONTIERS)
SOLVER(Solver, 18000)
PARAM(Solver.ACCURACY, 1e-8)
PARAM(Solver.NR_LOOPS, 300)
PARAM(Solver.GS_LOOPS, 1)
PARAM(Solver.GS_THRESHOLD, 6)
//PARAM(Solver.ITERATIVE, "SOR")
PARAM(Solver.ITERATIVE, "MAT_CR")
//PARAM(Solver.ITERATIVE, "GMRES")
PARAM(Solver.PARALLEL, 0)
PARAM(Solver.SOR_FACTOR, 1.00)
PARAM(Solver.DYNAMIC_TS, 0)
PARAM(Solver.DYNAMIC_LTE, 5e-4)
PARAM(Solver.MIN_TIMESTEP, 20e-6)
#else
SOLVER(Solver, 12000)
PARAM(Solver.ACCURACY, 1e-8)
PARAM(Solver.NR_LOOPS, 300)
PARAM(Solver.GS_LOOPS, 20)
PARAM(Solver.ITERATIVE, "GMRES")
PARAM(Solver.PARALLEL, 0)
#endif
LOCAL_SOURCE(kidniki_schematics)
ANALOG_INPUT(I_V5, 5)
//ANALOG_INPUT(I_V0, 0)
ALIAS(I_V0.Q, GND)
/* AY 8910 internal resistors */
RES(R_AY45L_A, 1000)
RES(R_AY45L_B, 1000)
RES(R_AY45L_C, 1000)
RES(R_AY45M_A, 1000)
RES(R_AY45M_B, 1000)
RES(R_AY45M_C, 1000)
NET_C(I_V5, R_AY45L_A.1, R_AY45L_B.1, R_AY45L_C.1, R_AY45M_A.1, R_AY45M_B.1, R_AY45M_C.1)
NET_C(R_AY45L_A.2, R_AY45L_B.2, R_AY45M_A.2, R_AY45M_B.2, R_AY45M_C.2)
ALIAS(I_SOUNDIC0, R_AY45L_C.2)
ALIAS(I_SOUND0, R_AY45L_A.2)
/* On M62 boards with pcb pictures available
* D6 is missing, although the pcb print exists.
* We are replacing this with a 10m Resistor.
*/
TTL_INPUT(SINH, 1)
#if 0
DIODE(D6, "1N914")
NET_C(D6.K, SINH)
ALIAS(I_SINH0, D6.A)
#else
RES(SINH_DUMMY, RES_M(10))
NET_C(SINH_DUMMY.1, SINH)
ALIAS(I_SINH0, SINH_DUMMY.2)
#endif
NET_MODEL("AY8910PORT FAMILY(OVL=0.05 OVH=4.95 ORL=100.0 ORH=0.5k)")
LOGIC_INPUT(I_SD0, 1, "AY8910PORT")
//CLOCK(I_SD0, 5)
LOGIC_INPUT(I_BD0, 1, "AY8910PORT")
//CLOCK(I_BD0, 5)
LOGIC_INPUT(I_CH0, 1, "AY8910PORT")
//CLOCK(I_CH0, 2.2 )
LOGIC_INPUT(I_OH0, 1, "AY8910PORT")
//CLOCK(I_OH0, 1.0)
ANALOG_INPUT(I_MSM2K0, 0)
ANALOG_INPUT(I_MSM3K0, 0)
INCLUDE(kidniki_schematics)
#if (USE_FRONTIERS)
OPTIMIZE_FRONTIER(C63.2, RES_K(27), RES_K(1))
OPTIMIZE_FRONTIER(R31.2, RES_K(5.1), 50)
OPTIMIZE_FRONTIER(R29.2, RES_K(2.7), 50)
OPTIMIZE_FRONTIER(R87.2, RES_K(68), 50)
OPTIMIZE_FRONTIER(R50.1, RES_K(2.2), 50)
OPTIMIZE_FRONTIER(R55.1, RES_K(510), 50)
OPTIMIZE_FRONTIER(R84.2, RES_K(50), RES_K(5))
#endif
NETLIST_END()
/*************************************
*
* Machine drivers
@ -546,7 +452,7 @@ static MACHINE_CONFIG_FRAGMENT( irem_audio_base )
/* NETLIST configuration using internal AY8910 resistor values */
MCFG_SOUND_ADD("snd_nl", NETLIST_SOUND, 48000)
MCFG_NETLIST_SETUP(kidniki_interface)
MCFG_NETLIST_SETUP(kidniki)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
MCFG_NETLIST_LOGIC_INPUT("snd_nl", "ibd", "I_BD0.IN", 0, 1)

104
src/mame/audio/nl_kidniki.inc → src/mame/audio/nl_kidniki.cpp
View File

@ -2,13 +2,8 @@
// copyright-holders:Andrew Gardner, Couriersud
#include "netlist/devices/net_lib.h"
#ifndef USE_FRONTIERS
#define USE_FRONTIERS 0
#endif
#ifndef USE_FIXED_STV
#define USE_FIXED_STV 0
#endif
#define USE_FRONTIERS 1
#define USE_FIXED_STV 1
/* ----------------------------------------------------------------------------
* Library section header START
@ -306,3 +301,98 @@ NETLIST_START(kidniki_schematics)
NET_C(R26.2, C29.2, GND)
NETLIST_END()
/* ----------------------------------------------------------------------------
* Kidniki audio
* ---------------------------------------------------------------------------*/
NETLIST_START(kidniki)
#if (USE_FRONTIERS)
SOLVER(Solver, 18000)
PARAM(Solver.ACCURACY, 1e-8)
PARAM(Solver.NR_LOOPS, 300)
PARAM(Solver.GS_LOOPS, 1)
PARAM(Solver.GS_THRESHOLD, 6)
//PARAM(Solver.ITERATIVE, "SOR")
PARAM(Solver.ITERATIVE, "MAT_CR")
//PARAM(Solver.ITERATIVE, "GMRES")
PARAM(Solver.PARALLEL, 0)
PARAM(Solver.SOR_FACTOR, 1.00)
PARAM(Solver.DYNAMIC_TS, 0)
PARAM(Solver.DYNAMIC_LTE, 5e-4)
PARAM(Solver.MIN_TIMESTEP, 20e-6)
#else
SOLVER(Solver, 12000)
PARAM(Solver.ACCURACY, 1e-8)
PARAM(Solver.NR_LOOPS, 300)
PARAM(Solver.GS_LOOPS, 20)
PARAM(Solver.ITERATIVE, "GMRES")
PARAM(Solver.PARALLEL, 0)
#endif
LOCAL_SOURCE(kidniki_schematics)
ANALOG_INPUT(I_V5, 5)
//ANALOG_INPUT(I_V0, 0)
ALIAS(I_V0.Q, GND)
/* AY 8910 internal resistors */
RES(R_AY45L_A, 1000)
RES(R_AY45L_B, 1000)
RES(R_AY45L_C, 1000)
RES(R_AY45M_A, 1000)
RES(R_AY45M_B, 1000)
RES(R_AY45M_C, 1000)
NET_C(I_V5, R_AY45L_A.1, R_AY45L_B.1, R_AY45L_C.1, R_AY45M_A.1, R_AY45M_B.1, R_AY45M_C.1)
NET_C(R_AY45L_A.2, R_AY45L_B.2, R_AY45M_A.2, R_AY45M_B.2, R_AY45M_C.2)
ALIAS(I_SOUNDIC0, R_AY45L_C.2)
ALIAS(I_SOUND0, R_AY45L_A.2)
/* On M62 boards with pcb pictures available
* D6 is missing, although the pcb print exists.
* We are replacing this with a 10m Resistor.
*/
TTL_INPUT(SINH, 1)
#if 0
DIODE(D6, "1N914")
NET_C(D6.K, SINH)
ALIAS(I_SINH0, D6.A)
#else
RES(SINH_DUMMY, RES_M(10))
NET_C(SINH_DUMMY.1, SINH)
ALIAS(I_SINH0, SINH_DUMMY.2)
#endif
NET_MODEL("AY8910PORT FAMILY(OVL=0.05 OVH=4.95 ORL=100.0 ORH=0.5k)")
LOGIC_INPUT(I_SD0, 1, "AY8910PORT")
//CLOCK(I_SD0, 5)
LOGIC_INPUT(I_BD0, 1, "AY8910PORT")
//CLOCK(I_BD0, 5)
LOGIC_INPUT(I_CH0, 1, "AY8910PORT")
//CLOCK(I_CH0, 2.2 )
LOGIC_INPUT(I_OH0, 1, "AY8910PORT")
//CLOCK(I_OH0, 1.0)
ANALOG_INPUT(I_MSM2K0, 0)
ANALOG_INPUT(I_MSM3K0, 0)
INCLUDE(kidniki_schematics)
#if (USE_FRONTIERS)
OPTIMIZE_FRONTIER(C63.2, RES_K(27), RES_K(1))
OPTIMIZE_FRONTIER(R31.2, RES_K(5.1), 50)
OPTIMIZE_FRONTIER(R29.2, RES_K(2.7), 50)
OPTIMIZE_FRONTIER(R87.2, RES_K(68), 50)
OPTIMIZE_FRONTIER(R50.1, RES_K(2.2), 50)
OPTIMIZE_FRONTIER(R55.1, RES_K(510), 50)
OPTIMIZE_FRONTIER(R84.2, RES_K(50), RES_K(5))
#endif
NETLIST_END()