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srcclean (nw)

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This commit is contained in:
Curt Coder 2012-10-07 09:12:56 +00:00
parent 1f1557407c
commit 31387945c8
143 changed files with 1160 additions and 1160 deletions
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2
src/emu/clifront.c
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@ -1283,7 +1283,7 @@ void cli_frontend::listsoftware(const char *gamename)
/*-------------------------------------------------
verifysoftware - verify roms from the software
verifysoftware - verify roms from the software
list of the specified driver(s)
-------------------------------------------------*/
void cli_frontend::verifysoftware(const char *gamename)

6
src/emu/devdelegate.c
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@ -42,8 +42,8 @@
//-------------------------------------------------
// bound_object - use the device name to locate
// a device relative to the given search root;
// fatal error if not found
// a device relative to the given search root;
// fatal error if not found
//-------------------------------------------------
delegate_late_bind &device_delegate_helper::bound_object(device_t &search_root)
@ -57,7 +57,7 @@ delegate_late_bind &device_delegate_helper::bound_object(device_t &search_root)
//-------------------------------------------------
// safe_tag - return a tag string or (unknown) if
// the object is not valid
// the object is not valid
//-------------------------------------------------
const char *device_delegate_helper::safe_tag(device_t *object)

2
src/emu/driver.c
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@ -42,7 +42,7 @@
//**************************************************************************
// ADDRESS_MAPS
// ADDRESS_MAPS
//**************************************************************************
// default address map

2
src/emu/driver.h
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@ -166,7 +166,7 @@ typedef void (*legacy_callback_func)(running_machine &machine);
// ======================> driver_device
// base class for machine driver-specific devices
class driver_device : public device_t,
class driver_device : public device_t,
public device_memory_interface
{
public:

4
src/emu/machine/53c810.c
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@ -393,7 +393,7 @@ void lsi53c810_device::dma_exec()
UINT8 lsi53c810_device::lsi53c810_reg_r( int offset )
{
// logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, space.device().safe_pc());
// logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, space.device().safe_pc());
switch(offset)
{
case 0x00: /* SCNTL0 */
@ -476,7 +476,7 @@ UINT8 lsi53c810_device::lsi53c810_reg_r( int offset )
void lsi53c810_device::lsi53c810_reg_w(int offset, UINT8 data)
{
// logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, space.device().safe_pc());
// logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, space.device().safe_pc());
switch(offset)
{
case 0x00: /* SCNTL0 */

36
src/emu/machine/mos6526.c
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@ -9,17 +9,17 @@
/*
TODO:
TODO:
- pass Lorenz test suite 2.15
- ICR01
- IMR
- CIA1TA/TB
- CIA2TA/TB
- pass VICE cia tests
- 8520 read/write
- 5710 read/write
- optimize
- pass Lorenz test suite 2.15
- ICR01
- IMR
- CIA1TA/TB
- CIA2TA/TB
- pass VICE cia tests
- 8520 read/write
- 5710 read/write
- optimize
*/
@ -79,13 +79,13 @@ enum
#define CRA_START 0x01
#define CRA_STARTED BIT(m_cra, 0)
#define CRA_PBON BIT(m_cra, 1)
#define CRA_PBON BIT(m_cra, 1)
#define CRA_OUTMODE BIT(m_cra, 2)
#define CRA_RUNMODE BIT(m_cra, 3)
#define CRA_LOAD BIT(m_cra, 4)
#define CRA_INMODE BIT(m_cra, 5)
#define CRA_SPMODE BIT(m_cra, 6)
#define CRA_TODIN BIT(m_cra, 7)
#define CRA_INMODE BIT(m_cra, 5)
#define CRA_SPMODE BIT(m_cra, 6)
#define CRA_TODIN BIT(m_cra, 7)
// control register B
@ -99,12 +99,12 @@ enum
#define CRB_START 0x01
#define CRB_STARTED BIT(m_crb, 0)
#define CRB_PBON BIT(m_crb, 1)
#define CRB_PBON BIT(m_crb, 1)
#define CRB_OUTMODE BIT(m_crb, 2)
#define CRB_RUNMODE BIT(m_crb, 3)
#define CRB_LOAD BIT(m_crb, 4)
#define CRB_INMODE ((m_crb & 0x60) >> 5)
#define CRB_ALARM BIT(m_crb, 7)
#define CRB_LOAD BIT(m_crb, 4)
#define CRB_INMODE ((m_crb & 0x60) >> 5)
#define CRB_ALARM BIT(m_crb, 7)

16
src/emu/machine/seibu_cop.c
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@ -178,13 +178,13 @@ WRITE16_MEMBER(seibu_cop_device::pal_brightness_mode_w)
WRITE16_MEMBER(seibu_cop_device::dma_unk_param_w)
{
/*
This sets up a DMA mode of some sort
0x0e00: grainbow, cupsoc
0x0a00: legionna, godzilla, denjinmk
0x0600: heatbrl
0x1e00: zeroteam, xsedae
raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs
(both only uses 0x14 and 0x15 as DMAs afaik)
This sets up a DMA mode of some sort
0x0e00: grainbow, cupsoc
0x0a00: legionna, godzilla, denjinmk
0x0600: heatbrl
0x1e00: zeroteam, xsedae
raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs
(both only uses 0x14 and 0x15 as DMAs afaik)
*/
COMBINE_DATA(&m_dma_unk_param);
}
@ -271,7 +271,7 @@ void seibu_cop_device::palette_dma_transfer(void)
0x86 is used by Seibu Cup Soccer
0x87 is used by Denjin Makai
TODO:
TODO:
- Denjin Makai mode 4 is totally guessworked.
- SD Gundam doesn't fade colors correctly, it should have the text layer / sprites with normal gradient and the rest dimmed in most cases,
presumably bad RAM table or bad algorithm

4
src/emu/video/tms9928a.c
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@ -97,7 +97,7 @@ tms9928a_device::tms9928a_device( const machine_config &mconfig, device_type typ
{
m_50hz = is_50hz;
m_reva = is_reva;
// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
}
@ -108,7 +108,7 @@ tms9928a_device::tms9928a_device( const machine_config &mconfig, const char *tag
{
m_50hz = false;
m_reva = true;
// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
}

32
src/mame/drivers/8080bw.c
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@ -2358,23 +2358,23 @@ INPUT_CHANGED_MEMBER(_8080bw_state::claybust_gun_trigger)
if (newval)
{
/*
The game registers a valid shot after the gun trigger is pressed, and IN1 d0 is high.
It latches the gun position and then compares it with VRAM contents: 1 byte/8 pixels, 0 means miss.
IN1 d0 probably indicates if the latch is ready or not (glitches happen otherwise)
The game registers a valid shot after the gun trigger is pressed, and IN1 d0 is high.
It latches the gun position and then compares it with VRAM contents: 1 byte/8 pixels, 0 means miss.
IN1 d0 probably indicates if the latch is ready or not (glitches happen otherwise)
in $06
cpi $04
rc
mov h,a
in $02
mov l,a
lxi d,$1ffe <-- this is where the +2 comes from
dad d
out $00
mov a,m
ana a
rz
*/
in $06
cpi $04
rc
mov h,a
in $02
mov l,a
lxi d,$1ffe <-- this is where the +2 comes from
dad d
out $00
mov a,m
ana a
rz
*/
UINT8 gunx = ioport("GUNX")->read_safe(0x00);
UINT8 guny = ioport("GUNY")->read_safe(0x20);
m_claybust_gun_pos = ((gunx >> 3) | (guny << 5)) + 2;

2
src/mame/drivers/cd32.c
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@ -1475,7 +1475,7 @@ DRIVER_INIT_MEMBER(cd32_state,odeontw2)
/***************************************************************************************************/
// these are clones of the cd32 SYSTEM because they run on a stock retail unit, with additional HW
GAME( 1993, cd32bios, 0, cd32base, cd32, cd32_state, cd32, ROT0, "Commodore Business Machines", "CD32 Bios", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND | GAME_IS_BIOS_ROOT )
GAME( 1993, cd32bios, 0, cd32base, cd32, cd32_state, cd32, ROT0, "Commodore Business Machines", "CD32 Bios", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND | GAME_IS_BIOS_ROOT )
GAME( 1995, cndypuzl, cd32bios, cd32base, cndypuzl, cd32_state, cndypuzl, ROT0, "CD Express", "Candy Puzzle (v1.0)", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAME( 1995, haremchl, cd32bios, cd32base, haremchl, cd32_state, haremchl, ROT0, "CD Express", "Harem Challenge", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND )
GAME( 1995, lsrquiz, cd32bios, cd32base, lsrquiz, cd32_state, lsrquiz, ROT0, "CD Express", "Laser Quiz Italy", GAME_IMPERFECT_GRAPHICS|GAME_IMPERFECT_SOUND ) /* no player 2 inputs (ingame) */

2
src/mame/drivers/cdi.c
View File

@ -625,7 +625,7 @@ CONS( 1991, cdimono1, 0, 0, cdimono1, cdi, driver_device, 0,
// The Quizard games are RETAIL CD-i units, with additional JAMMA adapters & dongles for protection, hence being 'clones' of the system.
GAME( 1995, cdibios, 0, cdi_base, quizard, driver_device, 0, ROT0, "Philips", "CD-i Bios", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS | GAME_IS_BIOS_ROOT )
GAME( 1995, cdibios, 0, cdi_base, quizard, driver_device, 0, ROT0, "Philips", "CD-i Bios", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS | GAME_IS_BIOS_ROOT )
// Working
GAME( 1995, quizrd12, cdibios, quizrd12, quizard, driver_device, 0, ROT0, "TAB Austria", "Quizard 1.2", GAME_IMPERFECT_SOUND | GAME_UNEMULATED_PROTECTION )
GAME( 1995, quizrd17, cdibios, quizrd17, quizard, driver_device, 0, ROT0, "TAB Austria", "Quizard 1.7", GAME_IMPERFECT_SOUND | GAME_UNEMULATED_PROTECTION )

8
src/mame/drivers/cps1.c
View File

@ -3063,10 +3063,10 @@ static MACHINE_CONFIG_START( cps1_10MHz, cps_state )
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(59.61) /* verified on one of the input gates of the 74ls08@4J on GNG romboard 88620-b-2 */
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
// MCFG_SCREEN_SIZE(64*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(8*8, (64-8)*8-1, 2*8, 30*8-1 )
// MCFG_SCREEN_REFRESH_RATE(59.61) /* verified on one of the input gates of the 74ls08@4J on GNG romboard 88620-b-2 */
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
// MCFG_SCREEN_SIZE(64*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(8*8, (64-8)*8-1, 2*8, 30*8-1 )
MCFG_SCREEN_RAW_PARAMS(XTAL_16MHz/2, 518, 64, 448, 259, 16, 240) /* guess: assume that CPS-1 uses the same exact timings as CPS-2 */
MCFG_SCREEN_UPDATE_DRIVER(cps_state, screen_update_cps1)
MCFG_SCREEN_VBLANK_DRIVER(cps_state, screen_eof_cps1)

554
src/mame/drivers/gammagic.c
View File

@ -221,324 +221,324 @@ static I8237_INTERFACE( dma8237_2_config )
/*
static READ32_HANDLER( atapi_r )
{
gammagic_state *state = space.machine().driver_data<gammagic_state>();
UINT8 *atapi_regs = state->m_atapi_regs;
//running_machine &machine = space.machine();
int reg, data;
gammagic_state *state = space.machine().driver_data<gammagic_state>();
UINT8 *atapi_regs = state->m_atapi_regs;
//running_machine &machine = space.machine();
int reg, data;
if (mem_mask == 0x0000ffff) // word-wide command read
{
if (mem_mask == 0x0000ffff) // word-wide command read
{
logerror("ATAPI: packet read = %04x\n", state->m_atapi_data[state->m_atapi_data_ptr]);
// assert IRQ and drop DRQ
if (state->m_atapi_data_ptr == 0 && state->m_atapi_data_len == 0)
{
// get the data from the device
if( state->m_atapi_xferlen > 0 )
{
SCSIReadData( state->m_inserted_cdrom, state->m_atapi_data, state->m_atapi_xferlen );
state->m_atapi_data_len = state->m_atapi_xferlen;
}
// assert IRQ and drop DRQ
if (state->m_atapi_data_ptr == 0 && state->m_atapi_data_len == 0)
{
// get the data from the device
if( state->m_atapi_xferlen > 0 )
{
SCSIReadData( state->m_inserted_cdrom, state->m_atapi_data, state->m_atapi_xferlen );
state->m_atapi_data_len = state->m_atapi_xferlen;
}
if (state->m_atapi_xfermod > MAX_TRANSFER_SIZE)
{
state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
state->m_atapi_xfermod = state->m_atapi_xfermod - MAX_TRANSFER_SIZE;
}
else
{
state->m_atapi_xferlen = state->m_atapi_xfermod;
state->m_atapi_xfermod = 0;
}
if (state->m_atapi_xfermod > MAX_TRANSFER_SIZE)
{
state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
state->m_atapi_xfermod = state->m_atapi_xfermod - MAX_TRANSFER_SIZE;
}
else
{
state->m_atapi_xferlen = state->m_atapi_xfermod;
state->m_atapi_xfermod = 0;
}
//verboselog\\( machine, 2, "atapi_r: atapi_xferlen=%d\n", state->m_atapi_xferlen );
if( state->m_atapi_xferlen != 0 )
{
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_SERVDSC;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
}
else
{
logerror("ATAPI: dropping DRQ\n");
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
}
//verboselog\\( machine, 2, "atapi_r: atapi_xferlen=%d\n", state->m_atapi_xferlen );
if( state->m_atapi_xferlen != 0 )
{
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_SERVDSC;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
}
else
{
logerror("ATAPI: dropping DRQ\n");
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
}
atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
atapi_irq(space.machine(), ASSERT_LINE);
}
atapi_irq(space.machine(), ASSERT_LINE);
}
if( state->m_atapi_data_ptr < state->m_atapi_data_len )
{
data = state->m_atapi_data[state->m_atapi_data_ptr++];
data |= ( state->m_atapi_data[state->m_atapi_data_ptr++] << 8 );
if( state->m_atapi_data_ptr >= state->m_atapi_data_len )
{
if( state->m_atapi_data_ptr < state->m_atapi_data_len )
{
data = state->m_atapi_data[state->m_atapi_data_ptr++];
data |= ( state->m_atapi_data[state->m_atapi_data_ptr++] << 8 );
if( state->m_atapi_data_ptr >= state->m_atapi_data_len )
{
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
if( state->m_atapi_xferlen == 0 )
{
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
atapi_irq(space.machine(), ASSERT_LINE);
}
}
}
else
{
data = 0;
}
}
else
{
atapi_irq(space.machine(), CLEAR_LINE);
int shift;
shift = 0;
reg = offset<<2;
switch(mem_mask)
{
case 0x000000ff:
break;
case 0x0000ff00:
reg+=1;
data >>= 8;
shift=8;
break;
case 0x00ff0000:
reg+=2;
data >>=16;
shift=16;
break;
case 0xff000000:
reg+=3;
data >>=24;
shift=24;
break;
}
data = atapi_regs[reg];
data <<= shift;
}
return data;
if( state->m_atapi_xferlen == 0 )
{
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
atapi_irq(space.machine(), ASSERT_LINE);
}
}
}
else
{
data = 0;
}
}
else
{
atapi_irq(space.machine(), CLEAR_LINE);
int shift;
shift = 0;
reg = offset<<2;
switch(mem_mask)
{
case 0x000000ff:
break;
case 0x0000ff00:
reg+=1;
data >>= 8;
shift=8;
break;
case 0x00ff0000:
reg+=2;
data >>=16;
shift=16;
break;
case 0xff000000:
reg+=3;
data >>=24;
shift=24;
break;
}
data = atapi_regs[reg];
data <<= shift;
}
return data;
}
static WRITE32_HANDLER( atapi_w )
{
gammagic_state *state = space.machine().driver_data<gammagic_state>();
UINT8 *atapi_regs = state->m_atapi_regs;
UINT8 *atapi_data = state->m_atapi_data;
int reg;
if (mem_mask == 0x0000ffff) // word-wide command write
{
atapi_data[state->m_atapi_data_ptr++] = data & 0xff;
atapi_data[state->m_atapi_data_ptr++] = data >> 8;
gammagic_state *state = space.machine().driver_data<gammagic_state>();
UINT8 *atapi_regs = state->m_atapi_regs;
UINT8 *atapi_data = state->m_atapi_data;
int reg;
if (mem_mask == 0x0000ffff) // word-wide command write
{
atapi_data[state->m_atapi_data_ptr++] = data & 0xff;
atapi_data[state->m_atapi_data_ptr++] = data >> 8;
if (state->m_atapi_cdata_wait)
{
logerror("ATAPI: waiting, ptr %d wait %d\n", state->m_atapi_data_ptr, state->m_atapi_cdata_wait);
if (state->m_atapi_data_ptr == state->m_atapi_cdata_wait)
{
// send it to the device
SCSIWriteData( state->m_inserted_cdrom, atapi_data, state->m_atapi_cdata_wait );
if (state->m_atapi_cdata_wait)
{
logerror("ATAPI: waiting, ptr %d wait %d\n", state->m_atapi_data_ptr, state->m_atapi_cdata_wait);
if (state->m_atapi_data_ptr == state->m_atapi_cdata_wait)
{
// send it to the device
SCSIWriteData( state->m_inserted_cdrom, atapi_data, state->m_atapi_cdata_wait );
// assert IRQ
atapi_irq(space.machine(), ASSERT_LINE);
// assert IRQ
atapi_irq(space.machine(), ASSERT_LINE);
// not sure here, but clear DRQ at least?
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
}
}
// not sure here, but clear DRQ at least?
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
}
}
else if ( state->m_atapi_data_ptr == 12 )
{
int phase;
// reset data pointer for reading SCSI results
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
else if ( state->m_atapi_data_ptr == 12 )
{
int phase;
// reset data pointer for reading SCSI results
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
// send it to the SCSI device
SCSISetCommand( state->m_inserted_cdrom, state->m_atapi_data, 12 );
SCSIExecCommand( state->m_inserted_cdrom, &state->m_atapi_xferlen );
SCSIGetPhase( state->m_inserted_cdrom, &phase );
// send it to the SCSI device
SCSISetCommand( state->m_inserted_cdrom, state->m_atapi_data, 12 );
SCSIExecCommand( state->m_inserted_cdrom, &state->m_atapi_xferlen );
SCSIGetPhase( state->m_inserted_cdrom, &phase );
if (state->m_atapi_xferlen != -1)
{
logerror("ATAPI: SCSI command %02x returned %d bytes from the device\n", atapi_data[0]&0xff, state->m_atapi_xferlen);
if (state->m_atapi_xferlen != -1)
{
logerror("ATAPI: SCSI command %02x returned %d bytes from the device\n", atapi_data[0]&0xff, state->m_atapi_xferlen);
// store the returned command length in the ATAPI regs, splitting into
// multiple transfers if necessary
state->m_atapi_xfermod = 0;
if (state->m_atapi_xferlen > MAX_TRANSFER_SIZE)
{
state->m_atapi_xfermod = state->m_atapi_xferlen - MAX_TRANSFER_SIZE;
state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
}
// store the returned command length in the ATAPI regs, splitting into
// multiple transfers if necessary
state->m_atapi_xfermod = 0;
if (state->m_atapi_xferlen > MAX_TRANSFER_SIZE)
{
state->m_atapi_xfermod = state->m_atapi_xferlen - MAX_TRANSFER_SIZE;
state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
}
atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
if (state->m_atapi_xferlen == 0)
{
// if no data to return, set the registers properly
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRDY;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO|ATAPI_INTREASON_COMMAND;
}
else
{
// indicate data ready: set DRQ and DMA ready, and IO in INTREASON
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_SERVDSC;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
}
if (state->m_atapi_xferlen == 0)
{
// if no data to return, set the registers properly
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRDY;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO|ATAPI_INTREASON_COMMAND;
}
else
{
// indicate data ready: set DRQ and DMA ready, and IO in INTREASON
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_SERVDSC;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
}
switch( phase )
{
case SCSI_PHASE_DATAOUT:
state->m_atapi_cdata_wait = state->m_atapi_xferlen;
break;
}
switch( phase )
{
case SCSI_PHASE_DATAOUT:
state->m_atapi_cdata_wait = state->m_atapi_xferlen;
break;
}
// perform special ATAPI processing of certain commands
switch (atapi_data[0]&0xff)
{
case 0x00: // BUS RESET / TEST UNIT READY
case 0xbb: // SET CDROM SPEED
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
break;
// perform special ATAPI processing of certain commands
switch (atapi_data[0]&0xff)
{
case 0x00: // BUS RESET / TEST UNIT READY
case 0xbb: // SET CDROM SPEED
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
break;
case 0x45: // PLAY
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_BSY;
state->m_atapi_timer->adjust( downcast<cpu_device *>(&space->device())->cycles_to_attotime( ATAPI_CYCLES_PER_SECTOR ) );
break;
}
case 0x45: // PLAY
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_BSY;
state->m_atapi_timer->adjust( downcast<cpu_device *>(&space->device())->cycles_to_attotime( ATAPI_CYCLES_PER_SECTOR ) );
break;
}
// assert IRQ
atapi_irq(space.machine(), ASSERT_LINE);
}
else
{
logerror("ATAPI: SCSI device returned error!\n");
// assert IRQ
atapi_irq(space.machine(), ASSERT_LINE);
}
else
{
logerror("ATAPI: SCSI device returned error!\n");
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_CHECK;
atapi_regs[ATAPI_REG_ERRFEAT] = 0x50; // sense key = ILLEGAL REQUEST
atapi_regs[ATAPI_REG_COUNTLOW] = 0;
atapi_regs[ATAPI_REG_COUNTHIGH] = 0;
}
}
}
else
{
reg = offset<<2;
switch(mem_mask)
{
case 0x000000ff:
break;
case 0x0000ff00:
reg+=1;
data >>= 8;
break;
case 0x00ff0000:
reg+=2;
data >>=16;
break;
case 0xff000000:
reg+=3;
data >>=24;
break;
}
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_CHECK;
atapi_regs[ATAPI_REG_ERRFEAT] = 0x50; // sense key = ILLEGAL REQUEST
atapi_regs[ATAPI_REG_COUNTLOW] = 0;
atapi_regs[ATAPI_REG_COUNTHIGH] = 0;
}
}
}
else
{
reg = offset<<2;
switch(mem_mask)
{
case 0x000000ff:
break;
case 0x0000ff00:
reg+=1;
data >>= 8;
break;
case 0x00ff0000:
reg+=2;
data >>=16;
break;
case 0xff000000:
reg+=3;
data >>=24;
break;
}
atapi_regs[reg] = data;
logerror("ATAPI: reg %d = %x (offset %x mask %x PC=%x)\n", reg, data, offset, mem_mask, cpu_get_pc(&space->device()));
atapi_regs[reg] = data;
logerror("ATAPI: reg %d = %x (offset %x mask %x PC=%x)\n", reg, data, offset, mem_mask, cpu_get_pc(&space->device()));
if (reg == ATAPI_REG_CMDSTATUS)
{
logerror("ATAPI command %x issued! (PC=%x)\n", data, cpu_get_pc(&space->device()));
switch (data)
{
case 0xa0: // PACKET
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_COMMAND;
if (reg == ATAPI_REG_CMDSTATUS)
{
logerror("ATAPI command %x issued! (PC=%x)\n", data, cpu_get_pc(&space->device()));
switch (data)
{
case 0xa0: // PACKET
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_COMMAND;
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
// we have no data
state->m_atapi_xferlen = 0;
state->m_atapi_xfermod = 0;
// we have no data
state->m_atapi_xferlen = 0;
state->m_atapi_xfermod = 0;
state->m_atapi_cdata_wait = 0;
break;
state->m_atapi_cdata_wait = 0;
break;
case 0xa1: // IDENTIFY PACKET DEVICE
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
case 0xa1: // IDENTIFY PACKET DEVICE
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 512;
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 512;
// we have no data
state->m_atapi_xferlen = 0;
state->m_atapi_xfermod = 0;
// we have no data
state->m_atapi_xferlen = 0;
state->m_atapi_xfermod = 0;
memset( atapi_data, 0, state->m_atapi_data_len );
memset( atapi_data, 0, state->m_atapi_data_len );
atapi_data[ 0 ^ 1 ] = 0x85; // ATAPI device, cmd set 5 compliant, DRQ within 3 ms of PACKET command
atapi_data[ 1 ^ 1 ] = 0x80; // ATAPI device, removable media
atapi_data[ 0 ^ 1 ] = 0x85; // ATAPI device, cmd set 5 compliant, DRQ within 3 ms of PACKET command
atapi_data[ 1 ^ 1 ] = 0x80; // ATAPI device, removable media
memset( &atapi_data[ 46 ], ' ', 8 );
atapi_data[ 46 ^ 1 ] = '1';
atapi_data[ 47 ^ 1 ] = '.';
atapi_data[ 48 ^ 1 ] = '0';
memset( &atapi_data[ 46 ], ' ', 8 );
atapi_data[ 46 ^ 1 ] = '1';
atapi_data[ 47 ^ 1 ] = '.';
atapi_data[ 48 ^ 1 ] = '0';
memset( &atapi_data[ 54 ], ' ', 40 );
atapi_data[ 54 ^ 1 ] = 'T';
atapi_data[ 55 ^ 1 ] = 'O';
atapi_data[ 56 ^ 1 ] = 'S';
atapi_data[ 57 ^ 1 ] = 'H';
atapi_data[ 58 ^ 1 ] = 'I';
atapi_data[ 59 ^ 1 ] = 'B';
atapi_data[ 60 ^ 1 ] = 'A';
atapi_data[ 61 ^ 1 ] = ' ';
atapi_data[ 62 ^ 1 ] = 'X';
atapi_data[ 63 ^ 1 ] = 'M';
atapi_data[ 64 ^ 1 ] = '-';
atapi_data[ 65 ^ 1 ] = '3';
atapi_data[ 66 ^ 1 ] = '3';
atapi_data[ 67 ^ 1 ] = '0';
atapi_data[ 68 ^ 1 ] = '1';
atapi_data[ 69 ^ 1 ] = ' ';
memset( &atapi_data[ 54 ], ' ', 40 );
atapi_data[ 54 ^ 1 ] = 'T';
atapi_data[ 55 ^ 1 ] = 'O';
atapi_data[ 56 ^ 1 ] = 'S';
atapi_data[ 57 ^ 1 ] = 'H';
atapi_data[ 58 ^ 1 ] = 'I';
atapi_data[ 59 ^ 1 ] = 'B';
atapi_data[ 60 ^ 1 ] = 'A';
atapi_data[ 61 ^ 1 ] = ' ';
atapi_data[ 62 ^ 1 ] = 'X';
atapi_data[ 63 ^ 1 ] = 'M';
atapi_data[ 64 ^ 1 ] = '-';
atapi_data[ 65 ^ 1 ] = '3';
atapi_data[ 66 ^ 1 ] = '3';
atapi_data[ 67 ^ 1 ] = '0';
atapi_data[ 68 ^ 1 ] = '1';
atapi_data[ 69 ^ 1 ] = ' ';
atapi_data[ 98 ^ 1 ] = 0x06; // Word 49=Capabilities, IORDY may be disabled (bit_10), LBA Supported mandatory (bit_9)
atapi_data[ 99 ^ 1 ] = 0x00;
atapi_data[ 98 ^ 1 ] = 0x06; // Word 49=Capabilities, IORDY may be disabled (bit_10), LBA Supported mandatory (bit_9)
atapi_data[ 99 ^ 1 ] = 0x00;
atapi_regs[ATAPI_REG_COUNTLOW] = 0;
atapi_regs[ATAPI_REG_COUNTHIGH] = 2;
atapi_regs[ATAPI_REG_COUNTLOW] = 0;
atapi_regs[ATAPI_REG_COUNTHIGH] = 2;
atapi_irq(space.machine(), ASSERT_LINE);
break;
case 0xec: //IDENTIFY DEVICE - Must abort here and set for packet data
atapi_regs[ATAPI_REG_ERRFEAT] = ATAPI_ERRFEAT_ABRT;
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_CHECK;
atapi_irq(space.machine(), ASSERT_LINE);
break;
case 0xec: //IDENTIFY DEVICE - Must abort here and set for packet data
atapi_regs[ATAPI_REG_ERRFEAT] = ATAPI_ERRFEAT_ABRT;
atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_CHECK;
atapi_irq(space.machine(), ASSERT_LINE);
atapi_irq(space.machine(), ASSERT_LINE);
case 0xef: // SET FEATURES
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
case 0xef: // SET FEATURES
atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
state->m_atapi_data_ptr = 0;
state->m_atapi_data_len = 0;
atapi_irq(space.machine(), ASSERT_LINE);
break;
atapi_irq(space.machine(), ASSERT_LINE);
break;
default:
logerror("ATAPI: Unknown IDE command %x\n", data);
break;
}
}
}
default:
logerror("ATAPI: Unknown IDE command %x\n", data);
break;
}
}
}
}
*/
// Memory is mostly handled by the chipset
@ -652,14 +652,14 @@ static MACHINE_RESET( gammagic )
/*static void atapi_irq(running_machine &machine, int state)
{
gammagic_state *drvstate = machine.driver_data<gammagic_state>();
pic8259_ir6_w(drvstate->m_pic8259_2, state);
gammagic_state *drvstate = machine.driver_data<gammagic_state>();
pic8259_ir6_w(drvstate->m_pic8259_2, state);
}
static void atapi_exit(running_machine& machine)
{
gammagic_state *state = machine.driver_data<gammagic_state>();
SCSIDeleteInstance(state->m_inserted_cdrom);
gammagic_state *state = machine.driver_data<gammagic_state>();
SCSIDeleteInstance(state->m_inserted_cdrom);
}
*/
@ -782,11 +782,11 @@ static MACHINE_CONFIG_START( gammagic, gammagic_state )
MCFG_PIC8259_ADD( "pic8259_1", gammagic_pic8259_1_config )
MCFG_PIC8259_ADD( "pic8259_2", gammagic_pic8259_2_config )
MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
// MCFG_I82371SB_ADD("i82371sb")
// MCFG_I82439TX_ADD("i82439tx", "maincpu", "user")
// MCFG_I82371SB_ADD("i82371sb")
// MCFG_I82439TX_ADD("i82439tx", "maincpu", "user")
MCFG_PCI_BUS_ADD("pcibus", 0)
// MCFG_PCI_BUS_DEVICE(0, "i82439tx", i82439tx_pci_read, i82439tx_pci_write)
// MCFG_PCI_BUS_DEVICE(1, "i82371sb", i82371sb_pci_read, i82371sb_pci_write)
// MCFG_PCI_BUS_DEVICE(0, "i82439tx", i82439tx_pci_read, i82439tx_pci_write)
// MCFG_PCI_BUS_DEVICE(1, "i82371sb", i82371sb_pci_read, i82371sb_pci_write)
/* video hardware */
MCFG_FRAGMENT_ADD( pcvideo_vga )

4
src/mame/drivers/intrscti.c
View File

@ -90,12 +90,12 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( intrscti_sub_map, AS_PROGRAM, 8, intrscti_state )
AM_RANGE(0x0000, 0x07ff) AM_ROM
AM_RANGE(0x2000, 0x23ff) AM_RAM
// AM_RANGE(0x0000, 0xffff) AM_WRITENOP
// AM_RANGE(0x0000, 0xffff) AM_WRITENOP
ADDRESS_MAP_END
static ADDRESS_MAP_START( intrscti_sub_io_map, AS_IO, 8, intrscti_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
// AM_RANGE(0x00, 0xff) AM_NOP
// AM_RANGE(0x00, 0xff) AM_NOP
ADDRESS_MAP_END

6
src/mame/drivers/jpmsys5.c
View File

@ -13,9 +13,9 @@
Known Issues:
* Some features used by the AWP games such as reels and meters
are not emulated.
* Timing for reels, and other opto devices is controlled by the same clock
as the lamps, in a weird daisychain setup.
are not emulated.
* Timing for reels, and other opto devices is controlled by the same clock
as the lamps, in a weird daisychain setup.
AWP game notes:
The byte at 0x81 of the EVEN 68k rom appears to be some kind of

2
src/mame/drivers/pipedrm.c
View File

@ -191,7 +191,7 @@ static WRITE8_HANDLER( pipedrm_bankswitch_w )
state->membank("bank1")->set_entry(data & 0x7);
/* map to the fromance gfx register */
state->fromance_gfxreg_w(space, offset, ((data >> 6) & 0x01) | /* flipscreen */
state->fromance_gfxreg_w(space, offset, ((data >> 6) & 0x01) | /* flipscreen */
((~data >> 2) & 0x02)); /* videoram select */
}

2
src/mame/drivers/raiden2.c
View File

@ -1924,7 +1924,7 @@ static MACHINE_CONFIG_START( zeroteam, raiden2_state )
MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK)
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(55.47) /* verified on pcb */
// MCFG_SCREEN_REFRESH_RATE(55.47) /* verified on pcb */
MCFG_SCREEN_RAW_PARAMS(XTAL_32MHz/4,546,0,40*8,264,0,32*8) /* hand-tuned to match ~55.47 */
MCFG_SCREEN_UPDATE_DRIVER(raiden2_state, screen_update_raiden2)
MCFG_GFXDECODE(raiden2)

8
src/mame/drivers/shangha3.c
View File

@ -557,10 +557,10 @@ static MACHINE_CONFIG_START( blocken, shangha3_state )
MCFG_VIDEO_ATTRIBUTES(VIDEO_HAS_SHADOWS)
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(60)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
// MCFG_SCREEN_SIZE(24*16, 16*16)
// MCFG_SCREEN_VISIBLE_AREA(0*16, 24*16-1, 1*16, 15*16-1)
// MCFG_SCREEN_REFRESH_RATE(60)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
// MCFG_SCREEN_SIZE(24*16, 16*16)
// MCFG_SCREEN_VISIBLE_AREA(0*16, 24*16-1, 1*16, 15*16-1)
MCFG_SCREEN_RAW_PARAMS(BLOCKEN_MASTER_CLOCK/6,512,0,24*16,263,1*16,15*16) /* refresh rate is unknown */
MCFG_SCREEN_UPDATE_DRIVER(shangha3_state, screen_update_shangha3)

32
src/mame/drivers/spectra.c
View File

@ -212,22 +212,22 @@ TIMER_DEVICE_CALLBACK_MEMBER( spectra_state::outtimer)
static const sn76477_interface sn76477_intf =
{
RES_M(1000), /* 4 noise_res */
RES_M(1000), /* 5 filter_res */
CAP_N(0), /* 6 filter_cap */
RES_K(470), /* 7 decay_res */
CAP_N(1), /* 8 attack_decay_cap */
RES_K(22), /* 10 attack_res */
RES_K(100), /* 11 amplitude_res */
RES_K(52), /* 12 feedback_res */
5.0, /* 16 vco_voltage */
CAP_U(0.01), /* 17 vco_cap */
RES_K(390), /* 18 vco_res */
0.0, /* 19 pitch_voltage */
RES_M(1), /* 20 slf_res */
CAP_U(0.1), /* 21 slf_cap */
CAP_U(0.47), /* 23 oneshot_cap */
RES_K(470), /* 24 oneshot_res */
RES_M(1000), /* 4 noise_res */
RES_M(1000), /* 5 filter_res */
CAP_N(0), /* 6 filter_cap */
RES_K(470), /* 7 decay_res */
CAP_N(1), /* 8 attack_decay_cap */
RES_K(22), /* 10 attack_res */
RES_K(100), /* 11 amplitude_res */
RES_K(52), /* 12 feedback_res */
5.0, /* 16 vco_voltage */
CAP_U(0.01), /* 17 vco_cap */
RES_K(390), /* 18 vco_res */
0.0, /* 19 pitch_voltage */
RES_M(1), /* 20 slf_res */
CAP_U(0.1), /* 21 slf_cap */
CAP_U(0.47), /* 23 oneshot_cap */
RES_K(470), /* 24 oneshot_res */
0, /* 22 vco (variable) */
0, /* 26 mixer A (grounded) */
0, /* 25 mixer B (variable) */

18
src/mame/drivers/vicdual.c
View File

@ -921,7 +921,7 @@ static INPUT_PORTS_START( digger )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("IN2")
// PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_timer_value, NULL) // it's like this according to the schematics, but gameplay speed is too fast;
// PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_timer_value, NULL) // it's like this according to the schematics, but gameplay speed is too fast;
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_composite_blank_comp, NULL) // gameplay speed is correct now, there's likely an error in the schematics then...
PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_read_coin_status, NULL)
@ -1278,7 +1278,7 @@ static INPUT_PORTS_START( invho2 )
PORT_DIPNAME( 0x03, 0x01, "Head On 2 Lives" ) PORT_DIPLOCATION("SW1:1,2")
PORT_DIPSETTING( 0x00, "2" )
PORT_DIPSETTING( 0x01, "3" )
// PORT_DIPSETTING( 0x02, "3" ) // dupe
// PORT_DIPSETTING( 0x02, "3" ) // dupe
PORT_DIPSETTING( 0x03, "4" )
/* There's probably a bug in the Invinco game code:
@ -1290,8 +1290,8 @@ static INPUT_PORTS_START( invho2 )
PORT_DIPNAME( 0x03, 0x03, "Invinco Lives" ) PORT_DIPLOCATION("SW1:3,4")
PORT_DIPSETTING( 0x03, "3" )
PORT_DIPSETTING( 0x02, "4" )
// PORT_DIPSETTING( 0x01, "5" ) // results in 3, see above
// PORT_DIPSETTING( 0x00, "6" ) // results in 4, see above
// PORT_DIPSETTING( 0x01, "5" ) // results in 3, see above
// PORT_DIPSETTING( 0x00, "6" ) // results in 4, see above
INPUT_PORTS_END
@ -1646,7 +1646,7 @@ static INPUT_PORTS_START( brdrline )
PORT_DIPSETTING( 0x00, "3" )
PORT_DIPSETTING( 0x01, "4" )
PORT_DIPSETTING( 0x02, "5" )
// PORT_DIPSETTING( 0x03, "5" ) // dupe
// PORT_DIPSETTING( 0x03, "5" ) // dupe
INPUT_PORTS_END
@ -1700,7 +1700,7 @@ static INPUT_PORTS_START( starrkr )
PORT_DIPSETTING( 0x00, "3" )
PORT_DIPSETTING( 0x01, "4" )
PORT_DIPSETTING( 0x02, "5" )
// PORT_DIPSETTING( 0x03, "5" ) // dupe
// PORT_DIPSETTING( 0x03, "5" ) // dupe
INPUT_PORTS_END
@ -2064,7 +2064,7 @@ static INPUT_PORTS_START( samurai )
PORT_START("IN1")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,samurai_protection_r, (void *)1)
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2") // unknown, but used
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2") // unknown, but used
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_composite_blank_comp, NULL)
@ -2249,10 +2249,10 @@ static INPUT_PORTS_START( nsub )
PORT_DIPSETTING( 0x03, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
// PORT_DIPSETTING( 0x00, DEF_STR( 0C_1C ) ) // invalid
// PORT_DIPSETTING( 0x00, DEF_STR( 0C_1C ) ) // invalid
PORT_DIPNAME( 0x78, 0x08, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW:4,5,6,7")
PORT_DIPSETTING( 0x40, "Shared With Coin A" )
// PORT_DIPSETTING( 0x00, DEF_STR( 1C_0C ) ) // invalid
// PORT_DIPSETTING( 0x00, DEF_STR( 1C_0C ) ) // invalid
PORT_DIPSETTING( 0x08, DEF_STR( 1C_1C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x18, DEF_STR( 1C_3C ) )

46
src/mame/drivers/vlc.c
View File

@ -248,9 +248,9 @@ static WRITE16_HANDLER( nevada_videoram_w )
{
// Todo, Just for sample
nevada_state *state = space->machine().driver_data<nevada_state>();
state->m_videoram[offset] = data;
state->m_bg_tilemap->mark_tile_dirty(offset);
nevada_state *state = space->machine().driver_data<nevada_state>();
state->m_videoram[offset] = data;
state->m_bg_tilemap->mark_tile_dirty(offset);
}
*/
@ -265,14 +265,14 @@ GFXDECODE_END
static TILE_GET_INFO( get_bg_tile_info )
{
// Todo, Just for sample
nevada_state *state = machine.driver_data<nevada_state>();
nevada_state *state = machine.driver_data<nevada_state>();
int attr = state->m_colorram[tile_index];
int code = ((attr & 1) << 8) | state->m_videoram[tile_index];
int bank = (attr & 0x02) >> 1;
int color = (attr & 0x3c) >> 2;
int attr = state->m_colorram[tile_index];
int code = ((attr & 1) << 8) | state->m_videoram[tile_index];
int bank = (attr & 0x02) >> 1;
int color = (attr & 0x3c) >> 2;
SET_TILE_INFO(bank, code, color, 0);
SET_TILE_INFO(bank, code, color, 0);
}
*/
@ -282,8 +282,8 @@ static VIDEO_START( nevada )
{
// todo
/*
nevada_state *state = machine.driver_data<nevada_state>();
state->m_bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
nevada_state *state = machine.driver_data<nevada_state>();
state->m_bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
*/
}
@ -292,8 +292,8 @@ static SCREEN_UPDATE_IND16( nevada )
{
// Todo
/*
nevada_state *state = screen.machine().driver_data<nevada_state>();
state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
nevada_state *state = screen.machine().driver_data<nevada_state>();
state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
*/
return 0;
}
@ -342,7 +342,7 @@ static void duart18_irq_handler(device_t *device, int state, UINT8 vector )
/***************************************************************************/
static void duart18_tx(device_t *device, int channel, UINT8 data)
{
// nevada_state *state = device->machine().driver_data<nevada_state>();
// nevada_state *state = device->machine().driver_data<nevada_state>();
/* Todo , just for sample */
if ( channel == 0 )
{
@ -374,7 +374,7 @@ static void duart39_irq_handler( device_t *device, int state, UINT8 vector )
/***************************************************************************/
static void duart39_tx(device_t *device, int channel, UINT8 data)
{
// nevada_state *state = device->machine().driver_data<nevada_state>();
// nevada_state *state = device->machine().driver_data<nevada_state>();
/* Todo , just for sample */
if ( channel == 0 )
{
@ -464,8 +464,8 @@ static const ay8910_interface ay8910_config =
{
AY8910_LEGACY_OUTPUT,
AY8910_DEFAULT_LOADS,
// DEVCB_INPUT_PORT("DSW1"), /* not used */
// DEVCB_INPUT_PORT("DSW2"), /* not used */
// DEVCB_INPUT_PORT("DSW1"), /* not used */
// DEVCB_INPUT_PORT("DSW2"), /* not used */
DEVCB_NULL, /* callback for display state changes */
DEVCB_NULL, /* callback for cursor state changes */
DEVCB_NULL,
@ -493,7 +493,7 @@ static WRITE16_HANDLER (io_board_x)
static READ16_HANDLER( nevada_sec_r )
{
nevada_state *state = space.machine().driver_data<nevada_state>();
// D3..D0 = DOOR OPEN or Track STATE of PAL35
// D3..D0 = DOOR OPEN or Track STATE of PAL35
UINT16 res;
/* UPPER byte is use for input in PAL35 */
// 74LS173 $bits Register used LOWER bits D3..D0 for PAL35 state and DOOR LOGIC SWITCH
@ -508,8 +508,8 @@ static WRITE16_HANDLER( nevada_sec_w )
{
nevada_state *state = space.machine().driver_data<nevada_state>();
// 74LS173 $bits Register used LOWER bits D3..D0 for DOOR LOGIC SWITCH
state->m_datA40000 = data | 0x00f0; // since D7..D4 are not used and are connected to PULLUP
// popmessage("WRITE %04x %04x ",datA40000,data);
state->m_datA40000 = data | 0x00f0; // since D7..D4 are not used and are connected to PULLUP
// popmessage("WRITE %04x %04x ",datA40000,data);
}
/***************************************************************************/
@ -782,15 +782,15 @@ DRIVER_INIT_MEMBER(nevada_state,nevada)
/* Patch for WDT test with int Level7 */
/* PATCH FE0086 4278 0414 Clrf $0414 */
/* this skip the test for the WDT */
// ROM[0xFE0086/2] = 0x4278;
// ROM[0xFE0088/2] = 0x0414;
// ROM[0xFE0086/2] = 0x4278;
// ROM[0xFE0088/2] = 0x0414;
// Skip PAL SECURITY
ROM[0xFE0248/2] = 0x4E71; // nop
ROM[0xFE05D0/2] = 0x4E71; // nop
ROM[0xFE05D8/2] = 0x6014; // bra
ROM[0xFE0606/2] = 0x600A; // bra
// ROM[0xFE18B4/2] = 0x4E71; // nop
// ROM[0xFE18B4/2] = 0x4E71; // nop
}

4
src/mame/machine/archimds.c
View File

@ -867,8 +867,8 @@ WRITE32_MEMBER(archimedes_state::archimedes_vidc_w)
case VIDC_HCR: m_vidc_regs[VIDC_HCR] = ((val >> 14)<<1)+1; break;
// case VIDC_HSWR: m_vidc_regs[VIDC_HSWR] = (val >> 14)+1; break;
case VIDC_HBSR: m_vidc_regs[VIDC_HBSR] = ((val >> 14)<<1)+1; break;
case VIDC_HDSR: m_vidc_regs[VIDC_HDSR] = (val >> 14); break;
case VIDC_HDER: m_vidc_regs[VIDC_HDER] = (val >> 14); break;
case VIDC_HDSR: m_vidc_regs[VIDC_HDSR] = (val >> 14); break;
case VIDC_HDER: m_vidc_regs[VIDC_HDER] = (val >> 14); break;
case VIDC_HBER: m_vidc_regs[VIDC_HBER] = ((val >> 14)<<1)+1; break;
// #define VIDC_HCSR 0x98
// #define VIDC_HIR 0x9c

2
src/mame/machine/megacd.c
View File

@ -2584,7 +2584,7 @@ void sega_segacd_device::device_start()
segacd_font_bits = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:segacd_font")->ptr());
segacd_backupram = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:backupram")->ptr());
segacd_dataram = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:dataram")->ptr());
// segacd_dataram2 = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:dataram2")->ptr());
// segacd_dataram2 = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:dataram2")->ptr());
segacd_4meg_prgram = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:segacd_program")->ptr());
segacd_4meg_prgbank = 0;

2
src/mame/machine/pcecommn.h
View File

@ -24,7 +24,7 @@ public:
virtual UINT8 joy_read();
private:
UINT8 m_io_port_options; /*driver-specific options for the PCE*/
UINT8 m_io_port_options; /*driver-specific options for the PCE*/
int m_joystick_port_select; /* internal index of joystick ports */
int m_joystick_data_select; /* which nibble of joystick data we want */
};

28
src/mame/machine/seicop.c
View File

@ -2048,10 +2048,10 @@ static void cop_take_hit_box_params(UINT8 offs)
{
height = UINT8(cop_collision_info[offs].hitbox_y >> 8);
start_y = INT8(cop_collision_info[offs].hitbox_y);
start_y = INT8(cop_collision_info[offs].hitbox_y);
width = UINT8(cop_collision_info[offs].hitbox_x >> 8);
start_x = INT8(cop_collision_info[offs].hitbox_x);
}
start_x = INT8(cop_collision_info[offs].hitbox_x);
}
cop_collision_info[offs].min_x = (cop_collision_info[offs].x >> 16) + start_x;
cop_collision_info[offs].max_x = cop_collision_info[offs].min_x + width;
@ -2089,8 +2089,8 @@ static UINT8 cop_calculate_collsion_detection(running_machine &machine)
//if(res == 0)
//popmessage("0:%08x %08x %08x 1:%08x %08x %08x\n",cop_collision_info[0].x,cop_collision_info[0].y,cop_collision_info[0].hitbox,cop_collision_info[1].x,cop_collision_info[1].y,cop_collision_info[1].hitbox);
// popmessage("0:%08x %08x %08x %08x 1:%08x %08x %08x %08x\n",cop_collision_info[0].min_x,cop_collision_info[0].max_x,cop_collision_info[0].min_y, cop_collision_info[0].max_y,
// cop_collision_info[1].min_x,cop_collision_info[1].max_x,cop_collision_info[1].min_y, cop_collision_info[1].max_y);
// popmessage("0:%08x %08x %08x %08x 1:%08x %08x %08x %08x\n",cop_collision_info[0].min_x,cop_collision_info[0].max_x,cop_collision_info[0].min_y, cop_collision_info[0].max_y,
// cop_collision_info[1].min_x,cop_collision_info[1].max_x,cop_collision_info[1].min_y, cop_collision_info[1].max_y);
return res;
}
@ -2779,15 +2779,15 @@ static WRITE16_HANDLER( generic_cop_w )
cur_angle = INT8(space.read_byte(cop_register[0] + (0x34 ^ 3)));
//space.write_byte(cop_register[0] + (0^3),space.read_byte(cop_register[0] + (0^3)) & 0xfb); //correct?
/*
0x00 0x00 0x60 0x00
0x00 0x20 0x60 0x20
0x00 0x40 0x60 0x60
0x00 0x60 0x60 0x60
0x00 0x80 0x60 0xa0
0x00 0xa0 0x60 0xa0
0x00 0xc0 0x60 0xc0
0x00 0xe0 0x60 0xe0
*/
0x00 0x00 0x60 0x00
0x00 0x20 0x60 0x20
0x00 0x40 0x60 0x60
0x00 0x60 0x60 0x60
0x00 0x80 0x60 0xa0
0x00 0xa0 0x60 0xa0
0x00 0xc0 0x60 0xc0
0x00 0xe0 0x60 0xe0
*/
if(cur_angle > cop_angle_compare)
{

2
src/mame/video/awpvid.c
View File

@ -8,7 +8,7 @@
This is a primitive handler for generating reels with multiple symbols visible
hanging off steppers.c .
TODO: Add any lamping persistance simulations we need.
TODO: Add any lamping persistance simulations we need.
**************************************************************************************/

10
src/mame/video/dkong.c
View File

@ -129,7 +129,7 @@ static const res_net_info radarscp_net_info =
{
{ RES_NET_AMP_DARLINGTON, 470 * TRS_J1, 470*(1-TRS_J1), 3, { 1000, 470, 220 } },
{ RES_NET_AMP_DARLINGTON, 470 * TRS_J1, 470*(1-TRS_J1), 3, { 1000, 470, 220 } },
{ RES_NET_AMP_EMITTER, 680 * TRS_J1, 680*(1-TRS_J1), 2, { 470, 220, 0 } } /* radarscp */
{ RES_NET_AMP_EMITTER, 680 * TRS_J1, 680*(1-TRS_J1), 2, { 470, 220, 0 } } /* radarscp */
}
};
@ -139,7 +139,7 @@ static const res_net_info radarscp_net_bck_info =
{
{ RES_NET_AMP_DARLINGTON, 470, 4700, 0, { 0 } },
{ RES_NET_AMP_DARLINGTON, 470, 4700, 0, { 0 } },
{ RES_NET_AMP_EMITTER, 470, 4700, 0, { 0 } } /* radarscp */
{ RES_NET_AMP_EMITTER, 470, 4700, 0, { 0 } } /* radarscp */
}
};
@ -713,9 +713,9 @@ static void radarscp_step(running_machine &machine, int line_cnt)
int sig;
/* vsync is divided by 2 by a LS161
* The resulting 30 Hz signal clocks a LFSR (LS164) operating as a
* random number generator.
*/
* The resulting 30 Hz signal clocks a LFSR (LS164) operating as a
* random number generator.
*/
if ( line_cnt == 0)
{

2
src/mame/video/ninjakd2.c
View File

@ -352,7 +352,7 @@ static void draw_sprites(running_machine& machine, bitmap_ind16 &bitmap)
counts as one sprite drawn.
This is proven by Mutant Night, which doesn't work correctly (leaves shots
on screen) if we don't take big sprites into account.
*/
*/
for (;;)
{

18
src/mess/drivers/a2600.c
View File

@ -47,8 +47,8 @@ public:
a2600_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_riot_ram(*this, "riot_ram")
// , m_joy1(*this, CONTROL1_TAG)
// , m_joy2(*this, CONTROL2_TAG)
// , m_joy1(*this, CONTROL1_TAG)
// , m_joy2(*this, CONTROL2_TAG)
{ }
dpc_t m_dpc;
@ -128,8 +128,8 @@ public:
DECLARE_READ8_MEMBER(riot_input_port_8_r);
protected:
// required_device<vcs_control_port_device> m_joy1;
// required_device<vcs_control_port_device> m_joy2;
// required_device<vcs_control_port_device> m_joy1;
// required_device<vcs_control_port_device> m_joy2;
int next_bank();
void modeF8_switch(UINT16 offset, UINT8 data);
void modeFA_switch(UINT16 offset, UINT8 data);
@ -1276,7 +1276,7 @@ READ8_MEMBER(a2600_state::switch_A_r)
case 0x00: /* Joystick */
case 0x05: /* Joystick w/Boostergrip */
val |= machine().root_device().ioport("SWA_JOY")->read() & 0xF0;
// val |= ( m_joy1->joy_r() & 0x0F ) << 4;
// val |= ( m_joy1->joy_r() & 0x0F ) << 4;
break;
case 0x01: /* Paddle */
val |= machine().root_device().ioport("SWA_PAD")->read() & 0xF0;
@ -2315,8 +2315,8 @@ static MACHINE_CONFIG_START( a2600, a2600_state )
/* devices */
MCFG_RIOT6532_ADD("riot", MASTER_CLOCK_NTSC / 3, r6532_interface)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
MCFG_FRAGMENT_ADD(a2600_cartslot)
MCFG_SOFTWARE_LIST_FILTER("cart_list", "NTSC")
@ -2351,8 +2351,8 @@ static MACHINE_CONFIG_START( a2600p, a2600_state )
/* devices */
MCFG_RIOT6532_ADD("riot", MASTER_CLOCK_PAL / 3, r6532_interface)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
MCFG_FRAGMENT_ADD(a2600_cartslot)
MCFG_SOFTWARE_LIST_FILTER("cart_list", "PAL")

2
src/mess/drivers/bml3.c
View File

@ -893,7 +893,7 @@ static MACHINE_CONFIG_START( bml3, bml3_state )
MCFG_CPU_ADD("maincpu",M6809, XTAL_1MHz)
MCFG_CPU_PROGRAM_MAP(bml3_mem)
MCFG_CPU_VBLANK_INT_DRIVER("screen", bml3_state, bml3_timer_firq)
// MCFG_CPU_PERIODIC_INT_DRIVER(bml3_state, bml3_firq, 45)
// MCFG_CPU_PERIODIC_INT_DRIVER(bml3_state, bml3_firq, 45)
// MCFG_MACHINE_RESET_OVERRIDE(bml3_state,bml3)

292
src/mess/drivers/cbm2.c
View File

@ -2,15 +2,15 @@
TODO:
- CIA timers fail in burn-in test
- NTSC variants unable to load from disk
- shift lock
- Hungarian keyboard
- cbm620hu charom banking?
- read VIC video/color RAM thru PLA (Sphi2 = 1, AE = 0)
- user port
- co-processor bus
- 8088 co-processor board
- CIA timers fail in burn-in test
- NTSC variants unable to load from disk
- shift lock
- Hungarian keyboard
- cbm620hu charom banking?
- read VIC video/color RAM thru PLA (Sphi2 = 1, AE = 0)
- user port
- co-processor bus
- 8088 co-processor board
*/
@ -675,24 +675,24 @@ WRITE8_MEMBER( p500_state::write )
READ8_MEMBER( p500_state::vic_videoram_r )
{
/*
int sphi0 = 0, sphi1 = 1, sphi2 = 0, ba = 1, ae = 0, bras = 0, bcas = 0;
offs_t va = offset;
int sphi0 = 0, sphi1 = 1, sphi2 = 0, ba = 1, ae = 0, bras = 0, bcas = 0;
offs_t va = offset;
return read_memory(space, 0, va, sphi0, sphi1, sphi2, ba, ae, bras, bcas);
*/
return read_memory(space, 0, va, sphi0, sphi1, sphi2, ba, ae, bras, bcas);
*/
/*
int ba = 1, ae = 0, bras = 1, bcas = 0;
UINT8 clrnib = 0xf;
int ba = 1, ae = 0, bras = 1, bcas = 0;
UINT8 clrnib = 0xf;
if (offset < 0x1000)
{
return read_memory(space, 0, offset, 0, 1, 0, ba, ae, bras, bcas, &clrnib);
}
else
{
return read_memory(space, 0, offset, 1, 0, 1, ba, ae, bras, bcas, &clrnib);
}
*/
if (offset < 0x1000)
{
return read_memory(space, 0, offset, 0, 1, 0, ba, ae, bras, bcas, &clrnib);
}
else
{
return read_memory(space, 0, offset, 1, 0, 1, ba, ae, bras, bcas, &clrnib);
}
*/
if (offset < 0x1000)
{
@ -1107,18 +1107,18 @@ READ8_MEMBER( cbm2_state::tpi1_pa_r )
{
/*
bit description
bit description
0 0
1 0
2 REN
3 ATN
4 DAV
5 EOI
6 NDAC
7 NRFD
0 0
1 0
2 REN
3 ATN
4 DAV
5 EOI
6 NDAC
7 NRFD
*/
*/
UINT8 data = 0;
@ -1137,18 +1137,18 @@ WRITE8_MEMBER( cbm2_state::tpi1_pa_w )
{
/*
bit description
bit description
0 75161A DC
1 75161A TE
2 REN
3 ATN
4 DAV
5 EOI
6 NDAC
7 NRFD
0 75161A DC
1 75161A TE
2 REN
3 ATN
4 DAV
5 EOI
6 NDAC
7 NRFD
*/
*/
// IEEE-488
m_ieee2->dc_w(BIT(data, 0));
@ -1168,18 +1168,18 @@ READ8_MEMBER( cbm2_state::tpi1_pb_r )
{
/*
bit description
bit description
0 IFC
1 SRQ
2 user port PB2
3 user port PB3
4
5
6
7 CASS SW
0 IFC
1 SRQ
2 user port PB2
3 user port PB3
4
5
6
7 CASS SW
*/
*/
UINT8 data = 0;
@ -1201,22 +1201,22 @@ WRITE8_MEMBER( cbm2_state::tpi1_pb_w )
{
/*
bit description
bit description
0 IFC
1 SRQ
2 user port PB2
3 user port PB3
4 DRAMON
5 CASS WRT
6 CASS MTR
7
0 IFC
1 SRQ
2 user port PB2
3 user port PB3
4 DRAMON
5 CASS WRT
6 CASS MTR
7
*/
*/
// IEEE-488
m_ieee2->ifc_w(BIT(data, 0));
m_ieee2->srq_w(BIT(data, 1));
m_ieee2->ifc_w(BIT(data, 0));
m_ieee2->srq_w(BIT(data, 1));
// user port
//m_user->pb2_w(BIT(data, 2));
@ -1314,18 +1314,18 @@ READ8_MEMBER( cbm2_state::tpi2_pc_r )
{
/*
bit description
bit description
0 COLUMN 0
1 COLUMN 1
2 COLUMN 2
3 COLUMN 3
4 COLUMN 4
5 COLUMN 5
6 0=PAL, 1=NTSC
7 0
0 COLUMN 0
1 COLUMN 1
2 COLUMN 2
3 COLUMN 3
4 COLUMN 4
5 COLUMN 5
6 0=PAL, 1=NTSC
7 0
*/
*/
return (m_ntsc << 6) | (read_keyboard() & 0x3f);
}
@ -1334,18 +1334,18 @@ READ8_MEMBER( cbm2hp_state::tpi2_pc_r )
{
/*
bit description
bit description
0 COLUMN 0
1 COLUMN 1
2 COLUMN 2
3 COLUMN 3
4 COLUMN 4
5 COLUMN 5
6 1
7 1
0 COLUMN 0
1 COLUMN 1
2 COLUMN 2
3 COLUMN 3
4 COLUMN 4
5 COLUMN 5
6 1
7 1
*/
*/
return read_keyboard();
}
@ -1354,18 +1354,18 @@ READ8_MEMBER( p500_state::tpi2_pc_r )
{
/*
bit description
bit description
0 COLUMN 0
1 COLUMN 1
2 COLUMN 2
3 COLUMN 3
4 COLUMN 4
5 COLUMN 5
6 0
7 0
0 COLUMN 0
1 COLUMN 1
2 COLUMN 2
3 COLUMN 3
4 COLUMN 4
5 COLUMN 5
6 0
7 0
*/
*/
return read_keyboard();
}
@ -1374,18 +1374,18 @@ WRITE8_MEMBER( p500_state::tpi2_pc_w )
{
/*
bit description
bit description
0
1
2
3
4
5
6 VICBNKSEL0
7 VICBNKSEL1
0
1
2
3
4
5
6 VICBNKSEL0
7 VICBNKSEL1
*/
*/
m_vicbnksel = data >> 6;
}
@ -1438,18 +1438,18 @@ READ8_MEMBER( cbm2_state::cia_pa_r )
{
/*
bit description
bit description
0 IEEE-488 D0, user port 1D0
1 IEEE-488 D1, user port 1D1
2 IEEE-488 D2, user port 1D2
3 IEEE-488 D3, user port 1D3
4 IEEE-488 D4, user port 1D4
5 IEEE-488 D5, user port 1D5
6 IEEE-488 D6, user port 1D6, LTPN
7 IEEE-488 D7, user port 1D7, GAME TRIGGER 24
0 IEEE-488 D0, user port 1D0
1 IEEE-488 D1, user port 1D1
2 IEEE-488 D2, user port 1D2
3 IEEE-488 D3, user port 1D3
4 IEEE-488 D4, user port 1D4
5 IEEE-488 D5, user port 1D5
6 IEEE-488 D6, user port 1D6, LTPN
7 IEEE-488 D7, user port 1D7, GAME TRIGGER 24
*/
*/
UINT8 data = 0;
@ -1470,18 +1470,18 @@ WRITE8_MEMBER( cbm2_state::cia_pa_w )
{
/*
bit description
bit description
0 IEEE-488 D0, user port 1D0
1 IEEE-488 D1, user port 1D1
2 IEEE-488 D2, user port 1D2
3 IEEE-488 D3, user port 1D3
4 IEEE-488 D4, user port 1D4
5 IEEE-488 D5, user port 1D5
6 IEEE-488 D6, user port 1D6
7 IEEE-488 D7, user port 1D7
0 IEEE-488 D0, user port 1D0
1 IEEE-488 D1, user port 1D1
2 IEEE-488 D2, user port 1D2
3 IEEE-488 D3, user port 1D3
4 IEEE-488 D4, user port 1D4
5 IEEE-488 D5, user port 1D5
6 IEEE-488 D6, user port 1D6
7 IEEE-488 D7, user port 1D7
*/
*/
// IEEE-488
m_ieee1->write(space, 0, data);
@ -1497,18 +1497,18 @@ READ8_MEMBER( cbm2_state::cia_pb_r )
{
/*
bit description
bit description
0 user port 2D0, GAME10
1 user port 2D1, GAME11
2 user port 2D2, GAME12
3 user port 2D3, GAME13
4 user port 2D4, GAME20
5 user port 2D5, GAME21
6 user port 2D6, GAME22
7 user port 2D7, GAME23
0 user port 2D0, GAME10
1 user port 2D1, GAME11
2 user port 2D2, GAME12
3 user port 2D3, GAME13
4 user port 2D4, GAME20
5 user port 2D5, GAME21
6 user port 2D6, GAME22
7 user port 2D7, GAME23
*/
*/
UINT8 data = 0;
@ -1526,18 +1526,18 @@ WRITE8_MEMBER( cbm2_state::cia_pb_w )
{
/*
bit description
bit description
0 user port 2D0
1 user port 2D1
2 user port 2D2
3 user port 2D3
4 user port 2D4
5 user port 2D5
6 user port 2D6
7 user port 2D7
0 user port 2D0
1 user port 2D1
2 user port 2D2
3 user port 2D3
4 user port 2D4
5 user port 2D5
6 user port 2D6
7 user port 2D7
*/
*/
//m_user->data2_w(data);
}

4
src/mess/drivers/jr100.c
View File

@ -265,11 +265,11 @@ static const via6522_interface jr100_via_intf =
DEVCB_NULL, /* in_ca2_func */
DEVCB_NULL, /* in_cb2_func */
DEVCB_DRIVER_MEMBER(jr100_state,jr100_via_write_a), /* out_a_func */
DEVCB_DRIVER_MEMBER(jr100_state,jr100_via_write_b), /* out_b_func */
DEVCB_DRIVER_MEMBER(jr100_state,jr100_via_write_b), /* out_b_func */
DEVCB_NULL, /* out_ca1_func */
DEVCB_NULL, /* out_cb1_func */
DEVCB_NULL, /* out_ca2_func */
DEVCB_DRIVER_LINE_MEMBER(jr100_state, jr100_via_write_cb2), /* out_cb2_func */
DEVCB_DRIVER_LINE_MEMBER(jr100_state, jr100_via_write_cb2), /* out_cb2_func */
DEVCB_NULL /* irq_func */
};
static const cassette_interface jr100_cassette_interface =

40
src/mess/drivers/korgm1.c
View File

@ -1,11 +1,11 @@
/***************************************************************************
Korg M1 (c) 1988
Korg M1 (c) 1988
skeleton driver
skeleton driver
Note: driver isn't yet hooked up to mess.lst / mess.mak, until a ROM
dump is found.
Note: driver isn't yet hooked up to mess.lst / mess.mak, until a ROM
dump is found.
***************************************************************************/
@ -51,24 +51,24 @@ UINT32 korgm1_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap,
static ADDRESS_MAP_START( korgm1_map, AS_PROGRAM, 16, korgm1_state )
AM_RANGE(0x00000, 0x0ffff) AM_RAM // 64 KB
// AM_RANGE(0x50000, 0x57fff) AM_RAM // memory card 32 KB
// AM_RANGE(0x50000, 0x57fff) AM_RAM // memory card 32 KB
AM_RANGE(0xe0000, 0xfffff) AM_ROM AM_REGION("ipl", 0)
ADDRESS_MAP_END
static ADDRESS_MAP_START( korgm1_io, AS_IO, 16, korgm1_state )
// AM_RANGE(0x0000, 0x00ff) internal peripheral (?)
// AM_RANGE(0x0100, 0x01ff) VDF 1 (MB87404)
// AM_RANGE(0x0200, 0x02ff) VDF 2 (MB87404)
// AM_RANGE(0x0500, 0x0503) MDE (MB87405)
// AM_RANGE(0x0600, 0x0601) OPZ 1 (8-bit port)
// AM_RANGE(0x0700, 0x0701) OPZ 2 (8-bit port)
// AM_RANGE(0x0800, 0x0801) SCAN (8-bit port) (keyboard)
// AM_RANGE(0x0900, 0x09??) A/D Converter (M58990P, Joystick, "value" and After Touch routes here) **
// AM_RANGE(0x0a00, 0x0a03) PPI (CXD1095, presumably i8255 compatible, LCD, LED and SW routes here) *
// AM_RANGE(0x0b00, 0x0b01) LCDC (8-bit port)
// AM_RANGE(0x1000, 0x11ff) TG (MB87402)
// AM_RANGE(0x2000, 0x23ff) SCSI
// AM_RANGE(0x3000, 0x33ff) FDC
// AM_RANGE(0x0000, 0x00ff) internal peripheral (?)
// AM_RANGE(0x0100, 0x01ff) VDF 1 (MB87404)
// AM_RANGE(0x0200, 0x02ff) VDF 2 (MB87404)
// AM_RANGE(0x0500, 0x0503) MDE (MB87405)
// AM_RANGE(0x0600, 0x0601) OPZ 1 (8-bit port)
// AM_RANGE(0x0700, 0x0701) OPZ 2 (8-bit port)
// AM_RANGE(0x0800, 0x0801) SCAN (8-bit port) (keyboard)
// AM_RANGE(0x0900, 0x09??) A/D Converter (M58990P, Joystick, "value" and After Touch routes here) **
// AM_RANGE(0x0a00, 0x0a03) PPI (CXD1095, presumably i8255 compatible, LCD, LED and SW routes here) *
// AM_RANGE(0x0b00, 0x0b01) LCDC (8-bit port)
// AM_RANGE(0x1000, 0x11ff) TG (MB87402)
// AM_RANGE(0x2000, 0x23ff) SCSI
// AM_RANGE(0x3000, 0x33ff) FDC
// TG 2?
ADDRESS_MAP_END
@ -145,7 +145,7 @@ static const gfx_layout charlayout =
#endif
static GFXDECODE_START( korgm1 )
// GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
// GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
GFXDECODE_END
@ -202,7 +202,7 @@ ROM_START( korgm1 )
ROM_REGION( 0x200000, "pcm", ROMREGION_ERASE00 )
ROM_LOAD( "pcm.rom", 0x00000, 0x200000, NO_DUMP )
// ROM_REGION( 0x10000, "gfx1", ROMREGION_ERASE00 )
// ROM_REGION( 0x10000, "gfx1", ROMREGION_ERASE00 )
ROM_END
GAME( 1988, korgm1, 0, korgm1, korgm1, 0, ROT0, "Korg", "M1", GAME_IS_SKELETON )

4
src/mess/drivers/pc8801.c
View File

@ -2348,8 +2348,8 @@ static void pc8801_sound_irq( device_t *device, int irq )
/*
TIMER_DEVICE_CALLBACK_MEMBER(pc8801_state::pc8801_rtc_irq)
{
if(m_timer_irq_mask)
pc8801_raise_irq(machine(),1<<(2),1);
if(m_timer_irq_mask)
pc8801_raise_irq(machine(),1<<(2),1);
}
*/

4
src/mess/drivers/pv9234.c
View File

@ -79,10 +79,10 @@ WRITE32_MEMBER( pv9234_state::debug1_w )
{
j = (data & 0xff000000) >> 24;
data <<= 8;
// printf("%c",j); // this prints 'OFF' to the console.
// printf("%c",j); // this prints 'OFF' to the console.
logerror("debug1=%02x %c\n",j,j);
}
// printf("\n");
// printf("\n");
}
}

2
src/mess/drivers/test_t400.c
View File

@ -21,7 +21,7 @@ public:
WRITE8_MEMBER( t400_test_suite_state::port_l_w )
{
// printf("L: %u\n", data);
// printf("L: %u\n", data);
}
static ADDRESS_MAP_START( cop_io, AS_IO, 8, t400_test_suite_state )

4
src/mess/drivers/xerox820.c
View File

@ -559,13 +559,13 @@ TIMER_DEVICE_CALLBACK_MEMBER(xerox820_state::ctc_tick)
WRITE_LINE_MEMBER(xerox820_state::ctc_z0_w)
{
// device_t *device = machine().device(Z80CTC_TAG);
// device_t *device = machine().device(Z80CTC_TAG);
// z80ctc_trg1_w(device, state);
}
WRITE_LINE_MEMBER(xerox820_state::ctc_z2_w)
{
// device_t *device = machine().device(Z80CTC_TAG);
// device_t *device = machine().device(Z80CTC_TAG);
// z80ctc_trg3_w(device, state);
}

2
src/mess/drivers/xor100.c
View File

@ -482,7 +482,7 @@ static Z80CTC_INTERFACE( ctc_intf )
DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), /* interrupt handler */
DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z0_w), /* ZC/TO0 callback */
DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z1_w), /* ZC/TO1 callback */
DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z2_w) /* ZC/TO2 callback */
DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z2_w) /* ZC/TO2 callback */
};
/* WD1795-02 Interface */

74
src/mess/machine/bebox.c
View File

@ -610,48 +610,48 @@ void bebox_ide_interrupt(device_t *device, int state)
/*
static READ64_MEMBER(bebox_state::bebox_video_r )
{
UINT64 result = 0;
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_7)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 0, mem_mask >> 0) << 0;
if (ACCESSING_BITS_8_15)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 1, mem_mask >> 8) << 8;
if (ACCESSING_BITS_16_23)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 2, mem_mask >> 16) << 16;
if (ACCESSING_BITS_24_31)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 3, mem_mask >> 24) << 24;
if (ACCESSING_BITS_32_39)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 4, mem_mask >> 32) << 32;
if (ACCESSING_BITS_40_47)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 5, mem_mask >> 40) << 40;
if (ACCESSING_BITS_48_55)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 6, mem_mask >> 48) << 48;
if (ACCESSING_BITS_56_63)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 7, mem_mask >> 56) << 56;
return FLIPENDIAN_INT64(result);
UINT64 result = 0;
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_7)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 0, mem_mask >> 0) << 0;
if (ACCESSING_BITS_8_15)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 1, mem_mask >> 8) << 8;
if (ACCESSING_BITS_16_23)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 2, mem_mask >> 16) << 16;
if (ACCESSING_BITS_24_31)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 3, mem_mask >> 24) << 24;
if (ACCESSING_BITS_32_39)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 4, mem_mask >> 32) << 32;
if (ACCESSING_BITS_40_47)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 5, mem_mask >> 40) << 40;
if (ACCESSING_BITS_48_55)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 6, mem_mask >> 48) << 48;
if (ACCESSING_BITS_56_63)
result |= (UINT64)vga_mem_linear_r(space, offset * 8 + 7, mem_mask >> 56) << 56;
return FLIPENDIAN_INT64(result);
}
static WRITE64_MEMBER(bebox_state::bebox_video_w )
{
data = FLIPENDIAN_INT64(data);
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_7)
vga_mem_linear_w(space, offset * 8 + 0, data >> 0 , mem_mask >> 0);
if (ACCESSING_BITS_8_15)
vga_mem_linear_w(space, offset * 8 + 1, data >> 8 , mem_mask >> 8);
if (ACCESSING_BITS_16_23)
vga_mem_linear_w(space, offset * 8 + 2, data >> 16, mem_mask >> 16);
if (ACCESSING_BITS_24_31)
vga_mem_linear_w(space, offset * 8 + 3, data >> 24, mem_mask >> 24);
if (ACCESSING_BITS_32_39)
vga_mem_linear_w(space, offset * 8 + 4, data >> 32, mem_mask >> 32);
if (ACCESSING_BITS_40_47)
vga_mem_linear_w(space, offset * 8 + 5, data >> 40, mem_mask >> 40);
if (ACCESSING_BITS_48_55)
vga_mem_linear_w(space, offset * 8 + 6, data >> 48, mem_mask >> 48);
if (ACCESSING_BITS_56_63)
vga_mem_linear_w(space, offset * 8 + 7, data >> 56, mem_mask >> 56);
data = FLIPENDIAN_INT64(data);
mem_mask = FLIPENDIAN_INT64(mem_mask);
if (ACCESSING_BITS_0_7)
vga_mem_linear_w(space, offset * 8 + 0, data >> 0 , mem_mask >> 0);
if (ACCESSING_BITS_8_15)
vga_mem_linear_w(space, offset * 8 + 1, data >> 8 , mem_mask >> 8);
if (ACCESSING_BITS_16_23)
vga_mem_linear_w(space, offset * 8 + 2, data >> 16, mem_mask >> 16);
if (ACCESSING_BITS_24_31)
vga_mem_linear_w(space, offset * 8 + 3, data >> 24, mem_mask >> 24);
if (ACCESSING_BITS_32_39)
vga_mem_linear_w(space, offset * 8 + 4, data >> 32, mem_mask >> 32);
if (ACCESSING_BITS_40_47)
vga_mem_linear_w(space, offset * 8 + 5, data >> 40, mem_mask >> 40);
if (ACCESSING_BITS_48_55)
vga_mem_linear_w(space, offset * 8 + 6, data >> 48, mem_mask >> 48);
if (ACCESSING_BITS_56_63)
vga_mem_linear_w(space, offset * 8 + 7, data >> 56, mem_mask >> 56);
}
*/
/*************************************

46
src/mess/machine/cbm2_graphic.c
View File

@ -9,10 +9,10 @@
/*
TODO:
TODO:
- version A (EF9365, 512x512 interlaced, 1 page)
- version B (EF9366, 512x256 non-interlaced, 2 pages)
- version A (EF9365, 512x512 interlaced, 1 page)
- version B (EF9366, 512x256 non-interlaced, 2 pages)
*/
@ -146,18 +146,18 @@ UINT8 cbm2_graphic_cartridge_device::cbm2_bd_r(address_space &space, offs_t offs
{
/*
bit description
bit description
0 light pen
1
2
3
4
5
6
7
0 light pen
1
2
3
4
5
6
7
*/
*/
}
else if (offset == 0x7fb0)
{
@ -185,18 +185,18 @@ void cbm2_graphic_cartridge_device::cbm2_bd_w(address_space &space, offs_t offse
{
/*
bit description
bit description
0 hard copy (0=active)
1 operating page select (version B)
2
3 read-modify-write (1=active)
4 display switch (1=graphic)
5 display page select (version B)
6
7
0 hard copy (0=active)
1 operating page select (version B)
2
3 read-modify-write (1=active)
4 display switch (1=graphic)
5 display page select (version B)
6
7
*/
*/
}
else if (offset >= 0x7ff0)
{

20
src/mess/machine/pc.c
View File

@ -924,8 +924,8 @@ TIMER_CALLBACK_MEMBER(pc_state::mc1502_keyb_signal_callback)
key |= machine().root_device().ioport("Y10")->read();
key |= machine().root_device().ioport("Y11")->read();
key |= machine().root_device().ioport("Y12")->read();
// DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, mc1502_keyb.pulsing,
// (key || mc1502_keyb.pulsing) ? " will IRQ" : ""));
// DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, mc1502_keyb.pulsing,
// (key || mc1502_keyb.pulsing) ? " will IRQ" : ""));
/*
If a key is pressed and we're not pulsing yet, start pulsing the IRQ1;
@ -946,13 +946,13 @@ TIMER_CALLBACK_MEMBER(pc_state::mc1502_keyb_signal_callback)
READ8_MEMBER(pc_state::mc1502_ppi_porta_r)
{
// DBG_LOG(1,"mc1502_ppi_porta_r",("= %02X\n", mc1502_keyb.latch));
// DBG_LOG(1,"mc1502_ppi_porta_r",("= %02X\n", mc1502_keyb.latch));
return mc1502_keyb.latch;
}
WRITE8_MEMBER(pc_state::mc1502_ppi_porta_w)
{
// DBG_LOG(1,"mc1502_ppi_porta_w",("( %02X )\n", data));
// DBG_LOG(1,"mc1502_ppi_porta_w",("( %02X )\n", data));
mc1502_keyb.latch = data;
if (mc1502_keyb.pulsing)
mc1502_keyb.pulsing--;
@ -961,7 +961,7 @@ WRITE8_MEMBER(pc_state::mc1502_ppi_porta_w)
WRITE8_MEMBER(pc_state::mc1502_ppi_portb_w)
{
// DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
// DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
m_ppi_portb = data;
pit8253_gate2_w(machine().device("pit8253"), BIT(data, 0));
pc_speaker_set_spkrdata( machine(), data & 0x02 );
@ -981,8 +981,8 @@ READ8_MEMBER(pc_state::mc1502_ppi_portc_r)
// 0x10 -- SNDOUT
data = ( data & ~0x10 ) | ( (BIT(m_ppi_portb, 1) && timer2_output) ? 0x10 : 0x00 );
// DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
// data, tap_val, timer2_output, machine().describe_context()));
// DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
// data, tap_val, timer2_output, machine().describe_context()));
return data;
}
@ -1003,7 +1003,7 @@ READ8_MEMBER(pc_state::mc1502_kppi_porta_r)
if (mc1502_keyb.mask & 0x0400) { key |= machine().root_device().ioport("Y11")->read(); }
if (mc1502_keyb.mask & 0x0800) { key |= machine().root_device().ioport("Y12")->read(); }
key ^= 0xff;
// DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
// DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
return key;
}
@ -1015,14 +1015,14 @@ WRITE8_MEMBER(pc_state::mc1502_kppi_portb_w)
mc1502_keyb.mask |= 1 << 11;
else
mc1502_keyb.mask &= ~(1 << 11);
// DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
// DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
}
WRITE8_MEMBER(pc_state::mc1502_kppi_portc_w)
{
mc1502_keyb.mask &= ~(7 << 8);
mc1502_keyb.mask |= ((data ^ 7) & 7) << 8;
// DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
// DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
}

4
src/mess/machine/rx01.c
View File

@ -176,7 +176,7 @@ UINT16 rx01_device::status_read()
void rx01_device::data_write(UINT16 data)
{
// printf("data_write %04x\n",data);
// printf("data_write %04x\n",data);
// data can be written only if TR is set
if (BIT(m_rxcs,7)) m_rxdb = data;
machine().scheduler().timer_set(attotime::from_msec(100), FUNC(command_execution_callback), 0, this);
@ -185,7 +185,7 @@ void rx01_device::data_write(UINT16 data)
UINT16 rx01_device::data_read()
{
if (m_state==RX01_EMPTY && BIT(m_rxcs,7)) m_rxcs &= (1<<7); // clear TR bit;
// printf("data_read %04x\n",m_rxdb);
// printf("data_read %04x\n",m_rxdb);
return m_rxdb;
}