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second round of clang 3.4 fixes for MESS (nw)

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This commit is contained in:
Oliver Stöneberg 2014-02-20 18:18:29 +00:00
parent d8ba983889
commit 3138b2c660
37 changed files with 163 additions and 115 deletions
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2
src/emu/bus/ecbbus/grip.c
View File

@ -52,6 +52,7 @@ ROM_START( grip21 )
ROM_END ROM_END
#if 0
//------------------------------------------------- //-------------------------------------------------
// ROM( grip25 ) // ROM( grip25 )
//------------------------------------------------- //-------------------------------------------------
@ -100,6 +101,7 @@ ROM_START( grips115 )
ROM_REGION( 0x4000, Z80_TAG, 0 ) ROM_REGION( 0x4000, Z80_TAG, 0 )
ROM_LOAD( "grips115.z2", 0x0000, 0x4000, CRC(505706ef) SHA1(05fb032fb1a504c534c30c352ba4bd47623503d0) ) ROM_LOAD( "grips115.z2", 0x0000, 0x4000, CRC(505706ef) SHA1(05fb032fb1a504c534c30c352ba4bd47623503d0) )
ROM_END ROM_END
#endif
//------------------------------------------------- //-------------------------------------------------

2
src/emu/bus/pc_kbd/keytro.c
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@ -342,6 +342,7 @@ static INPUT_PORTS_START( kb_keytronic_at )
INPUT_PORTS_END INPUT_PORTS_END
#if 0
/*************************************************************************** /***************************************************************************
ROM DEFINITIONS ROM DEFINITIONS
***************************************************************************/ ***************************************************************************/
@ -350,6 +351,7 @@ ROM_START( kb_keytr )
ROM_REGION(0x2000, "kb_keytr", 0) ROM_REGION(0x2000, "kb_keytr", 0)
ROM_LOAD("14166.bin", 0x0000, 0x2000, CRC(1aea1b53) SHA1(b75b6d4509036406052157bc34159f7039cdc72e)) ROM_LOAD("14166.bin", 0x0000, 0x2000, CRC(1aea1b53) SHA1(b75b6d4509036406052157bc34159f7039cdc72e))
ROM_END ROM_END
#endif
//************************************************************************** //**************************************************************************

2
src/emu/cpu/asap/asap.c
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@ -27,7 +27,7 @@ const UINT32 PS_NFLAG = 0x00000008;
const UINT32 PS_IFLAG = 0x00000010; const UINT32 PS_IFLAG = 0x00000010;
const UINT32 PS_PFLAG = 0x00000020; const UINT32 PS_PFLAG = 0x00000020;
const int EXCEPTION_RESET = 0; //const int EXCEPTION_RESET = 0;
const int EXCEPTION_TRAP0 = 1; const int EXCEPTION_TRAP0 = 1;
const int EXCEPTION_TRAPF = 2; const int EXCEPTION_TRAPF = 2;
const int EXCEPTION_INTERRUPT = 3; const int EXCEPTION_INTERRUPT = 3;

2
src/emu/cpu/avr8/avr8.c
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@ -165,7 +165,7 @@ enum
WGM5_FAST_PWM_OCR WGM5_FAST_PWM_OCR
}; };
static const char avr8_reg_name[4] = { 'A', 'B', 'C', 'D' }; //static const char avr8_reg_name[4] = { 'A', 'B', 'C', 'D' };
#define SREG_R(b) ((m_r[AVR8_REGIDX_SREG] & (1 << (b))) >> (b)) #define SREG_R(b) ((m_r[AVR8_REGIDX_SREG] & (1 << (b))) >> (b))
#define SREG_W(b,v) m_r[AVR8_REGIDX_SREG] = (m_r[AVR8_REGIDX_SREG] & ~(1 << (b))) | ((v) << (b)) #define SREG_W(b,v) m_r[AVR8_REGIDX_SREG] = (m_r[AVR8_REGIDX_SREG] & ~(1 << (b))) | ((v) << (b))

8
src/emu/cpu/drcbex64.c
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@ -198,8 +198,8 @@ const UINT32 PTYPE_M = 1 << parameter::PTYPE_MEMORY;
const UINT32 PTYPE_I = 1 << parameter::PTYPE_IMMEDIATE; const UINT32 PTYPE_I = 1 << parameter::PTYPE_IMMEDIATE;
const UINT32 PTYPE_R = 1 << parameter::PTYPE_INT_REGISTER; const UINT32 PTYPE_R = 1 << parameter::PTYPE_INT_REGISTER;
const UINT32 PTYPE_F = 1 << parameter::PTYPE_FLOAT_REGISTER; const UINT32 PTYPE_F = 1 << parameter::PTYPE_FLOAT_REGISTER;
const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I; //const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I;
const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I; //const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MR = PTYPE_M | PTYPE_R; const UINT32 PTYPE_MR = PTYPE_M | PTYPE_R;
const UINT32 PTYPE_MRI = PTYPE_M | PTYPE_R | PTYPE_I; const UINT32 PTYPE_MRI = PTYPE_M | PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F; const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F;
@ -248,7 +248,7 @@ inline x86_memref drcbe_x64::MABS(const void *ptr)
drcbe_x64::opcode_generate_func drcbe_x64::s_opcode_table[OP_MAX]; drcbe_x64::opcode_generate_func drcbe_x64::s_opcode_table[OP_MAX];
// size-to-mask table // size-to-mask table
static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) }; //static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) };
// register mapping tables // register mapping tables
static const UINT8 int_register_map[REG_I_COUNT] = static const UINT8 int_register_map[REG_I_COUNT] =
@ -286,6 +286,7 @@ static const UINT8 condition_map[uml::COND_MAX - uml::COND_Z] =
x64emit::COND_GE, // COND_GE, requires SV x64emit::COND_GE, // COND_GE, requires SV
}; };
#if 0
// rounding mode mapping table // rounding mode mapping table
static const UINT8 fprnd_map[4] = static const UINT8 fprnd_map[4] =
{ {
@ -294,6 +295,7 @@ static const UINT8 fprnd_map[4] =
FPRND_UP, // ROUND_CEIL, round up FPRND_UP, // ROUND_CEIL, round up
FPRND_DOWN // ROUND_FLOOR round down FPRND_DOWN // ROUND_FLOOR round down
}; };
#endif

6
src/emu/cpu/drcbex86.c
View File

@ -108,8 +108,8 @@ const UINT32 PTYPE_M = 1 << parameter::PTYPE_MEMORY;
const UINT32 PTYPE_I = 1 << parameter::PTYPE_IMMEDIATE; const UINT32 PTYPE_I = 1 << parameter::PTYPE_IMMEDIATE;
const UINT32 PTYPE_R = 1 << parameter::PTYPE_INT_REGISTER; const UINT32 PTYPE_R = 1 << parameter::PTYPE_INT_REGISTER;
const UINT32 PTYPE_F = 1 << parameter::PTYPE_FLOAT_REGISTER; const UINT32 PTYPE_F = 1 << parameter::PTYPE_FLOAT_REGISTER;
const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I; //const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I;
const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I; //const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MR = PTYPE_M | PTYPE_R; const UINT32 PTYPE_MR = PTYPE_M | PTYPE_R;
const UINT32 PTYPE_MRI = PTYPE_M | PTYPE_R | PTYPE_I; const UINT32 PTYPE_MRI = PTYPE_M | PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F; const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F;
@ -137,7 +137,7 @@ const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F;
drcbe_x86::opcode_generate_func drcbe_x86::s_opcode_table[OP_MAX]; drcbe_x86::opcode_generate_func drcbe_x86::s_opcode_table[OP_MAX];
// size-to-mask table // size-to-mask table
static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) }; //static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) };
// register mapping tables // register mapping tables
static const UINT8 int_register_map[REG_I_COUNT] = static const UINT8 int_register_map[REG_I_COUNT] =

2
src/emu/cpu/es5510/es5510.c
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@ -26,7 +26,7 @@ static const INT64 MAX_48 = (S64(1) << 47) - 1;
static inline INT32 SX(INT32 x) { return IS_NEGATIVE(x) ? x | 0xff000000 : x & 0x00ffffff; } static inline INT32 SX(INT32 x) { return IS_NEGATIVE(x) ? x | 0xff000000 : x & 0x00ffffff; }
static inline INT32 SC(INT32 x) { return x & 0x00ffffff; } static inline INT32 SC(INT32 x) { return x & 0x00ffffff; }
static inline INT64 SX64(INT64 x) { return (x & S64(0x0000800000000000)) ? x | S64(0xffff000000000000) : x & S64(0x0000ffffffffffff); } static inline INT64 SX64(INT64 x) { return (x & S64(0x0000800000000000)) ? x | S64(0xffff000000000000) : x & S64(0x0000ffffffffffff); }
static inline INT64 SC64(INT64 x) { return x & S64(0x0000ffffffffffff); } //static inline INT64 SC64(INT64 x) { return x & S64(0x0000ffffffffffff); }
#define VERBOSE 0 #define VERBOSE 0
#define VERBOSE_EXEC 0 #define VERBOSE_EXEC 0

28
src/emu/cpu/h83002/h8speriph.c
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@ -228,15 +228,15 @@ const int TPU_3_DIV[] = { 1, 4, 16, 64, 0, 1024, 256, 4096 };
const int TPU_4_DIV[] = { 1, 4, 16, 64, 0, 0, 1024, 0 }; const int TPU_4_DIV[] = { 1, 4, 16, 64, 0, 0, 1024, 0 };
const int TPU_5_DIV[] = { 1, 4, 16, 64, 0, 0, 256, 0 }; const int TPU_5_DIV[] = { 1, 4, 16, 64, 0, 0, 256, 0 };
const int H8S_IO_SMR[] = { H8S_IO_SMR0, H8S_IO_SMR1, H8S_IO_SMR2 }; //const int H8S_IO_SMR[] = { H8S_IO_SMR0, H8S_IO_SMR1, H8S_IO_SMR2 };
const int H8S_IO_BRR[] = { H8S_IO_BRR0, H8S_IO_BRR1, H8S_IO_BRR2 }; //const int H8S_IO_BRR[] = { H8S_IO_BRR0, H8S_IO_BRR1, H8S_IO_BRR2 };
const int H8S_IO_SCR[] = { H8S_IO_SCR0, H8S_IO_SCR1, H8S_IO_SCR2 }; //const int H8S_IO_SCR[] = { H8S_IO_SCR0, H8S_IO_SCR1, H8S_IO_SCR2 };
const int H8S_IO_TDR[] = { H8S_IO_TDR0, H8S_IO_TDR1, H8S_IO_TDR2 }; //const int H8S_IO_TDR[] = { H8S_IO_TDR0, H8S_IO_TDR1, H8S_IO_TDR2 };
const int H8S_IO_SSR[] = { H8S_IO_SSR0, H8S_IO_SSR1, H8S_IO_SSR2 }; //const int H8S_IO_SSR[] = { H8S_IO_SSR0, H8S_IO_SSR1, H8S_IO_SSR2 };
const int H8S_IO_RDR[] = { H8S_IO_RDR0, H8S_IO_RDR1, H8S_IO_RDR2 }; //const int H8S_IO_RDR[] = { H8S_IO_RDR0, H8S_IO_RDR1, H8S_IO_RDR2 };
const int H8S_INT_TXI[] = { H8S_INT_TXI0, H8S_INT_TXI1, H8S_INT_TXI2 }; //const int H8S_INT_TXI[] = { H8S_INT_TXI0, H8S_INT_TXI1, H8S_INT_TXI2 };
const int H8S_INT_RXI[] = { H8S_INT_RXI0, H8S_INT_RXI1, H8S_INT_RXI2 }; //const int H8S_INT_RXI[] = { H8S_INT_RXI0, H8S_INT_RXI1, H8S_INT_RXI2 };
const int H8S_IO_TCORA[] = { H8S_IO_TCORA0, H8S_IO_TCORA1 }; const int H8S_IO_TCORA[] = { H8S_IO_TCORA0, H8S_IO_TCORA1 };
const int H8S_IO_TCORB[] = { H8S_IO_TCORB0, H8S_IO_TCORB1 }; const int H8S_IO_TCORB[] = { H8S_IO_TCORB0, H8S_IO_TCORB1 };
@ -249,15 +249,15 @@ const int H8S_INT_CMIA[] = { H8S_INT_CMIA0, H8S_INT_CMIA1 };
const int H8S_INT_CMIB[] = { H8S_INT_CMIB0, H8S_INT_CMIB1 }; const int H8S_INT_CMIB[] = { H8S_INT_CMIB0, H8S_INT_CMIB1 };
const int H8S_IO_TGRA_H[] = { H8S_IO_TGR0A_H, H8S_IO_TGR1A_H, H8S_IO_TGR2A_H, H8S_IO_TGR3A_H, H8S_IO_TGR4A_H, H8S_IO_TGR5A_H }; const int H8S_IO_TGRA_H[] = { H8S_IO_TGR0A_H, H8S_IO_TGR1A_H, H8S_IO_TGR2A_H, H8S_IO_TGR3A_H, H8S_IO_TGR4A_H, H8S_IO_TGR5A_H };
const int H8S_IO_TGRA_L[] = { H8S_IO_TGR0A_L, H8S_IO_TGR1A_L, H8S_IO_TGR2A_L, H8S_IO_TGR3A_L, H8S_IO_TGR4A_L, H8S_IO_TGR5A_L }; //const int H8S_IO_TGRA_L[] = { H8S_IO_TGR0A_L, H8S_IO_TGR1A_L, H8S_IO_TGR2A_L, H8S_IO_TGR3A_L, H8S_IO_TGR4A_L, H8S_IO_TGR5A_L };
const int H8S_IO_TGRB_H[] = { H8S_IO_TGR0B_H, H8S_IO_TGR1B_H, H8S_IO_TGR2B_H, H8S_IO_TGR3B_H, H8S_IO_TGR4B_H, H8S_IO_TGR5B_H }; const int H8S_IO_TGRB_H[] = { H8S_IO_TGR0B_H, H8S_IO_TGR1B_H, H8S_IO_TGR2B_H, H8S_IO_TGR3B_H, H8S_IO_TGR4B_H, H8S_IO_TGR5B_H };
const int H8S_IO_TGRB_L[] = { H8S_IO_TGR0B_L, H8S_IO_TGR1B_L, H8S_IO_TGR2B_L, H8S_IO_TGR3B_L, H8S_IO_TGR4B_L, H8S_IO_TGR5B_L }; //const int H8S_IO_TGRB_L[] = { H8S_IO_TGR0B_L, H8S_IO_TGR1B_L, H8S_IO_TGR2B_L, H8S_IO_TGR3B_L, H8S_IO_TGR4B_L, H8S_IO_TGR5B_L };
const int H8S_IO_TGRC_H[] = { H8S_IO_TGR0C_H, 0, 0, H8S_IO_TGR3C_H, 0, 0 }; const int H8S_IO_TGRC_H[] = { H8S_IO_TGR0C_H, 0, 0, H8S_IO_TGR3C_H, 0, 0 };
const int H8S_IO_TGRC_L[] = { H8S_IO_TGR0C_L, 0, 0, H8S_IO_TGR3C_L, 0, 0 }; //const int H8S_IO_TGRC_L[] = { H8S_IO_TGR0C_L, 0, 0, H8S_IO_TGR3C_L, 0, 0 };
const int H8S_IO_TGRD_H[] = { H8S_IO_TGR0D_H, 0, 0, H8S_IO_TGR3D_H, 0, 0 }; const int H8S_IO_TGRD_H[] = { H8S_IO_TGR0D_H, 0, 0, H8S_IO_TGR3D_H, 0, 0 };
const int H8S_IO_TGRD_L[] = { H8S_IO_TGR0D_L, 0, 0, H8S_IO_TGR3D_L, 0, 0 }; //const int H8S_IO_TGRD_L[] = { H8S_IO_TGR0D_L, 0, 0, H8S_IO_TGR3D_L, 0, 0 };
const int H8S_IO_TCNT_H[] = { H8S_IO_TCNT0_H, H8S_IO_TCNT1_H, H8S_IO_TCNT2_H, H8S_IO_TCNT3_H, H8S_IO_TCNT4_H, H8S_IO_TCNT5_H }; const int H8S_IO_TCNT_H[] = { H8S_IO_TCNT0_H, H8S_IO_TCNT1_H, H8S_IO_TCNT2_H, H8S_IO_TCNT3_H, H8S_IO_TCNT4_H, H8S_IO_TCNT5_H };
const int H8S_IO_TCNT_L[] = { H8S_IO_TCNT0_L, H8S_IO_TCNT1_L, H8S_IO_TCNT2_L, H8S_IO_TCNT3_L, H8S_IO_TCNT4_L, H8S_IO_TCNT5_L }; //const int H8S_IO_TCNT_L[] = { H8S_IO_TCNT0_L, H8S_IO_TCNT1_L, H8S_IO_TCNT2_L, H8S_IO_TCNT3_L, H8S_IO_TCNT4_L, H8S_IO_TCNT5_L };
const int H8S_IO_TIOR_H[] = { H8S_IO_TIOR0_H, H8S_IO_TIOR1, H8S_IO_TIOR2, H8S_IO_TIOR3_H, H8S_IO_TIOR4, H8S_IO_TIOR5 }; const int H8S_IO_TIOR_H[] = { H8S_IO_TIOR0_H, H8S_IO_TIOR1, H8S_IO_TIOR2, H8S_IO_TIOR3_H, H8S_IO_TIOR4, H8S_IO_TIOR5 };
const int H8S_IO_TIOR_L[] = { H8S_IO_TIOR0_L, 0, 0, H8S_IO_TIOR3_L, 0, 0 }; const int H8S_IO_TIOR_L[] = { H8S_IO_TIOR0_L, 0, 0, H8S_IO_TIOR3_L, 0, 0 };
const int H8S_IO_TTCR[] = { H8S_IO_TTCR0, H8S_IO_TTCR1, H8S_IO_TTCR2, H8S_IO_TTCR3, H8S_IO_TTCR4, H8S_IO_TTCR5 }; const int H8S_IO_TTCR[] = { H8S_IO_TTCR0, H8S_IO_TTCR1, H8S_IO_TTCR2, H8S_IO_TTCR3, H8S_IO_TTCR4, H8S_IO_TTCR5 };
@ -265,7 +265,7 @@ const int H8S_IO_TIER[] = { H8S_IO_TIER0, H8S_IO_TIER1, H8S_IO_TIER2, H8S_IO_T
const int H8S_IO_TSR[] = { H8S_IO_TSR0, H8S_IO_TSR1, H8S_IO_TSR2, H8S_IO_TSR3, H8S_IO_TSR4, H8S_IO_TSR5 }; const int H8S_IO_TSR[] = { H8S_IO_TSR0, H8S_IO_TSR1, H8S_IO_TSR2, H8S_IO_TSR3, H8S_IO_TSR4, H8S_IO_TSR5 };
const int H8S_INT_TCIV[] = { H8S_INT_TCI0V, H8S_INT_TCI1V, H8S_INT_TCI2V, H8S_INT_TCI3V, H8S_INT_TCI4V, H8S_INT_TCI5V }; const int H8S_INT_TCIV[] = { H8S_INT_TCI0V, H8S_INT_TCI1V, H8S_INT_TCI2V, H8S_INT_TCI3V, H8S_INT_TCI4V, H8S_INT_TCI5V };
const int H8S_INT_TCIU[] = { 0, H8S_INT_TCI1U, H8S_INT_TCI2U, 0, H8S_INT_TCI4U, H8S_INT_TCI5U }; //const int H8S_INT_TCIU[] = { 0, H8S_INT_TCI1U, H8S_INT_TCI2U, 0, H8S_INT_TCI4U, H8S_INT_TCI5U };
const int H8S_INT_TGIA[] = { H8S_INT_TGI0A, H8S_INT_TGI1A, H8S_INT_TGI2A, H8S_INT_TGI3A, H8S_INT_TGI4A, H8S_INT_TGI5A }; const int H8S_INT_TGIA[] = { H8S_INT_TGI0A, H8S_INT_TGI1A, H8S_INT_TGI2A, H8S_INT_TGI3A, H8S_INT_TGI4A, H8S_INT_TGI5A };
const int H8S_INT_TGIB[] = { H8S_INT_TGI0B, H8S_INT_TGI1B, H8S_INT_TGI2B, H8S_INT_TGI3B, H8S_INT_TGI4B, H8S_INT_TGI5B }; const int H8S_INT_TGIB[] = { H8S_INT_TGI0B, H8S_INT_TGI1B, H8S_INT_TGI2B, H8S_INT_TGI3B, H8S_INT_TGI4B, H8S_INT_TGI5B };
const int H8S_INT_TGIC[] = { H8S_INT_TGI0C, 0, 0, H8S_INT_TGI3C, 0, 0 }; const int H8S_INT_TGIC[] = { H8S_INT_TGI0C, 0, 0, H8S_INT_TGI3C, 0, 0 };

2
src/emu/cpu/i386/i386dasm.c
View File

@ -1960,6 +1960,7 @@ INLINE UINT8 FETCH(void)
return *opcode_ptr++; return *opcode_ptr++;
} }
#if 0
INLINE UINT16 FETCH16(void) INLINE UINT16 FETCH16(void)
{ {
UINT16 d; UINT16 d;
@ -1970,6 +1971,7 @@ INLINE UINT16 FETCH16(void)
pc += 2; pc += 2;
return d; return d;
} }
#endif
INLINE UINT32 FETCH32(void) INLINE UINT32 FETCH32(void)
{ {

2
src/emu/cpu/nec/necdasm.c
View File

@ -881,6 +881,7 @@ INLINE UINT8 FETCH(void)
return *opcode_ptr++; return *opcode_ptr++;
} }
#if 0
INLINE UINT16 FETCH16(void) INLINE UINT16 FETCH16(void)
{ {
UINT16 d; UINT16 d;
@ -891,6 +892,7 @@ INLINE UINT16 FETCH16(void)
pc += 2; pc += 2;
return d; return d;
} }
#endif
INLINE UINT8 FETCHD(void) INLINE UINT8 FETCHD(void)
{ {

4
src/emu/cpu/powerpc/ppccom.c
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@ -204,6 +204,7 @@ INLINE void set_decrementer(powerpc_state *ppc, UINT32 newdec)
} }
#if 0
/*------------------------------------------------- /*-------------------------------------------------
is_nan_double - is a double value a NaN is_nan_double - is a double value a NaN
-------------------------------------------------*/ -------------------------------------------------*/
@ -214,6 +215,7 @@ INLINE int is_nan_double(double x)
return( ((xi & DOUBLE_EXP) == DOUBLE_EXP) && return( ((xi & DOUBLE_EXP) == DOUBLE_EXP) &&
((xi & DOUBLE_FRAC) != DOUBLE_ZERO) ); ((xi & DOUBLE_FRAC) != DOUBLE_ZERO) );
} }
#endif
/*------------------------------------------------- /*-------------------------------------------------
@ -230,6 +232,7 @@ INLINE int is_qnan_double(double x)
} }
#if 0
/*------------------------------------------------- /*-------------------------------------------------
is_snan_double - is a double value a is_snan_double - is a double value a
signaling NaN signaling NaN
@ -242,6 +245,7 @@ INLINE int is_snan_double(double x)
((xi & DOUBLE_FRAC) != DOUBLE_ZERO) && ((xi & DOUBLE_FRAC) != DOUBLE_ZERO) &&
((xi & U64(0x0008000000000000)) == DOUBLE_ZERO) ); ((xi & U64(0x0008000000000000)) == DOUBLE_ZERO) );
} }
#endif
/*------------------------------------------------- /*-------------------------------------------------

2
src/emu/cpu/rsp/rspdrc.c
View File

@ -2116,6 +2116,7 @@ INLINE UINT16 SATURATE_ACCUM1(rsp_state *rsp, int accum, UINT16 negative, UINT16
return 0; return 0;
} }
#if 0
INLINE UINT16 C_SATURATE_ACCUM1(UINT16 *h, UINT16 *m, int accum, UINT16 negative, UINT16 positive) INLINE UINT16 C_SATURATE_ACCUM1(UINT16 *h, UINT16 *m, int accum, UINT16 negative, UINT16 positive)
{ {
// Return negative if H<0 && (H!=0xffff || M >= 0) // Return negative if H<0 && (H!=0xffff || M >= 0)
@ -2161,6 +2162,7 @@ INLINE UINT16 C_SATURATE_ACCUM1(UINT16 *h, UINT16 *m, int accum, UINT16 negative
return 0; return 0;
} }
#endif
#if USE_SIMD #if USE_SIMD
#define WRITEBACK_RESULT() { \ #define WRITEBACK_RESULT() { \

2
src/emu/cpu/tms32031/dis32031.c
View File

@ -30,6 +30,7 @@
CODE CODE CODE CODE
***************************************************************************/ ***************************************************************************/
#if 0
INLINE char *signed_16bit(INT16 val) INLINE char *signed_16bit(INT16 val)
{ {
static char temp[10]; static char temp[10];
@ -39,6 +40,7 @@ INLINE char *signed_16bit(INT16 val)
sprintf(temp, "$%x", val); sprintf(temp, "$%x", val);
return temp; return temp;
} }
#endif
static const char *const regname[32] = static const char *const regname[32] =
{ {

6
src/emu/cpu/tms32031/tms32031.c
View File

@ -67,9 +67,9 @@ const int LVFLAG = 0x0020;
const int LUFFLAG = 0x0040; const int LUFFLAG = 0x0040;
const int OVMFLAG = 0x0080; const int OVMFLAG = 0x0080;
const int RMFLAG = 0x0100; const int RMFLAG = 0x0100;
const int CFFLAG = 0x0400; //const int CFFLAG = 0x0400;
const int CEFLAG = 0x0800; //const int CEFLAG = 0x0800;
const int CCFLAG = 0x1000; //const int CCFLAG = 0x1000;
const int GIEFLAG = 0x2000; const int GIEFLAG = 0x2000;

4
src/emu/cpu/tms34010/tms34010.c
View File

@ -1169,6 +1169,7 @@ UINT32 tms34010_device::tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitm
I/O REGISTER WRITES I/O REGISTER WRITES
***************************************************************************/ ***************************************************************************/
#if 0
static const char *const ioreg_name[] = static const char *const ioreg_name[] =
{ {
"HESYNC", "HEBLNK", "HSBLNK", "HTOTAL", "HESYNC", "HEBLNK", "HSBLNK", "HTOTAL",
@ -1181,6 +1182,7 @@ static const char *const ioreg_name[] =
"RESERVED", "RESERVED", "RESERVED", "DPYTAP", "RESERVED", "RESERVED", "RESERVED", "DPYTAP",
"HCOUNT", "VCOUNT", "DPYADR", "REFCNT" "HCOUNT", "VCOUNT", "DPYADR", "REFCNT"
}; };
#endif
WRITE16_HANDLER( tms34010_io_register_w ) WRITE16_HANDLER( tms34010_io_register_w )
{ {
@ -1302,6 +1304,7 @@ WRITE16_HANDLER( tms34010_io_register_w )
} }
#if 0
static const char *const ioreg020_name[] = static const char *const ioreg020_name[] =
{ {
"VESYNC", "HESYNC", "VEBLNK", "HEBLNK", "VESYNC", "HESYNC", "VEBLNK", "HEBLNK",
@ -1324,6 +1327,7 @@ static const char *const ioreg020_name[] =
"IHOST1L", "IHOST1H", "IHOST2L", "IHOST2H", "IHOST1L", "IHOST1H", "IHOST2L", "IHOST2H",
"IHOST3L", "IHOST3H", "IHOST4L", "IHOST4H" "IHOST3L", "IHOST3H", "IHOST4L", "IHOST4H"
}; };
#endif
WRITE16_HANDLER( tms34020_io_register_w ) WRITE16_HANDLER( tms34020_io_register_w )
{ {

2
src/emu/dimemory.c
View File

@ -24,7 +24,7 @@
// CONSTANTS // CONSTANTS
//************************************************************************** //**************************************************************************
const int TRIGGER_SUSPENDTIME = -4000; //const int TRIGGER_SUSPENDTIME = -4000;

2
src/emu/emualloc.c
View File

@ -25,7 +25,7 @@
//************************************************************************** //**************************************************************************
// align all allocated memory to this size // align all allocated memory to this size
const int memory_align = 16; //const int memory_align = 16;
// number of memory_entries to allocate in a block // number of memory_entries to allocate in a block
const int memory_block_alloc_chunk = 256; const int memory_block_alloc_chunk = 256;

4
src/emu/machine/laserdsc.c
View File

@ -38,8 +38,8 @@ const UINT32 LEAD_OUT_MIN_SIZE_IN_UM = 2000; // 2 mm
// the track pitch is defined as a range; we pick a nominal pitch // the track pitch is defined as a range; we pick a nominal pitch
// that ensures we can fit 54,000 tracks // that ensures we can fit 54,000 tracks
const UINT32 MIN_TRACK_PITCH_IN_NM = 1400; // 1.4 um //const UINT32 MIN_TRACK_PITCH_IN_NM = 1400; // 1.4 um
const UINT32 MAX_TRACK_PITCH_IN_NM = 2000; // 2 um //const UINT32 MAX_TRACK_PITCH_IN_NM = 2000; // 2 um
const UINT32 NOMINAL_TRACK_PITCH_IN_NM = (PROGRAM_MAX_RADIUS_IN_UM - PROGRAM_MIN_RADIUS_IN_UM) * 1000 / 54000; const UINT32 NOMINAL_TRACK_PITCH_IN_NM = (PROGRAM_MAX_RADIUS_IN_UM - PROGRAM_MIN_RADIUS_IN_UM) * 1000 / 54000;
// we simulate extra lead-in and lead-out tracks // we simulate extra lead-in and lead-out tracks

2
src/emu/machine/rp5c01.c
View File

@ -67,7 +67,7 @@ static const int REGISTER_WRITE_MASK[2][16] =
// days per month // days per month
static const int DAYS_PER_MONTH[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //static const int DAYS_PER_MONTH[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
// modes // modes

10
src/emu/machine/z80ctc.c
View File

@ -33,14 +33,14 @@
// these are the bits of the incoming commands to the CTC // these are the bits of the incoming commands to the CTC
const int INTERRUPT = 0x80; const int INTERRUPT = 0x80;
const int INTERRUPT_ON = 0x80; const int INTERRUPT_ON = 0x80;
const int INTERRUPT_OFF = 0x00; //const int INTERRUPT_OFF = 0x00;
const int MODE = 0x40; const int MODE = 0x40;
const int MODE_TIMER = 0x00; const int MODE_TIMER = 0x00;
const int MODE_COUNTER = 0x40; const int MODE_COUNTER = 0x40;
const int PRESCALER = 0x20; const int PRESCALER = 0x20;
const int PRESCALER_256 = 0x20; //const int PRESCALER_256 = 0x20;
const int PRESCALER_16 = 0x00; const int PRESCALER_16 = 0x00;
const int EDGE = 0x10; const int EDGE = 0x10;
@ -49,14 +49,14 @@ const int EDGE_RISING = 0x10;
const int TRIGGER = 0x08; const int TRIGGER = 0x08;
const int TRIGGER_AUTO = 0x00; const int TRIGGER_AUTO = 0x00;
const int TRIGGER_CLOCK = 0x08; //const int TRIGGER_CLOCK = 0x08;
const int CONSTANT = 0x04; const int CONSTANT = 0x04;
const int CONSTANT_LOAD = 0x04; const int CONSTANT_LOAD = 0x04;
const int CONSTANT_NONE = 0x00; //const int CONSTANT_NONE = 0x00;
const int RESET = 0x02; const int RESET = 0x02;
const int RESET_CONTINUE = 0x00; //const int RESET_CONTINUE = 0x00;
const int RESET_ACTIVE = 0x02; const int RESET_ACTIVE = 0x02;
const int CONTROL = 0x01; const int CONTROL = 0x01;

12
src/emu/machine/z80pio.c
View File

@ -36,12 +36,12 @@ enum
}; };
const int ICW_ENABLE_INT = 0x80; const int ICW_ENABLE_INT = 0x80;
const int ICW_AND_OR = 0x40; //const int ICW_AND_OR = 0x40;
const int ICW_AND = 0x40; //const int ICW_AND = 0x40;
const int ICW_OR = 0x00; //const int ICW_OR = 0x00;
const int ICW_HIGH_LOW = 0x20; //const int ICW_HIGH_LOW = 0x20;
const int ICW_HIGH = 0x20; //const int ICW_HIGH = 0x20;
const int ICW_LOW = 0x00; //const int ICW_LOW = 0x00;
const int ICW_MASK_FOLLOWS = 0x10; const int ICW_MASK_FOLLOWS = 0x10;

122
src/emu/machine/z80sio.c
View File

@ -47,105 +47,105 @@ const int INT_CHA_RECEIVE = 4 + INT_RECEIVE;
const int INT_CHA_ERROR = 4 + INT_ERROR; const int INT_CHA_ERROR = 4 + INT_ERROR;
// SIO write register 0 // SIO write register 0
const int SIO_WR0_RESET_MASK = 0xc0; // D7-D6: Reset control //const int SIO_WR0_RESET_MASK = 0xc0; // D7-D6: Reset control
const int SIO_WR0_RESET_NULL = 0x00; // 00 = NULL code //const int SIO_WR0_RESET_NULL = 0x00; // 00 = NULL code
const int SIO_WR0_RESET_RX_CRC = 0x40; // 01 = Reset Rx CRC checker //const int SIO_WR0_RESET_RX_CRC = 0x40; // 01 = Reset Rx CRC checker
const int SIO_WR0_RESET_TX_CRC = 0x80; // 10 = Reset Tx CRC generator //const int SIO_WR0_RESET_TX_CRC = 0x80; // 10 = Reset Tx CRC generator
const int SIO_WR0_RESET_TX_LATCH = 0xc0; // 11 = Reset Tx Underrun/EOM latch //const int SIO_WR0_RESET_TX_LATCH = 0xc0; // 11 = Reset Tx Underrun/EOM latch
const int SIO_WR0_COMMAND_MASK = 0x38; // D5-D3: Command const int SIO_WR0_COMMAND_MASK = 0x38; // D5-D3: Command
const int SIO_WR0_COMMAND_NULL = 0x00; // 000 = NULL code //const int SIO_WR0_COMMAND_NULL = 0x00; // 000 = NULL code
const int SIO_WR0_COMMAND_SET_ABORT = 0x08; // 001 = Set abort (SDLC) //const int SIO_WR0_COMMAND_SET_ABORT = 0x08; // 001 = Set abort (SDLC)
const int SIO_WR0_COMMAND_RES_STATUS_INT = 0x10; // 010 = reset ext/status interrupts const int SIO_WR0_COMMAND_RES_STATUS_INT = 0x10; // 010 = reset ext/status interrupts
const int SIO_WR0_COMMAND_CH_RESET = 0x18; // 011 = Channel reset const int SIO_WR0_COMMAND_CH_RESET = 0x18; // 011 = Channel reset
const int SIO_WR0_COMMAND_ENA_RX_INT = 0x20; // 100 = Enable int on next Rx character const int SIO_WR0_COMMAND_ENA_RX_INT = 0x20; // 100 = Enable int on next Rx character
const int SIO_WR0_COMMAND_RES_TX_INT = 0x28; // 101 = Reset Tx int pending const int SIO_WR0_COMMAND_RES_TX_INT = 0x28; // 101 = Reset Tx int pending
const int SIO_WR0_COMMAND_RES_ERROR = 0x30; // 110 = Error reset const int SIO_WR0_COMMAND_RES_ERROR = 0x30; // 110 = Error reset
const int SIO_WR0_COMMAND_RETI = 0x38; // 111 = Return from int (CH-A only) //const int SIO_WR0_COMMAND_RETI = 0x38; // 111 = Return from int (CH-A only)
const int SIO_WR0_REGISTER_MASK = 0x07; // D2-D0: Register select (0-7) //const int SIO_WR0_REGISTER_MASK = 0x07; // D2-D0: Register select (0-7)
// SIO write register 1 // SIO write register 1
const int SIO_WR1_READY_WAIT_ENA = 0x80; // D7 = READY/WAIT enable //const int SIO_WR1_READY_WAIT_ENA = 0x80; // D7 = READY/WAIT enable
const int SIO_WR1_READY_WAIT_FUNCTION = 0x40; // D6 = READY/WAIT function //const int SIO_WR1_READY_WAIT_FUNCTION = 0x40; // D6 = READY/WAIT function
const int SIO_WR1_READY_WAIT_ON_RT = 0x20; // D5 = READY/WAIT on R/T //const int SIO_WR1_READY_WAIT_ON_RT = 0x20; // D5 = READY/WAIT on R/T
const int SIO_WR1_RXINT_MASK = 0x18; // D4-D3 = Rx int control const int SIO_WR1_RXINT_MASK = 0x18; // D4-D3 = Rx int control
const int SIO_WR1_RXINT_DISABLE = 0x00; // 00 = Rx int disable //const int SIO_WR1_RXINT_DISABLE = 0x00; // 00 = Rx int disable
const int SIO_WR1_RXINT_FIRST = 0x08; // 01 = Rx int on first character const int SIO_WR1_RXINT_FIRST = 0x08; // 01 = Rx int on first character
const int SIO_WR1_RXINT_ALL_PARITY = 0x10; // 10 = int on all Rx characters (parity affects vector) const int SIO_WR1_RXINT_ALL_PARITY = 0x10; // 10 = int on all Rx characters (parity affects vector)
const int SIO_WR1_RXINT_ALL_NOPARITY = 0x18; // 11 = int on all Rx characters (parity ignored) const int SIO_WR1_RXINT_ALL_NOPARITY = 0x18; // 11 = int on all Rx characters (parity ignored)
const int SIO_WR1_STATUS_AFFECTS_VECTOR = 0x04; // D2 = Status affects vector (CH-B only) //const int SIO_WR1_STATUS_AFFECTS_VECTOR = 0x04; // D2 = Status affects vector (CH-B only)
const int SIO_WR1_TXINT_ENABLE = 0x02; // D1 = Tx int enable const int SIO_WR1_TXINT_ENABLE = 0x02; // D1 = Tx int enable
const int SIO_WR1_STATUSINT_ENABLE = 0x01; // D0 = Ext int enable const int SIO_WR1_STATUSINT_ENABLE = 0x01; // D0 = Ext int enable
// SIO write register 2 (CH-B only) // SIO write register 2 (CH-B only)
const int SIO_WR2_INT_VECTOR_MASK = 0xff; // D7-D0 = interrupt vector //const int SIO_WR2_INT_VECTOR_MASK = 0xff; // D7-D0 = interrupt vector
// SIO write register 3 // SIO write register 3
const int SIO_WR3_RX_DATABITS_MASK = 0xc0; // D7-D6 = Rx Data bits //const int SIO_WR3_RX_DATABITS_MASK = 0xc0; // D7-D6 = Rx Data bits
const int SIO_WR3_RX_DATABITS_5 = 0x00; // 00 = Rx 5 bits/character //const int SIO_WR3_RX_DATABITS_5 = 0x00; // 00 = Rx 5 bits/character
const int SIO_WR3_RX_DATABITS_7 = 0x40; // 01 = Rx 7 bits/character //const int SIO_WR3_RX_DATABITS_7 = 0x40; // 01 = Rx 7 bits/character
const int SIO_WR3_RX_DATABITS_6 = 0x80; // 10 = Rx 6 bits/character //const int SIO_WR3_RX_DATABITS_6 = 0x80; // 10 = Rx 6 bits/character
const int SIO_WR3_RX_DATABITS_8 = 0xc0; // 11 = Rx 8 bits/character //const int SIO_WR3_RX_DATABITS_8 = 0xc0; // 11 = Rx 8 bits/character
const int SIO_WR3_AUTO_ENABLES = 0x20; // D5 = Auto enables //const int SIO_WR3_AUTO_ENABLES = 0x20; // D5 = Auto enables
const int SIO_WR3_ENTER_HUNT_PHASE = 0x10; // D4 = Enter hunt phase //const int SIO_WR3_ENTER_HUNT_PHASE = 0x10; // D4 = Enter hunt phase
const int SIO_WR3_RX_CRC_ENABLE = 0x08; // D3 = Rx CRC enable //const int SIO_WR3_RX_CRC_ENABLE = 0x08; // D3 = Rx CRC enable
const int SIO_WR3_ADDR_SEARCH_MODE = 0x04; // D2 = Address search mode (SDLC) //const int SIO_WR3_ADDR_SEARCH_MODE = 0x04; // D2 = Address search mode (SDLC)
const int SIO_WR3_SYNC_LOAD_INHIBIT = 0x02; // D1 = Sync character load inhibit //const int SIO_WR3_SYNC_LOAD_INHIBIT = 0x02; // D1 = Sync character load inhibit
const int SIO_WR3_RX_ENABLE = 0x01; // D0 = Rx enable const int SIO_WR3_RX_ENABLE = 0x01; // D0 = Rx enable
// SIO write register 4 // SIO write register 4
const int SIO_WR4_CLOCK_MODE_MASK = 0xc0; // D7-D6 = Clock mode //const int SIO_WR4_CLOCK_MODE_MASK = 0xc0; // D7-D6 = Clock mode
const int SIO_WR4_CLOCK_MODE_x1 = 0x00; // 00 = x1 clock mode //const int SIO_WR4_CLOCK_MODE_x1 = 0x00; // 00 = x1 clock mode
const int SIO_WR4_CLOCK_MODE_x16 = 0x40; // 01 = x16 clock mode //const int SIO_WR4_CLOCK_MODE_x16 = 0x40; // 01 = x16 clock mode
const int SIO_WR4_CLOCK_MODE_x32 = 0x80; // 10 = x32 clock mode //const int SIO_WR4_CLOCK_MODE_x32 = 0x80; // 10 = x32 clock mode
const int SIO_WR4_CLOCK_MODE_x64 = 0xc0; // 11 = x64 clock mode //const int SIO_WR4_CLOCK_MODE_x64 = 0xc0; // 11 = x64 clock mode
const int SIO_WR4_SYNC_MODE_MASK = 0x30; // D5-D4 = Sync mode //const int SIO_WR4_SYNC_MODE_MASK = 0x30; // D5-D4 = Sync mode
const int SIO_WR4_SYNC_MODE_8BIT = 0x00; // 00 = 8 bit sync character //const int SIO_WR4_SYNC_MODE_8BIT = 0x00; // 00 = 8 bit sync character
const int SIO_WR4_SYNC_MODE_16BIT = 0x10; // 01 = 16 bit sync character //const int SIO_WR4_SYNC_MODE_16BIT = 0x10; // 01 = 16 bit sync character
const int SIO_WR4_SYNC_MODE_SDLC = 0x20; // 10 = SDLC mode (01111110 flag) //const int SIO_WR4_SYNC_MODE_SDLC = 0x20; // 10 = SDLC mode (01111110 flag)
const int SIO_WR4_SYNC_MODE_EXTERNAL = 0x30; // 11 = External sync mode //const int SIO_WR4_SYNC_MODE_EXTERNAL = 0x30; // 11 = External sync mode
const int SIO_WR4_STOPBITS_MASK = 0x0c; // D3-D2 = Stop bits //const int SIO_WR4_STOPBITS_MASK = 0x0c; // D3-D2 = Stop bits
const int SIO_WR4_STOPBITS_SYNC = 0x00; // 00 = Sync modes enable //const int SIO_WR4_STOPBITS_SYNC = 0x00; // 00 = Sync modes enable
const int SIO_WR4_STOPBITS_1 = 0x04; // 01 = 1 stop bit/character //const int SIO_WR4_STOPBITS_1 = 0x04; // 01 = 1 stop bit/character
const int SIO_WR4_STOPBITS_15 = 0x08; // 10 = 1.5 stop bits/character //const int SIO_WR4_STOPBITS_15 = 0x08; // 10 = 1.5 stop bits/character
const int SIO_WR4_STOPBITS_2 = 0x0c; // 11 = 2 stop bits/character //const int SIO_WR4_STOPBITS_2 = 0x0c; // 11 = 2 stop bits/character
const int SIO_WR4_PARITY_EVEN = 0x02; // D1 = Parity even/odd //const int SIO_WR4_PARITY_EVEN = 0x02; // D1 = Parity even/odd
const int SIO_WR4_PARITY_ENABLE = 0x01; // D0 = Parity enable //const int SIO_WR4_PARITY_ENABLE = 0x01; // D0 = Parity enable
// SIO write register 5 // SIO write register 5
const int SIO_WR5_DTR = 0x80; // D7 = DTR const int SIO_WR5_DTR = 0x80; // D7 = DTR
const int SIO_WR5_TX_DATABITS_MASK = 0x60; // D6-D5 = Tx Data bits //const int SIO_WR5_TX_DATABITS_MASK = 0x60; // D6-D5 = Tx Data bits
const int SIO_WR5_TX_DATABITS_5 = 0x00; // 00 = Tx 5 bits/character //const int SIO_WR5_TX_DATABITS_5 = 0x00; // 00 = Tx 5 bits/character
const int SIO_WR5_TX_DATABITS_7 = 0x20; // 01 = Tx 7 bits/character //const int SIO_WR5_TX_DATABITS_7 = 0x20; // 01 = Tx 7 bits/character
const int SIO_WR5_TX_DATABITS_6 = 0x40; // 10 = Tx 6 bits/character //const int SIO_WR5_TX_DATABITS_6 = 0x40; // 10 = Tx 6 bits/character
const int SIO_WR5_TX_DATABITS_8 = 0x60; // 11 = Tx 8 bits/character //const int SIO_WR5_TX_DATABITS_8 = 0x60; // 11 = Tx 8 bits/character
const int SIO_WR5_SEND_BREAK = 0x10; // D4 = Send break const int SIO_WR5_SEND_BREAK = 0x10; // D4 = Send break
const int SIO_WR5_TX_ENABLE = 0x08; // D3 = Tx Enable const int SIO_WR5_TX_ENABLE = 0x08; // D3 = Tx Enable
const int SIO_WR5_CRC16_SDLC = 0x04; // D2 = CRC-16/SDLC //const int SIO_WR5_CRC16_SDLC = 0x04; // D2 = CRC-16/SDLC
const int SIO_WR5_RTS = 0x02; // D1 = RTS const int SIO_WR5_RTS = 0x02; // D1 = RTS
const int SIO_WR5_TX_CRC_ENABLE = 0x01; // D0 = Tx CRC enable //const int SIO_WR5_TX_CRC_ENABLE = 0x01; // D0 = Tx CRC enable
// SIO write register 6 // SIO write register 6
const int SIO_WR6_SYNC_7_0_MASK = 0xff; // D7-D0 = Sync bits 7-0 //const int SIO_WR6_SYNC_7_0_MASK = 0xff; // D7-D0 = Sync bits 7-0
// SIO write register 7 // SIO write register 7
const int SIO_WR7_SYNC_15_8_MASK = 0xff; // D7-D0 = Sync bits 15-8 //const int SIO_WR7_SYNC_15_8_MASK = 0xff; // D7-D0 = Sync bits 15-8
// SIO read register 0 // SIO read register 0
const int SIO_RR0_BREAK_ABORT = 0x80; // D7 = Break/abort //const int SIO_RR0_BREAK_ABORT = 0x80; // D7 = Break/abort
const int SIO_RR0_TX_UNDERRUN = 0x40; // D6 = Tx underrun/EOM //const int SIO_RR0_TX_UNDERRUN = 0x40; // D6 = Tx underrun/EOM
const int SIO_RR0_CTS = 0x20; // D5 = CTS const int SIO_RR0_CTS = 0x20; // D5 = CTS
const int SIO_RR0_SYNC_HUNT = 0x10; // D4 = Sync/hunt //const int SIO_RR0_SYNC_HUNT = 0x10; // D4 = Sync/hunt
const int SIO_RR0_DCD = 0x08; // D3 = DCD const int SIO_RR0_DCD = 0x08; // D3 = DCD
const int SIO_RR0_TX_BUFFER_EMPTY = 0x04; // D2 = Tx buffer empty const int SIO_RR0_TX_BUFFER_EMPTY = 0x04; // D2 = Tx buffer empty
const int SIO_RR0_INT_PENDING = 0x02; // D1 = int pending (CH-A only) const int SIO_RR0_INT_PENDING = 0x02; // D1 = int pending (CH-A only)
const int SIO_RR0_RX_CHAR_AVAILABLE = 0x01; // D0 = Rx character available const int SIO_RR0_RX_CHAR_AVAILABLE = 0x01; // D0 = Rx character available
// SIO read register 1 // SIO read register 1
const int SIO_RR1_END_OF_FRAME = 0x80; // D7 = End of frame (SDLC) //const int SIO_RR1_END_OF_FRAME = 0x80; // D7 = End of frame (SDLC)
const int SIO_RR1_CRC_FRAMING_ERROR = 0x40; // D6 = CRC/Framing error //const int SIO_RR1_CRC_FRAMING_ERROR = 0x40; // D6 = CRC/Framing error
const int SIO_RR1_RX_OVERRUN_ERROR = 0x20; // D5 = Rx overrun error //const int SIO_RR1_RX_OVERRUN_ERROR = 0x20; // D5 = Rx overrun error
const int SIO_RR1_PARITY_ERROR = 0x10; // D4 = Parity error //const int SIO_RR1_PARITY_ERROR = 0x10; // D4 = Parity error
const int SIO_RR1_IFIELD_BITS_MASK = 0x0e; // D3-D1 = I field bits //const int SIO_RR1_IFIELD_BITS_MASK = 0x0e; // D3-D1 = I field bits
// 100 = 0 in prev, 3 in 2nd prev // 100 = 0 in prev, 3 in 2nd prev
// 010 = 0 in prev, 4 in 2nd prev // 010 = 0 in prev, 4 in 2nd prev
// 110 = 0 in prev, 5 in 2nd prev // 110 = 0 in prev, 5 in 2nd prev
@ -154,10 +154,10 @@ const int SIO_RR1_IFIELD_BITS_MASK = 0x0e; // D3-D1 = I field bits
// 011 = 0 in prev, 8 in 2nd prev // 011 = 0 in prev, 8 in 2nd prev
// 111 = 1 in prev, 8 in 2nd prev // 111 = 1 in prev, 8 in 2nd prev
// 000 = 2 in prev, 8 in 2nd prev // 000 = 2 in prev, 8 in 2nd prev
const int SIO_RR1_ALL_SENT = 0x01; // D0 = All sent //const int SIO_RR1_ALL_SENT = 0x01; // D0 = All sent
// SIO read register 2 (CH-B only) // SIO read register 2 (CH-B only)
const int SIO_RR2_VECTOR_MASK = 0xff; // D7-D0 = Interrupt vector //const int SIO_RR2_VECTOR_MASK = 0xff; // D7-D0 = Interrupt vector
const UINT8 z80sio_device::k_int_priority[] = const UINT8 z80sio_device::k_int_priority[] =

8
src/emu/machine/z80sti.c
View File

@ -46,12 +46,12 @@ const device_type Z80STI = &device_creator<z80sti_device>;
//************************************************************************** //**************************************************************************
// timer C/D control register // timer C/D control register
const int TCDC_TARS = 0x80; //const int TCDC_TARS = 0x80;
const int TCDC_TBRS = 0x08; //const int TCDC_TBRS = 0x08;
// interrupt vector register // interrupt vector register
const int PVR_ISE = 0x08; //const int PVR_ISE = 0x08;
const int PVR_VR4 = 0x10; //const int PVR_VR4 = 0x10;
// general purpose I/O interrupt levels // general purpose I/O interrupt levels
const int z80sti_device::INT_LEVEL_GPIP[] = const int z80sti_device::INT_LEVEL_GPIP[] =

4
src/emu/softlist.c
View File

@ -151,6 +151,7 @@ INLINE void unknown_attribute(software_list *swlist, const char *attrname)
#if 0
/*------------------------------------------------- /*-------------------------------------------------
unknown_attribute_value unknown_attribute_value
-------------------------------------------------*/ -------------------------------------------------*/
@ -164,6 +165,7 @@ INLINE void unknown_attribute_value(software_list *swlist,
XML_GetCurrentLineNumber(swlist->state.parser), XML_GetCurrentLineNumber(swlist->state.parser),
XML_GetCurrentColumnNumber(swlist->state.parser)); XML_GetCurrentColumnNumber(swlist->state.parser));
} }
#endif
/*------------------------------------------------- /*-------------------------------------------------
@ -1298,6 +1300,7 @@ const char *software_list_get_description(const software_list *swlist)
} }
#if 0
/*------------------------------------------------- /*-------------------------------------------------
software_list_find_by_number software_list_find_by_number
-------------------------------------------------*/ -------------------------------------------------*/
@ -1315,6 +1318,7 @@ INLINE software_info *software_list_find_by_number(software_list *swlist, int nu
return cur_info; return cur_info;
} }
#endif
/*------------------------------------------------- /*-------------------------------------------------

2
src/emu/sound/fm2612.c
View File

@ -1010,11 +1010,13 @@ INLINE UINT8 FM_STATUS_FLAG(FM_ST *ST)
} }
return ST->status; return ST->status;
} }
#if 0
INLINE void FM_BUSY_SET(FM_ST *ST,int busyclock ) INLINE void FM_BUSY_SET(FM_ST *ST,int busyclock )
{ {
TIME_TYPE expiry_period = MULTIPLY_TIME_BY_INT(attotime::from_hz(ST->clock), busyclock * ST->timer_prescaler); TIME_TYPE expiry_period = MULTIPLY_TIME_BY_INT(attotime::from_hz(ST->clock), busyclock * ST->timer_prescaler);
ST->busy_expiry_time = ADD_TIMES(FM_GET_TIME_NOW(&ST->device->machine()), expiry_period); ST->busy_expiry_time = ADD_TIMES(FM_GET_TIME_NOW(&ST->device->machine()), expiry_period);
} }
#endif
#else #else
#define FM_STATUS_FLAG(ST) ((ST)->status) #define FM_STATUS_FLAG(ST) ((ST)->status)
#define FM_BUSY_SET(ST,bclock) {} #define FM_BUSY_SET(ST,bclock) {}

6
src/emu/sound/spu.c
View File

@ -126,7 +126,7 @@ enum srrr_flags
srrr_rr_mask=0x1f srrr_rr_mask=0x1f
}; };
static const unsigned int sound_buffer_size=65536*4, static const unsigned int /*sound_buffer_size=65536*4,*/
xa_sector_size=(18*28*8)<<1, xa_sector_size=(18*28*8)<<1,
xa_buffer_sectors=16, xa_buffer_sectors=16,
cdda_sector_size=2352, cdda_sector_size=2352,
@ -136,7 +136,7 @@ static const unsigned int sound_buffer_size=65536*4,
spu_ram_size=512*1024, spu_ram_size=512*1024,
spu_infinity=0xffffffff, spu_infinity=0xffffffff,
output_buffer_size=65536/8, output_buffer_size=65536/8/*,
sample_loop_cache_pool_size=64, sample_loop_cache_pool_size=64,
sample_loop_cache_extend_size=64, sample_loop_cache_extend_size=64,
@ -144,7 +144,7 @@ static const unsigned int sound_buffer_size=65536*4,
sample_cache_extend_size=64, sample_cache_extend_size=64,
stream_marker_pool_size=64, stream_marker_pool_size=64,
stream_marker_extend_size=64; stream_marker_extend_size=64*/;
// //
// //

10
src/emu/video/crt9007.c
View File

@ -200,15 +200,15 @@ enum
// interrupt enable register bits // interrupt enable register bits
const int IE_VERTICAL_RETRACE = 0x40; const int IE_VERTICAL_RETRACE = 0x40;
const int IE_LIGHT_PEN = 0x20; //const int IE_LIGHT_PEN = 0x20;
const int IE_FRAME_TIMER = 0x01; //const int IE_FRAME_TIMER = 0x01;
// status register bits // status register bits
const int STATUS_INTERRUPT_PENDING = 0x80; const int STATUS_INTERRUPT_PENDING = 0x80;
const int STATUS_VERTICAL_RETRACE = 0x40; //const int STATUS_VERTICAL_RETRACE = 0x40;
const int STATUS_LIGHT_PEN_UPDATE = 0x20; const int STATUS_LIGHT_PEN_UPDATE = 0x20;
const int STATUS_ODD_EVEN = 0x04; //const int STATUS_ODD_EVEN = 0x04;
const int STATUS_FRAME_TIMER_OCCURRED = 0x01; //const int STATUS_FRAME_TIMER_OCCURRED = 0x01;

2
src/emu/video/pc_cga.c
View File

@ -775,6 +775,7 @@ static MC6845_UPDATE_ROW( cga_gfx_4bppl_update_row )
* are the same size as the normal colour ones. * are the same size as the normal colour ones.
*/ */
#if 0
static const UINT8 yc_lut2[4] = { 0, 182, 71, 255 }; static const UINT8 yc_lut2[4] = { 0, 182, 71, 255 };
static const UINT8 yc_lut[16][8] = static const UINT8 yc_lut[16][8] =
@ -797,6 +798,7 @@ static const UINT8 yc_lut[16][8] =
{ 3, 3, 3, 3, 2, 2, 2, 2 }, /* yellow */ { 3, 3, 3, 3, 2, 2, 2, 2 }, /* yellow */
{ 3, 3, 3, 3, 3, 3, 3, 3 }, /* white */ { 3, 3, 3, 3, 3, 3, 3, 3 }, /* white */
}; };
#endif
static MC6845_UPDATE_ROW( cga_gfx_4bpph_update_row ) static MC6845_UPDATE_ROW( cga_gfx_4bpph_update_row )
{ {

2
src/lib/softfloat/fyl2x.c
View File

@ -75,6 +75,7 @@ INLINE flag extractFloatx80Sign( floatx80 a )
} }
#if 0
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
| Takes extended double-precision floating-point NaN `a' and returns the | Takes extended double-precision floating-point NaN `a' and returns the
| appropriate NaN result. If `a' is a signaling NaN, the invalid exception | appropriate NaN result. If `a' is a signaling NaN, the invalid exception
@ -90,6 +91,7 @@ INLINE floatx80 propagateFloatx80NaNOneArg(floatx80 a)
return a; return a;
} }
#endif
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
| Normalizes the subnormal extended double-precision floating-point value | Normalizes the subnormal extended double-precision floating-point value

2
src/mame/video/ppu2c0x.c
View File

@ -440,6 +440,7 @@ void ppu2c0x_device::init_palette_rgb( running_machine &machine, int first_entry
/* color tables are modified at run-time, and are initialized on 'ppu2c0x_reset' */ /* color tables are modified at run-time, and are initialized on 'ppu2c0x_reset' */
} }
#if 0
/* the charlayout we use for the chargen */ /* the charlayout we use for the chargen */
static const gfx_layout ppu_charlayout = static const gfx_layout ppu_charlayout =
{ {
@ -451,6 +452,7 @@ static const gfx_layout ppu_charlayout =
{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 }, { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
16*8 /* every char takes 16 consecutive bytes */ 16*8 /* every char takes 16 consecutive bytes */
}; };
#endif
/************************************* /*************************************
* *

2
src/mess/drivers/bullet.c
View File

@ -892,6 +892,7 @@ WRITE8_MEMBER( bulletf_state::dma_mreq_w )
m_ram->pointer()[(DMB6 << 16) | offset] = data; m_ram->pointer()[(DMB6 << 16) | offset] = data;
} }
#if 0
static Z80DMA_INTERFACE( bulletf_dma_intf ) static Z80DMA_INTERFACE( bulletf_dma_intf )
{ {
DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_HALT), DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_HALT),
@ -902,6 +903,7 @@ static Z80DMA_INTERFACE( bulletf_dma_intf )
DEVCB_DRIVER_MEMBER(bullet_state, io_read_byte), DEVCB_DRIVER_MEMBER(bullet_state, io_read_byte),
DEVCB_DRIVER_MEMBER(bullet_state, io_write_byte) DEVCB_DRIVER_MEMBER(bullet_state, io_write_byte)
}; };
#endif
//------------------------------------------------- //-------------------------------------------------

2
src/mess/drivers/ec184x.c
View File

@ -138,6 +138,7 @@ WRITE8_MEMBER(ec184x_state::memboard_w)
m_memory.enable[offset] = data; m_memory.enable[offset] = data;
} }
#if 0
const struct pit8253_interface ec1841_pit8253_config = const struct pit8253_interface ec1841_pit8253_config =
{ {
{ {
@ -156,6 +157,7 @@ const struct pit8253_interface ec1841_pit8253_config =
} }
} }
}; };
#endif
DRIVER_INIT_MEMBER( ec184x_state, ec184x ) DRIVER_INIT_MEMBER( ec184x_state, ec184x )

2
src/mess/drivers/jupiter.c
View File

@ -182,6 +182,7 @@ UINT32 jupiter3_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap
// wd17xx_interface fdc_intf // wd17xx_interface fdc_intf
//------------------------------------------------- //-------------------------------------------------
#if 0
static const floppy_interface jupiter_floppy_interface = static const floppy_interface jupiter_floppy_interface =
{ {
DEVCB_NULL, DEVCB_NULL,
@ -194,6 +195,7 @@ static const floppy_interface jupiter_floppy_interface =
NULL, NULL,
NULL NULL
}; };
#endif
static const wd17xx_interface fdc_intf = static const wd17xx_interface fdc_intf =
{ {

2
src/mess/drivers/lc80.c
View File

@ -284,6 +284,7 @@ static Z80PIO_INTERFACE( pio2_intf )
DEVCB_NULL /* portB ready active callback */ DEVCB_NULL /* portB ready active callback */
}; };
#if 0
/* Z80 Daisy Chain */ /* Z80 Daisy Chain */
static const z80_daisy_config lc80_daisy_chain[] = static const z80_daisy_config lc80_daisy_chain[] =
@ -293,6 +294,7 @@ static const z80_daisy_config lc80_daisy_chain[] =
{ Z80PIO1_TAG }, { Z80PIO1_TAG },
{ NULL } { NULL }
}; };
#endif
/* Machine Initialization */ /* Machine Initialization */

2
src/mess/drivers/poly880.c
View File

@ -248,6 +248,7 @@ static Z80PIO_INTERFACE( pio2_intf )
DEVCB_NULL /* portB ready active callback */ DEVCB_NULL /* portB ready active callback */
}; };
#if 0
/* Z80 Daisy Chain */ /* Z80 Daisy Chain */
static const z80_daisy_config poly880_daisy_chain[] = static const z80_daisy_config poly880_daisy_chain[] =
@ -257,6 +258,7 @@ static const z80_daisy_config poly880_daisy_chain[] =
{ Z80CTC_TAG }, { Z80CTC_TAG },
{ NULL } { NULL }
}; };
#endif
/* Machine Initialization */ /* Machine Initialization */

2
src/mess/drivers/vtech1.c
View File

@ -1046,6 +1046,7 @@ ROM_START( laser110 )
ROM_CART_LOAD("cart", 0x4000, 0x27ff, ROM_NOMIRROR | ROM_OPTIONAL) ROM_CART_LOAD("cart", 0x4000, 0x27ff, ROM_NOMIRROR | ROM_OPTIONAL)
ROM_END ROM_END
#if 0
/* The VZ-200 sold in Germany and the Netherlands came with BASIC V1.1, which /* The VZ-200 sold in Germany and the Netherlands came with BASIC V1.1, which
is currently not dumped. */ is currently not dumped. */
ROM_START( vz200de ) ROM_START( vz200de )
@ -1054,6 +1055,7 @@ ROM_START( vz200de )
ROM_LOAD("vtechv11.u10", 0x2000, 0x2000, NO_DUMP) ROM_LOAD("vtechv11.u10", 0x2000, 0x2000, NO_DUMP)
ROM_CART_LOAD("cart", 0x4000, 0x27ff, ROM_NOMIRROR | ROM_OPTIONAL) ROM_CART_LOAD("cart", 0x4000, 0x27ff, ROM_NOMIRROR | ROM_OPTIONAL)
ROM_END ROM_END
#endif
#define rom_las110de rom_laser110 #define rom_las110de rom_laser110
#define rom_laser200 rom_laser110 #define rom_laser200 rom_laser110

2
src/osd/sdl/drawogl.c
View File

@ -274,6 +274,7 @@ struct line_aa_step
float weight; // weight contribution float weight; // weight contribution
}; };
#if 0
static const line_aa_step line_aa_1step[] = static const line_aa_step line_aa_1step[] =
{ {
{ 0.00f, 0.00f, 1.00f }, { 0.00f, 0.00f, 1.00f },
@ -288,6 +289,7 @@ static const line_aa_step line_aa_4step[] =
{ 0.00f, 0.25f, 0.25f }, { 0.00f, 0.25f, 0.25f },
{ 0 } { 0 }
}; };
#endif
//============================================================ //============================================================
// INLINES // INLINES