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hp9845: synchronizer in 9895 drive optimized a bit

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This commit is contained in:
fulivi 2017-01-27 11:12:40 +01:00
parent cc3e8fd81c
commit 3168d16f67
2 changed files with 32 additions and 44 deletions
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75
src/devices/bus/ieee488/hp9895.cpp
View File

@ -19,7 +19,6 @@
* floppy_image_device sometimes reports the wrong state for ready & * floppy_image_device sometimes reports the wrong state for ready &
wpt signals wpt signals
* IBM mode hasn't been tested yet * IBM mode hasn't been tested yet
* Synchronizer/AM detector could be optimized
*********************************************************************/ *********************************************************************/
@ -94,8 +93,6 @@ enum {
#define TIMEOUT_MSEC 450 // Timeout duration (ms) #define TIMEOUT_MSEC 450 // Timeout duration (ms)
#define HPMODE_BIT_FREQ 500000 // HP-mode bit frequency (Hz) #define HPMODE_BIT_FREQ 500000 // HP-mode bit frequency (Hz)
#define IBMMODE_BIT_FREQ 250000 // IBM-mode bit frequency (Hz) #define IBMMODE_BIT_FREQ 250000 // IBM-mode bit frequency (Hz)
#define HPMODE_SYNC_MAX 2400 // Maximum distance of transitions to synchronize in HP mode (nsec)
#define IBMMODE_SYNC_MIN 3400 // Minimum distance of transitions to synchronize in IBM mode (nsec)
#define MIN_SYNC_BITS 29 // Number of bits to synchronize #define MIN_SYNC_BITS 29 // Number of bits to synchronize
@ -164,7 +161,6 @@ void hp9895_device::device_start()
save_item(NAME(m_lckup)); save_item(NAME(m_lckup));
save_item(NAME(m_amdt)); save_item(NAME(m_amdt));
save_item(NAME(m_sync_cnt)); save_item(NAME(m_sync_cnt));
save_item(NAME(m_prev_transition));
save_item(NAME(m_hiden)); save_item(NAME(m_hiden));
save_item(NAME(m_mgnena)); save_item(NAME(m_mgnena));
@ -301,46 +297,40 @@ void hp9895_device::device_timer(emu_timer &timer, device_timer_id id, int param
attotime edge; attotime edge;
attotime tm; attotime tm;
get_next_transition(m_pll.ctime, edge); get_next_transition(m_pll.ctime, edge);
bool half_bit = m_pll.feed_read_data(tm , edge , attotime::never); bool half_bit0 = m_pll.feed_read_data(tm , edge , attotime::never);
if (half_bit) { get_next_transition(m_pll.ctime, edge);
if (!m_prev_transition.is_never()) { bool half_bit1 = m_pll.feed_read_data(tm , edge , attotime::never);
attotime delta{ edge - m_prev_transition }; if (half_bit0 == half_bit1) {
LOG_0(("Time=%.7f, Prev @ %.7f, Edge @ %.7f, Delta=%.7f\n" , machine().time().as_double() , m_prev_transition.as_double() , edge.as_double() , delta.as_double())); // If half bits are equal, no synch
if ((m_hiden && delta > attotime::from_nsec(HPMODE_SYNC_MAX)) || LOG_0(("Reset sync_cnt\n"));
(!m_hiden && delta < attotime::from_nsec(IBMMODE_SYNC_MIN))) { m_sync_cnt = 0;
LOG_0(("Reset sync_cnt\n")); } else if (++m_sync_cnt >= MIN_SYNC_BITS) {
m_sync_cnt = 0; // Synchronized, now wait for AM
} else if (++m_sync_cnt >= MIN_SYNC_BITS) { LOG_0(("Synchronized @ %.6f\n" , machine().time().as_double()));
// Synchronized, now wait for AM m_lckup = false;
LOG_0(("Synchronized @ %.6f\n" , machine().time().as_double())); if (BIT(m_cntl_reg , REG_CNTL_WRITON_BIT)) {
m_lckup = false; // When loopback is active, leave AM detection to byte timer as
if (BIT(m_cntl_reg , REG_CNTL_WRITON_BIT)) { // byte boundary is already synchronized
// When loopback is active, leave AM detection to byte timer as timer.reset();
// byte boundary is already synchronized return;
timer.reset(); } else {
return; // Align with bit cell
} else { // Synchronization bits in HP mode: 32x 1s -> C/D bits = 01010101...
// half_bit is 0 in the clock part of bit cell when in HP mode, // Synchronization bits in IBM mode: 32x 0s -> C/D bits = 10101010...
// whereas it's 1 in IBM mode if (m_hiden != half_bit1) {
// Synchronization bits in HP mode: 32x 1s -> C/D bits = 01010101... // Discard 1/2 bit cell if synchronization achieved in the clock part
// Synchronization bits in IBM mode: 32x 0s -> C/D bits = 10101010... get_next_transition(m_pll.ctime, edge);
if (!m_hiden) { m_pll.feed_read_data(tm , edge , attotime::never);
// Discard 1/2 bit cell if synchronization achieved in the clock part }
get_next_transition(m_pll.ctime, edge); // Load CSR & DSR as they are after synchronization bits
m_pll.feed_read_data(tm , edge , attotime::never); if (m_hiden) {
} m_clock_sr = 0;
// Load CSR & DSR as they are after synchronization bits m_data_sr = ~0;
if (m_hiden) { } else {
m_clock_sr = 0; m_clock_sr = ~0;
m_data_sr = ~0; m_data_sr = 0;
} else {
m_clock_sr = ~0;
m_data_sr = 0;
}
}
} }
} }
m_prev_transition = edge;
} }
} else { } else {
// Looking for AM // Looking for AM
@ -567,7 +557,6 @@ WRITE8_MEMBER(hp9895_device::cntl_w)
LOG_0(("Start reading..\n")); LOG_0(("Start reading..\n"));
m_pll.read_reset(machine().time()); m_pll.read_reset(machine().time());
m_sync_cnt = 0; m_sync_cnt = 0;
m_prev_transition = attotime::never;
m_half_bit_timer->adjust(get_half_bit_cell_period()); m_half_bit_timer->adjust(get_half_bit_cell_period());
} else if (old_readon && !new_readon) { } else if (old_readon && !new_readon) {
// Reading disabled // Reading disabled

1
src/devices/bus/ieee488/hp9895.h
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@ -107,7 +107,6 @@ private:
bool m_lckup; bool m_lckup;
bool m_amdt; bool m_amdt;
uint8_t m_sync_cnt; // U28 & U73 uint8_t m_sync_cnt; // U28 & U73
attotime m_prev_transition;
bool m_hiden; bool m_hiden;
bool m_mgnena; bool m_mgnena;
#if 0 #if 0