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h8: H8/3003 support [R. Belmont]
This commit is contained in:
arbee
parent
c1b84b9e30
commit
31a32f451d
@ -599,6 +599,8 @@ if (CPUS["H8"]~=null) then
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MAME_DIR .. "src/devices/cpu/h8/h83337.h",
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MAME_DIR .. "src/devices/cpu/h8/h83002.cpp",
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MAME_DIR .. "src/devices/cpu/h8/h83002.h",
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MAME_DIR .. "src/devices/cpu/h8/h83003.cpp",
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MAME_DIR .. "src/devices/cpu/h8/h83003.h",
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MAME_DIR .. "src/devices/cpu/h8/h83006.cpp",
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MAME_DIR .. "src/devices/cpu/h8/h83006.h",
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MAME_DIR .. "src/devices/cpu/h8/h83008.cpp",
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288
src/devices/cpu/h8/h83003.cpp
Normal file
288
src/devices/cpu/h8/h83003.cpp
Normal file
@ -0,0 +1,288 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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#include "emu.h"
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#include "h83003.h"
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DEFINE_DEVICE_TYPE(H83003, h83003_device, "h83003", "Hitachi H8/3003")
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h83003_device::h83003_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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h8h_device(mconfig, H83003, tag, owner, clock, address_map_constructor(FUNC(h83003_device::map), this)),
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intc(*this, "intc"),
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adc(*this, "adc"),
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dma(*this, "dma"),
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dma0(*this, "dma:0"),
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dma1(*this, "dma:1"),
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dma2(*this, "dma:2"),
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port4(*this, "port4"),
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port6(*this, "port6"),
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port7(*this, "port7"),
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port8(*this, "port8"),
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port9(*this, "port9"),
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porta(*this, "porta"),
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portb(*this, "portb"),
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timer16(*this, "timer16"),
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timer16_0(*this, "timer16:0"),
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timer16_1(*this, "timer16:1"),
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timer16_2(*this, "timer16:2"),
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timer16_3(*this, "timer16:3"),
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timer16_4(*this, "timer16:4"),
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sci0(*this, "sci0"),
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sci1(*this, "sci1"),
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watchdog(*this, "watchdog"),
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tend0_cb(*this),
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tend1_cb(*this)
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{
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syscr = 0;
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}
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void h83003_device::map(address_map &map)
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{
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map(0xfffd10, 0xffff0f).ram();
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// DMA: only full address mode supported
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map(0xffff20, 0xffff21).rw("dma:0", FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
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map(0xffff22, 0xffff23).rw("dma:0", FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
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map(0xffff24, 0xffff25).rw("dma:0", FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
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map(0xffff27, 0xffff27).rw("dma:0", FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
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map(0xffff28, 0xffff29).rw("dma:0", FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
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map(0xffff2a, 0xffff2b).rw("dma:0", FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
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map(0xffff2c, 0xffff2d).rw("dma:0", FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
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map(0xffff2f, 0xffff2f).rw("dma:0", FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
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map(0xffff30, 0xffff31).rw("dma:1", FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
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map(0xffff32, 0xffff33).rw("dma:1", FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
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map(0xffff34, 0xffff35).rw("dma:1", FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
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map(0xffff37, 0xffff37).rw("dma:1", FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
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map(0xffff38, 0xffff39).rw("dma:1", FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
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map(0xffff3a, 0xffff3b).rw("dma:1", FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
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map(0xffff3c, 0xffff3d).rw("dma:1", FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
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map(0xffff3f, 0xffff3f).rw("dma:1", FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
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map(0xffff40, 0xffff41).rw("dma:2", FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
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map(0xffff42, 0xffff43).rw("dma:2", FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
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map(0xffff44, 0xffff45).rw("dma:2", FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
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map(0xffff47, 0xffff47).rw("dma:2", FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
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map(0xffff48, 0xffff49).rw("dma:2", FUNC(h8_dma_channel_device::marbh_r), FUNC(h8_dma_channel_device::marbh_w));
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map(0xffff4a, 0xffff4b).rw("dma:2", FUNC(h8_dma_channel_device::marbl_r), FUNC(h8_dma_channel_device::marbl_w));
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map(0xffff4c, 0xffff4d).rw("dma:2", FUNC(h8_dma_channel_device::etcrb_r), FUNC(h8_dma_channel_device::etcrb_w));
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map(0xffff4f, 0xffff4f).rw("dma:2", FUNC(h8_dma_channel_device::dtcrb_r), FUNC(h8_dma_channel_device::dtcrb_w));
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map(0xffff50, 0xffff51).rw("dma:3", FUNC(h8_dma_channel_device::marah_r), FUNC(h8_dma_channel_device::marah_w));
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map(0xffff52, 0xffff53).rw("dma:3", FUNC(h8_dma_channel_device::maral_r), FUNC(h8_dma_channel_device::maral_w));
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map(0xffff54, 0xffff55).rw("dma:3", FUNC(h8_dma_channel_device::etcra_r), FUNC(h8_dma_channel_device::etcra_w));
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map(0xffff57, 0xffff57).rw("dma:3", FUNC(h8_dma_channel_device::dtcra_r), FUNC(h8_dma_channel_device::dtcra_w));
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map(0xffff60, 0xffff60).rw("timer16", FUNC(h8_timer16_device::tstr_r), FUNC(h8_timer16_device::tstr_w));
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map(0xffff61, 0xffff61).rw("timer16", FUNC(h8_timer16_device::tsyr_r), FUNC(h8_timer16_device::tsyr_w));
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map(0xffff62, 0xffff62).rw("timer16", FUNC(h8_timer16_device::tmdr_r), FUNC(h8_timer16_device::tmdr_w));
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map(0xffff63, 0xffff63).rw("timer16", FUNC(h8_timer16_device::tfcr_r), FUNC(h8_timer16_device::tfcr_w));
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map(0xffff64, 0xffff64).rw("timer16:0", FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w));
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map(0xffff65, 0xffff65).rw("timer16:0", FUNC(h8_timer16_channel_device::tior_r), FUNC(h8_timer16_channel_device::tior_w));
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map(0xffff66, 0xffff66).rw("timer16:0", FUNC(h8_timer16_channel_device::tier_r), FUNC(h8_timer16_channel_device::tier_w));
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map(0xffff67, 0xffff67).rw("timer16:0", FUNC(h8_timer16_channel_device::tsr_r), FUNC(h8_timer16_channel_device::tsr_w));
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map(0xffff68, 0xffff69).rw("timer16:0", FUNC(h8_timer16_channel_device::tcnt_r), FUNC(h8_timer16_channel_device::tcnt_w));
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map(0xffff6a, 0xffff6d).rw("timer16:0", FUNC(h8_timer16_channel_device::tgr_r), FUNC(h8_timer16_channel_device::tgr_w));
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map(0xffff6e, 0xffff6e).rw("timer16:1", FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w));
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map(0xffff6f, 0xffff6f).rw("timer16:1", FUNC(h8_timer16_channel_device::tior_r), FUNC(h8_timer16_channel_device::tior_w));
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map(0xffff70, 0xffff70).rw("timer16:1", FUNC(h8_timer16_channel_device::tier_r), FUNC(h8_timer16_channel_device::tier_w));
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map(0xffff71, 0xffff71).rw("timer16:1", FUNC(h8_timer16_channel_device::tsr_r), FUNC(h8_timer16_channel_device::tsr_w));
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map(0xffff72, 0xffff73).rw("timer16:1", FUNC(h8_timer16_channel_device::tcnt_r), FUNC(h8_timer16_channel_device::tcnt_w));
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map(0xffff74, 0xffff77).rw("timer16:1", FUNC(h8_timer16_channel_device::tgr_r), FUNC(h8_timer16_channel_device::tgr_w));
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map(0xffff78, 0xffff78).rw("timer16:2", FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w));
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map(0xffff79, 0xffff79).rw("timer16:2", FUNC(h8_timer16_channel_device::tior_r), FUNC(h8_timer16_channel_device::tior_w));
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map(0xffff7a, 0xffff7a).rw("timer16:2", FUNC(h8_timer16_channel_device::tier_r), FUNC(h8_timer16_channel_device::tier_w));
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map(0xffff7b, 0xffff7b).rw("timer16:2", FUNC(h8_timer16_channel_device::tsr_r), FUNC(h8_timer16_channel_device::tsr_w));
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map(0xffff7c, 0xffff7d).rw("timer16:2", FUNC(h8_timer16_channel_device::tcnt_r), FUNC(h8_timer16_channel_device::tcnt_w));
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map(0xffff7e, 0xffff81).rw("timer16:2", FUNC(h8_timer16_channel_device::tgr_r), FUNC(h8_timer16_channel_device::tgr_w));
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map(0xffff82, 0xffff82).rw("timer16:3", FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w));
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map(0xffff83, 0xffff83).rw("timer16:3", FUNC(h8_timer16_channel_device::tior_r), FUNC(h8_timer16_channel_device::tior_w));
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map(0xffff84, 0xffff84).rw("timer16:3", FUNC(h8_timer16_channel_device::tier_r), FUNC(h8_timer16_channel_device::tier_w));
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map(0xffff85, 0xffff85).rw("timer16:3", FUNC(h8_timer16_channel_device::tsr_r), FUNC(h8_timer16_channel_device::tsr_w));
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map(0xffff86, 0xffff87).rw("timer16:3", FUNC(h8_timer16_channel_device::tcnt_r), FUNC(h8_timer16_channel_device::tcnt_w));
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map(0xffff88, 0xffff8b).rw("timer16:3", FUNC(h8_timer16_channel_device::tgr_r), FUNC(h8_timer16_channel_device::tgr_w));
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map(0xffff8c, 0xffff8f).rw("timer16:3", FUNC(h8_timer16_channel_device::tbr_r), FUNC(h8_timer16_channel_device::tbr_w));
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map(0xffff90, 0xffff90).rw("timer16", FUNC(h8_timer16_device::toer_r), FUNC(h8_timer16_device::toer_w));
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map(0xffff91, 0xffff91).rw("timer16", FUNC(h8_timer16_device::tocr_r), FUNC(h8_timer16_device::tocr_w));
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map(0xffff92, 0xffff92).rw("timer16:4", FUNC(h8_timer16_channel_device::tcr_r), FUNC(h8_timer16_channel_device::tcr_w));
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map(0xffff93, 0xffff93).rw("timer16:4", FUNC(h8_timer16_channel_device::tior_r), FUNC(h8_timer16_channel_device::tior_w));
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map(0xffff94, 0xffff94).rw("timer16:4", FUNC(h8_timer16_channel_device::tier_r), FUNC(h8_timer16_channel_device::tier_w));
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map(0xffff95, 0xffff95).rw("timer16:4", FUNC(h8_timer16_channel_device::tsr_r), FUNC(h8_timer16_channel_device::tsr_w));
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map(0xffff96, 0xffff97).rw("timer16:4", FUNC(h8_timer16_channel_device::tcnt_r), FUNC(h8_timer16_channel_device::tcnt_w));
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map(0xffff98, 0xffff9b).rw("timer16:4", FUNC(h8_timer16_channel_device::tgr_r), FUNC(h8_timer16_channel_device::tgr_w));
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map(0xffff9c, 0xffff9f).rw("timer16:4", FUNC(h8_timer16_channel_device::tbr_r), FUNC(h8_timer16_channel_device::tbr_w));
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map(0xffffa8, 0xffffa9).rw("watchdog", FUNC(h8_watchdog_device::wd_r), FUNC(h8_watchdog_device::wd_w));
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map(0xffffaa, 0xffffab).rw("watchdog", FUNC(h8_watchdog_device::rst_r), FUNC(h8_watchdog_device::rst_w));
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map(0xffffad, 0xffffad).rw(FUNC(h83003_device::rtmcsr_r), FUNC(h83003_device::rtmcsr_w));
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map(0xffffb0, 0xffffb0).rw("sci0", FUNC(h8_sci_device::smr_r), FUNC(h8_sci_device::smr_w));
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map(0xffffb1, 0xffffb1).rw("sci0", FUNC(h8_sci_device::brr_r), FUNC(h8_sci_device::brr_w));
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map(0xffffb2, 0xffffb2).rw("sci0", FUNC(h8_sci_device::scr_r), FUNC(h8_sci_device::scr_w));
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map(0xffffb3, 0xffffb3).rw("sci0", FUNC(h8_sci_device::tdr_r), FUNC(h8_sci_device::tdr_w));
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map(0xffffb4, 0xffffb4).rw("sci0", FUNC(h8_sci_device::ssr_r), FUNC(h8_sci_device::ssr_w));
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map(0xffffb5, 0xffffb5).r("sci0", FUNC(h8_sci_device::rdr_r));
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map(0xffffb8, 0xffffb8).rw("sci1", FUNC(h8_sci_device::smr_r), FUNC(h8_sci_device::smr_w));
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map(0xffffb9, 0xffffb9).rw("sci1", FUNC(h8_sci_device::brr_r), FUNC(h8_sci_device::brr_w));
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map(0xffffba, 0xffffba).rw("sci1", FUNC(h8_sci_device::scr_r), FUNC(h8_sci_device::scr_w));
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map(0xffffbb, 0xffffbb).rw("sci1", FUNC(h8_sci_device::tdr_r), FUNC(h8_sci_device::tdr_w));
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map(0xffffbc, 0xffffbc).rw("sci1", FUNC(h8_sci_device::ssr_r), FUNC(h8_sci_device::ssr_w));
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map(0xffffbd, 0xffffbd).r("sci1", FUNC(h8_sci_device::rdr_r));
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map(0xffffc5, 0xffffc5).w("port4", FUNC(h8_port_device::ddr_w));
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map(0xffffc7, 0xffffc7).rw("port4", FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
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map(0xffffc9, 0xffffc9).w("port6", FUNC(h8_port_device::ddr_w));
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map(0xffffcb, 0xffffcb).rw("port6", FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
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map(0xffffcd, 0xffffcd).w("port8", FUNC(h8_port_device::ddr_w));
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map(0xffffce, 0xffffce).r("port7", FUNC(h8_port_device::port_r));
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map(0xffffcf, 0xffffcf).rw("port8", FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
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map(0xffffd0, 0xffffd0).w("port9", FUNC(h8_port_device::ddr_w));
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map(0xffffd1, 0xffffd1).w("porta", FUNC(h8_port_device::ddr_w));
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map(0xffffd2, 0xffffd2).rw("port9", FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
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map(0xffffd3, 0xffffd3).rw("porta", FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
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map(0xffffd4, 0xffffd4).w("portb", FUNC(h8_port_device::ddr_w));
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map(0xffffd6, 0xffffd6).rw("portb", FUNC(h8_port_device::port_r), FUNC(h8_port_device::dr_w));
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map(0xffffda, 0xffffda).rw("port4", FUNC(h8_port_device::pcr_r), FUNC(h8_port_device::pcr_w));
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map(0xffffe0, 0xffffe7).r("adc", FUNC(h8_adc_device::addr8_r));
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map(0xffffe8, 0xffffe8).rw("adc", FUNC(h8_adc_device::adcsr_r), FUNC(h8_adc_device::adcsr_w));
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map(0xffffe9, 0xffffe9).rw("adc", FUNC(h8_adc_device::adcr_r), FUNC(h8_adc_device::adcr_w));
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map(0xfffff2, 0xfffff2).rw(FUNC(h83003_device::syscr_r), FUNC(h83003_device::syscr_w));
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map(0xfffff4, 0xfffff4).rw("intc", FUNC(h8h_intc_device::iscr_r), FUNC(h8h_intc_device::iscr_w));
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map(0xfffff5, 0xfffff5).rw("intc", FUNC(h8h_intc_device::ier_r), FUNC(h8h_intc_device::ier_w));
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map(0xfffff6, 0xfffff6).rw("intc", FUNC(h8h_intc_device::isr_r), FUNC(h8h_intc_device::isr_w));
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map(0xfffff8, 0xfffff9).rw("intc", FUNC(h8h_intc_device::icr_r), FUNC(h8h_intc_device::icr_w));
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}
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MACHINE_CONFIG_START(h83003_device::device_add_mconfig)
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MCFG_H8H_INTC_ADD("intc")
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MCFG_H8_ADC_3337_ADD("adc", "intc", 60)
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MCFG_H8_DMA_ADD("dma")
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// (H8/2002.pdf) Table 8-11 DMAC Activation Sources
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MCFG_H8_DMA_CHANNEL_ADD("dma:0", "intc", 44, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
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MCFG_H8_DMA_CHANNEL_ADD("dma:1", "intc", 46, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
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MCFG_H8_DMA_CHANNEL_ADD("dma:2", "intc", 48, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
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MCFG_H8_DMA_CHANNEL_ADD("dma:3", "intc", 50, h8_dma_channel_device::NONE, 24, h8_dma_channel_device::DREQ_EDGE, h8_dma_channel_device::DREQ_LEVEL, 28, 32, 36, 54, 53, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE, h8_dma_channel_device::NONE)
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MCFG_H8_PORT_ADD("port4", h8_device::PORT_4, 0x00, 0x00)
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MCFG_H8_PORT_ADD("port6", h8_device::PORT_6, 0x80, 0x80)
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MCFG_H8_PORT_ADD("port7", h8_device::PORT_7, 0x00, 0x00)
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MCFG_H8_PORT_ADD("port8", h8_device::PORT_8, 0xf0, 0xe0)
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MCFG_H8_PORT_ADD("port9", h8_device::PORT_9, 0x00, 0xc0)
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MCFG_H8_PORT_ADD("porta", h8_device::PORT_A, 0x00, 0x00)
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MCFG_H8_PORT_ADD("portb", h8_device::PORT_B, 0x00, 0x00)
|
||||
MCFG_H8_TIMER16_ADD("timer16", 5, 0xe0)
|
||||
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:0", 2, 2, "intc", 24)
|
||||
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:1", 2, 2, "intc", 28)
|
||||
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:2", 2, 2, "intc", 32)
|
||||
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:3", 2, 2, "intc", 36)
|
||||
MCFG_H8H_TIMER16_CHANNEL_ADD("timer16:4", 2, 2, "intc", 40)
|
||||
MCFG_H8_SCI_ADD("sci0", "intc", 52, 53, 54, 55)
|
||||
MCFG_H8_SCI_ADD("sci1", "intc", 56, 57, 58, 59)
|
||||
MCFG_H8_WATCHDOG_ADD("watchdog", "intc", 20, h8_watchdog_device::H)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
void h83003_device::execute_set_input(int inputnum, int state)
|
||||
{
|
||||
if(inputnum == H8_INPUT_LINE_TEND0 && !tend0_cb.isnull())
|
||||
tend0_cb(state);
|
||||
else if(inputnum == H8_INPUT_LINE_TEND1 && !tend1_cb.isnull())
|
||||
tend1_cb(state);
|
||||
else if(inputnum >= H8_INPUT_LINE_DREQ0 && inputnum <= H8_INPUT_LINE_DREQ3)
|
||||
dma->set_input(inputnum, state);
|
||||
else
|
||||
intc->set_input(inputnum, state);
|
||||
}
|
||||
|
||||
int h83003_device::trapa_setup()
|
||||
{
|
||||
if(syscr & 0x08)
|
||||
CCR |= F_I;
|
||||
else
|
||||
CCR |= F_I|F_UI;
|
||||
return 8;
|
||||
}
|
||||
|
||||
void h83003_device::irq_setup()
|
||||
{
|
||||
if(syscr & 0x08)
|
||||
CCR |= F_I;
|
||||
else
|
||||
CCR |= F_I|F_UI;
|
||||
}
|
||||
|
||||
void h83003_device::update_irq_filter()
|
||||
{
|
||||
switch(syscr & 0x08) {
|
||||
case 0x00:
|
||||
if((CCR & (F_I|F_UI)) == (F_I|F_UI))
|
||||
intc->set_filter(2, -1);
|
||||
else if(CCR & F_I)
|
||||
intc->set_filter(1, -1);
|
||||
else
|
||||
intc->set_filter(0, -1);
|
||||
break;
|
||||
case 0x08:
|
||||
if(CCR & F_I)
|
||||
intc->set_filter(2, -1);
|
||||
else
|
||||
intc->set_filter(0, -1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void h83003_device::interrupt_taken()
|
||||
{
|
||||
standard_irq_callback(intc->interrupt_taken(taken_irq_vector));
|
||||
}
|
||||
|
||||
void h83003_device::internal_update(uint64_t current_time)
|
||||
{
|
||||
uint64_t event_time = 0;
|
||||
|
||||
add_event(event_time, adc->internal_update(current_time));
|
||||
add_event(event_time, sci0->internal_update(current_time));
|
||||
add_event(event_time, sci1->internal_update(current_time));
|
||||
add_event(event_time, timer16_0->internal_update(current_time));
|
||||
add_event(event_time, timer16_1->internal_update(current_time));
|
||||
add_event(event_time, timer16_2->internal_update(current_time));
|
||||
add_event(event_time, timer16_3->internal_update(current_time));
|
||||
add_event(event_time, timer16_4->internal_update(current_time));
|
||||
add_event(event_time, watchdog->internal_update(current_time));
|
||||
|
||||
recompute_bcount(event_time);
|
||||
}
|
||||
|
||||
void h83003_device::device_start()
|
||||
{
|
||||
h8h_device::device_start();
|
||||
dma_device = dma;
|
||||
|
||||
tend0_cb.resolve();
|
||||
tend1_cb.resolve();
|
||||
}
|
||||
|
||||
void h83003_device::device_reset()
|
||||
{
|
||||
h8h_device::device_reset();
|
||||
syscr = 0x09;
|
||||
}
|
||||
|
||||
READ8_MEMBER(h83003_device::syscr_r)
|
||||
{
|
||||
return syscr;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(h83003_device::syscr_w)
|
||||
{
|
||||
syscr = data;
|
||||
update_irq_filter();
|
||||
logerror("syscr = %02x\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(h83003_device::rtmcsr_r)
|
||||
{
|
||||
// set bit 7 -- Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR values have matched.
|
||||
return rtmcsr | 0x80;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(h83003_device::rtmcsr_w)
|
||||
{
|
||||
rtmcsr = data;
|
||||
logerror("rtmcsr = %02x\n", data);
|
||||
}
|
||||
90
src/devices/cpu/h8/h83003.h
Normal file
90
src/devices/cpu/h8/h83003.h
Normal file
@ -0,0 +1,90 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Olivier Galibert
|
||||
/***************************************************************************
|
||||
|
||||
h83003.h
|
||||
|
||||
H8/3003
|
||||
|
||||
H8/300H-based mcus.
|
||||
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef MAME_CPU_H8_H83003_H
|
||||
#define MAME_CPU_H8_H83003_H
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "h8h.h"
|
||||
#include "h8_adc.h"
|
||||
#include "h8_dma.h"
|
||||
#include "h8_port.h"
|
||||
#include "h8_intc.h"
|
||||
#include "h8_timer16.h"
|
||||
#include "h8_sci.h"
|
||||
#include "h8_watchdog.h"
|
||||
|
||||
#define MCFG_H83003_TEND0_CALLBACK(_devcb) \
|
||||
downcast<h83003_device &>(*device).set_tend0_callback(DEVCB_##_devcb);
|
||||
#define MCFG_H83003_TEND1_CALLBACK(_devcb) \
|
||||
downcast<h83003_device &>(*device).set_tend1_callback(DEVCB_##_devcb);
|
||||
|
||||
class h83003_device : public h8h_device {
|
||||
public:
|
||||
h83003_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
template<class Object> devcb_base &set_tend0_callback(Object &&cb) { return tend0_cb.set_callback(std::forward<Object>(cb)); }
|
||||
template<class Object> devcb_base &set_tend1_callback(Object &&cb) { return tend1_cb.set_callback(std::forward<Object>(cb)); }
|
||||
|
||||
DECLARE_READ8_MEMBER(syscr_r);
|
||||
DECLARE_WRITE8_MEMBER(syscr_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(rtmcsr_r);
|
||||
DECLARE_WRITE8_MEMBER(rtmcsr_w);
|
||||
|
||||
protected:
|
||||
required_device<h8h_intc_device> intc;
|
||||
required_device<h8_adc_device> adc;
|
||||
optional_device<h8_dma_device> dma;
|
||||
optional_device<h8_dma_channel_device> dma0;
|
||||
optional_device<h8_dma_channel_device> dma1;
|
||||
optional_device<h8_dma_channel_device> dma2;
|
||||
required_device<h8_port_device> port4;
|
||||
required_device<h8_port_device> port6;
|
||||
required_device<h8_port_device> port7;
|
||||
required_device<h8_port_device> port8;
|
||||
required_device<h8_port_device> port9;
|
||||
required_device<h8_port_device> porta;
|
||||
required_device<h8_port_device> portb;
|
||||
required_device<h8_timer16_device> timer16;
|
||||
required_device<h8h_timer16_channel_device> timer16_0;
|
||||
required_device<h8h_timer16_channel_device> timer16_1;
|
||||
required_device<h8h_timer16_channel_device> timer16_2;
|
||||
required_device<h8h_timer16_channel_device> timer16_3;
|
||||
required_device<h8h_timer16_channel_device> timer16_4;
|
||||
required_device<h8_sci_device> sci0;
|
||||
required_device<h8_sci_device> sci1;
|
||||
required_device<h8_watchdog_device> watchdog;
|
||||
|
||||
uint8_t syscr;
|
||||
uint8_t rtmcsr;
|
||||
|
||||
devcb_write_line tend0_cb, tend1_cb;
|
||||
|
||||
virtual void update_irq_filter() override;
|
||||
virtual void interrupt_taken() override;
|
||||
virtual int trapa_setup() override;
|
||||
virtual void irq_setup() override;
|
||||
virtual void internal_update(uint64_t current_time) override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
void map(address_map &map);
|
||||
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
virtual void execute_set_input(int inputnum, int state) override;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(H83003, h83003_device)
|
||||
|
||||
#endif // MAME_CPU_H8_H83003_H
|
||||
Loading…
Reference in New Issue
Block a user