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https://github.com/holub/mame
synced 2025-05-22 13:48:55 +03:00
lohtb2: Improved mcu emulation
* The whole startup cycle now works. No more timeouts and erratic behavior. * lohtb2 will however not display the "Warning" screen due to a priority issue. With color/attribute of 0x80 in videoram at 0xd0000 and 0xd8000, videoram at 0xd80000 will be displayed. Some tilemap guru has to look into this.
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@ -91,7 +91,6 @@ other supported games as well.
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#include "cpu/nec/nec.h"
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#include "cpu/nec/nec.h"
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#include "cpu/i8051/i8051.h"
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#include "cpu/i8051/i8051.h"
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#define MASTER_CLOCK XTAL_32MHz
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#define MASTER_CLOCK XTAL_32MHz
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#define SOUND_CLOCK XTAL_3_579545MHz
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#define SOUND_CLOCK XTAL_3_579545MHz
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@ -115,7 +114,7 @@ static MACHINE_START( m72 )
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static TIMER_CALLBACK( synch_callback )
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static TIMER_CALLBACK( synch_callback )
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{
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{
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//cpu_boost_interleave(attotime_zero, ATTOTIME_IN_USEC(8000000));
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//cpu_boost_interleave(attotime_zero, ATTOTIME_IN_USEC(8000000));
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cpu_boost_interleave(ATTOTIME_IN_HZ(MASTER_CLOCK/4/12), ATTOTIME_IN_SEC(8));
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cpu_boost_interleave(ATTOTIME_IN_HZ(MASTER_CLOCK/4/12), ATTOTIME_IN_SEC(25));
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}
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}
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static MACHINE_RESET( m72 )
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static MACHINE_RESET( m72 )
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@ -195,11 +194,6 @@ static TIMER_CALLBACK( delayed_ram16_w )
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ram[offset] = val;
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ram[offset] = val;
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}
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}
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static TIMER_CALLBACK( mcu_irq0_clear )
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{
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cputag_set_input_line(machine, "mcu", 0, CLEAR_LINE);
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}
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static WRITE16_HANDLER( m72_main_mcu_sound_w )
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static WRITE16_HANDLER( m72_main_mcu_sound_w )
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{
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{
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@ -228,7 +222,8 @@ static WRITE16_HANDLER( m72_main_mcu_w)
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protection_ram[offset] = val;
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protection_ram[offset] = val;
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cputag_set_input_line(machine, "mcu", 0, ASSERT_LINE);
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cputag_set_input_line(machine, "mcu", 0, ASSERT_LINE);
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/* Line driven, most likely by write line */
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/* Line driven, most likely by write line */
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timer_set(ATTOTIME_IN_CYCLES(2, mame_find_cpu_index(machine, "mcu")), NULL, 0, mcu_irq0_clear);
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//timer_set(ATTOTIME_IN_CYCLES(2, mame_find_cpu_index(machine, "mcu")), NULL, 0, mcu_irq0_clear);
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//timer_set(ATTOTIME_IN_CYCLES(0, mame_find_cpu_index(machine, "mcu")), NULL, 0, mcu_irq0_raise);
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}
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}
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else
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else
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timer_call_after_resynch( protection_ram, (offset<<16) | val, delayed_ram16_w);
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timer_call_after_resynch( protection_ram, (offset<<16) | val, delayed_ram16_w);
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@ -247,6 +242,11 @@ static READ8_HANDLER(m72_mcu_data_r )
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{
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{
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UINT8 ret;
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UINT8 ret;
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if (offset == 0x0fff || offset == 0x0ffe)
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{
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cputag_set_input_line(machine, "mcu", 0, CLEAR_LINE);
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}
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if (offset&1) ret = (protection_ram[offset/2] & 0xff00)>>8;
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if (offset&1) ret = (protection_ram[offset/2] & 0xff00)>>8;
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else ret = (protection_ram[offset/2] & 0x00ff);
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else ret = (protection_ram[offset/2] & 0x00ff);
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@ -256,7 +256,7 @@ static READ8_HANDLER(m72_mcu_data_r )
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static INTERRUPT_GEN( m72_mcu_int )
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static INTERRUPT_GEN( m72_mcu_int )
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{
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{
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//mcu_snd_cmd_latch |= 0x11; /* 0x10 is special as well - FIXME */
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//mcu_snd_cmd_latch |= 0x11; /* 0x10 is special as well - FIXME */
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mcu_snd_cmd_latch = 0x10 | (mame_rand(machine) & 1); /* 0x10 is special as well - FIXME */
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mcu_snd_cmd_latch = 0x11;// | (mame_rand(machine) & 1); /* 0x10 is special as well - FIXME */
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cputag_set_input_line(machine, "mcu", 1, ASSERT_LINE);
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cputag_set_input_line(machine, "mcu", 1, ASSERT_LINE);
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}
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}
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@ -335,6 +335,28 @@ INLINE DRIVER_INIT( loht_mcu )
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/* sound cpu */
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/* sound cpu */
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memory_install_write8_handler(machine, sndnum, ADDRESS_SPACE_IO, 0x82, 0x82, 0xff, 0, m72_snd_cpu_sample_w);
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memory_install_write8_handler(machine, sndnum, ADDRESS_SPACE_IO, 0x82, 0x82, 0xff, 0, m72_snd_cpu_sample_w);
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memory_install_read8_handler (machine, sndnum, ADDRESS_SPACE_IO, 0x84, 0x84, 0xff, 0, m72_snd_cpu_sample_r);
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memory_install_read8_handler (machine, sndnum, ADDRESS_SPACE_IO, 0x84, 0x84, 0xff, 0, m72_snd_cpu_sample_r);
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#if 0
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/* running the mcu at twice the speed, the following
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* timeouts have to be modified.
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* At normal speed, the timing heavily depends on opcode
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* prefetching on the V30.
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*/
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{
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UINT8 *rom=memory_region(machine, "mcu");
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rom[0x12d+5] += 1; printf(" 5: %d\n", rom[0x12d+5]);
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rom[0x12d+8] += 5; printf(" 8: %d\n", rom[0x12d+8]);
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rom[0x12d+11] += 7; printf("11: %d\n", rom[0x12d+11]);
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rom[0x12d+14] += 9; printf("14: %d\n", rom[0x12d+14]);
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rom[0x12d+17] += 1; printf("17: %d\n", rom[0x12d+17]);
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rom[0x12d+20] += 10; printf("20: %d\n", rom[0x12d+20]);
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rom[0x12d+23] += 3; printf("23: %d\n", rom[0x12d+23]);
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rom[0x12d+26] += 2; printf("26: %d\n", rom[0x12d+26]);
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rom[0x12d+29] += 2; printf("29: %d\n", rom[0x12d+29]);
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rom[0x12d+32] += 16; printf("32: %d\n", rom[0x12d+32]);
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}
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#endif
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}
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}
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@ -1035,29 +1057,6 @@ static ADDRESS_MAP_START( poundfor_sound_portmap, ADDRESS_SPACE_IO, 8 )
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AM_RANGE(0x42, 0x42) AM_WRITE(m72_sound_irq_ack_w)
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AM_RANGE(0x42, 0x42) AM_WRITE(m72_sound_irq_ack_w)
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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#if 0
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/* TODO: internal - should be removed */
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static ADDRESS_MAP_START( mcu_map, ADDRESS_SPACE_PROGRAM, 8 )
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//ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x0000, 0x0fff) AM_ROM
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ADDRESS_MAP_END
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#endif
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#if 0
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static ADDRESS_MAP_START( mcu_data_map, ADDRESS_SPACE_DATA, 8 )
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//ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x0000, 0x0000) AM_READWRITE(m72_mcu_sample_r, m72_mcu_low_w)
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AM_RANGE(0x0001, 0x0001) AM_WRITE(m72_mcu_high_w)
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AM_RANGE(0x0002, 0x0002) AM_READWRITE(m72_mcu_snd_r, m72_mcu_ack_w)
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/* shared at b0000 - b0fff on the main cpu */
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AM_RANGE(0xc000, 0xcfff) AM_RAM AM_READWRITE(m72_mcu_data_r,m72_mcu_data_w )
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( mcu_io_map, ADDRESS_SPACE_IO, 8 )
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//ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x0000, 0x0003) AM_READWRITE(m72_mcu_port_r, m72_mcu_port_w)
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ADDRESS_MAP_END
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#else
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static ADDRESS_MAP_START( mcu_io_map, ADDRESS_SPACE_IO, 8 )
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static ADDRESS_MAP_START( mcu_io_map, ADDRESS_SPACE_IO, 8 )
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/* External access */
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/* External access */
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AM_RANGE(0x0000, 0x0000) AM_READWRITE(m72_mcu_sample_r, m72_mcu_low_w)
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AM_RANGE(0x0000, 0x0000) AM_READWRITE(m72_mcu_sample_r, m72_mcu_low_w)
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@ -1070,8 +1069,6 @@ static ADDRESS_MAP_START( mcu_io_map, ADDRESS_SPACE_IO, 8 )
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AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(m72_mcu_port_r, m72_mcu_port_w)
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AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(m72_mcu_port_r, m72_mcu_port_w)
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ADDRESS_MAP_END
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ADDRESS_MAP_END
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#endif
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#define COIN_MODE_1 \
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#define COIN_MODE_1 \
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PORT_DIPNAME( 0x00f0, 0x00f0, DEF_STR( Coinage ) ) PORT_CONDITION("DSW", 0x0400, PORTCOND_NOTEQUALS, 0x0000) PORT_DIPLOCATION("SW1:5,6,7,8") \
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PORT_DIPNAME( 0x00f0, 0x00f0, DEF_STR( Coinage ) ) PORT_CONDITION("DSW", 0x0400, PORTCOND_NOTEQUALS, 0x0000) PORT_DIPLOCATION("SW1:5,6,7,8") \
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PORT_DIPSETTING( 0x00a0, DEF_STR( 6C_1C ) ) \
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PORT_DIPSETTING( 0x00a0, DEF_STR( 6C_1C ) ) \
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@ -1867,12 +1864,9 @@ static MACHINE_DRIVER_START( m72_8751 )
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MDRV_IMPORT_FROM(m72_base)
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MDRV_IMPORT_FROM(m72_base)
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MDRV_CPU_ADD("mcu",I8751, MASTER_CLOCK/2)
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MDRV_CPU_ADD("mcu",I8751, MASTER_CLOCK/4)
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/* internal - MDRV_CPU_PROGRAM_MAP(mcu_map,0) */
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//MDRV_CPU_DATA_MAP(mcu_data_map,0)
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MDRV_CPU_IO_MAP(mcu_io_map,0)
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MDRV_CPU_IO_MAP(mcu_io_map,0)
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MDRV_CPU_VBLANK_INT("main", m72_mcu_int)
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MDRV_CPU_VBLANK_INT("main", m72_mcu_int)
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//MDRV_INTERLEAVE(1000)
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MACHINE_DRIVER_END
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MACHINE_DRIVER_END
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